diff mbox series

RISC-V: Fine tune vmadc/vmsbc RA constraint

Message ID 20230316093914.176248-1-juzhe.zhong@rivai.ai
State Committed
Headers
Series RISC-V: Fine tune vmadc/vmsbc RA constraint |

Commit Message

juzhe.zhong@rivai.ai March 16, 2023, 9:39 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/vector.md: Fix bug of vmsbc

---
 gcc/config/riscv/vector.md | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Jeff Law April 21, 2023, 8:40 p.m. UTC | #1 
On 3/16/23 03:39, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Fix bug of vmsbc
OK.  Please install on the trunk.

jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index a76e8286fe5..c100407d9fa 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -2600,14 +2600,14 @@ 
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
 
 (define_insn "@pred_msbc<mode>_overflow"
-  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr, &vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, vr, &vr, &vr")
 	(unspec:<VM>
 	   [(minus:VI
-	     (match_operand:VI 1 "register_operand"     "  %0,  vr,  vr")
-	     (match_operand:VI 2 "register_operand"     "vrvi,  vr,  vi"))
+	     (match_operand:VI 1 "register_operand"     "   0,  vr,  vr,  vr")
+	     (match_operand:VI 2 "register_operand"     "  vr,   0,  vr,  vi"))
 	    (unspec:<VM>
-	      [(match_operand 3 "vector_length_operand" "  rK,  rK,  rK")
-	       (match_operand 4 "const_int_operand"     "   i,   i,   i")
+	      [(match_operand 3 "vector_length_operand" "  rK,  rK,  rK,  rK")
+	       (match_operand 4 "const_int_operand"     "   i,   i,   i,   i")
 	       (reg:SI VL_REGNUM)
 	       (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"