diff mbox series

RISC-V: Fine tune merge operand constraint for integer/load/store

Message ID 20230308031856.174124-1-juzhe.zhong@rivai.ai
State Committed
Headers
Series RISC-V: Fine tune merge operand constraint for integer/load/store |

Commit Message

juzhe.zhong@rivai.ai March 8, 2023, 3:18 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins-bases.cc: Split indexed load patterns according to RVV ISA.
        * config/riscv/vector-iterators.md: New iterators.
        * config/riscv/vector.md (@pred_indexed_<order>load<VNX1_QHSD:mode><VNX1_QHSDI:mode>): Remove.
        (@pred_indexed_<order>load<mode>_same_eew): New pattern.
        (@pred_indexed_<order>load<mode>_x2_greater_eew): Ditto.
        (@pred_indexed_<order>load<mode>_x4_greater_eew): Ditto.
        (@pred_indexed_<order>load<mode>_x8_greater_eew): Ditto.
        (@pred_indexed_<order>load<mode>_x2_smaller_eew): Ditto.
        (@pred_indexed_<order>load<mode>_x4_smaller_eew): Ditto.
        (@pred_indexed_<order>load<mode>_x8_smaller_eew): Ditto.
        (@pred_indexed_<order>load<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Remove.
        (@pred_indexed_<order>load<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
        (@pred_indexed_<order>load<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
        (@pred_indexed_<order>load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
        (@pred_indexed_<order>load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
        (@pred_indexed_<order>load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/merge_constraint-1.c: New test.

---
 .../riscv/riscv-vector-builtins-bases.cc      |   54 +-
 gcc/config/riscv/vector-iterators.md          |  214 ++-
 gcc/config/riscv/vector.md                    | 1243 +++++++++--------
 .../riscv/rvv/base/merge_constraint-1.c       |  204 +++
 4 files changed, 1065 insertions(+), 650 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-1.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 532b2edbf2e..9f87f8c645a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -129,9 +129,57 @@  public:
 	    code_for_pred_indexed_store (unspec, e.vector_mode (),
 					 e.index_mode ()));
 	else
-	  return e.use_exact_insn (
-	    code_for_pred_indexed_load (unspec, e.vector_mode (),
-					e.index_mode ()));
+	  {
+	    unsigned src_eew_bitsize
+	      = GET_MODE_BITSIZE (GET_MODE_INNER (e.index_mode ()));
+	    unsigned dst_eew_bitsize
+	      = GET_MODE_BITSIZE (GET_MODE_INNER (e.vector_mode ()));
+	    if (dst_eew_bitsize == src_eew_bitsize)
+	      return e.use_exact_insn (
+		code_for_pred_indexed_load_same_eew (unspec, e.vector_mode ()));
+	    else if (dst_eew_bitsize > src_eew_bitsize)
+	      {
+		unsigned factor = dst_eew_bitsize / src_eew_bitsize;
+		switch (factor)
+		  {
+		  case 2:
+		    return e.use_exact_insn (
+		      code_for_pred_indexed_load_x2_greater_eew (
+			unspec, e.vector_mode ()));
+		  case 4:
+		    return e.use_exact_insn (
+		      code_for_pred_indexed_load_x4_greater_eew (
+			unspec, e.vector_mode ()));
+		  case 8:
+		    return e.use_exact_insn (
+		      code_for_pred_indexed_load_x8_greater_eew (
+			unspec, e.vector_mode ()));
+		  default:
+		    gcc_unreachable ();
+		  }
+	      }
+	    else
+	      {
+		unsigned factor = src_eew_bitsize / dst_eew_bitsize;
+		switch (factor)
+		  {
+		  case 2:
+		    return e.use_exact_insn (
+		      code_for_pred_indexed_load_x2_smaller_eew (
+			unspec, e.vector_mode ()));
+		  case 4:
+		    return e.use_exact_insn (
+		      code_for_pred_indexed_load_x4_smaller_eew (
+			unspec, e.vector_mode ()));
+		  case 8:
+		    return e.use_exact_insn (
+		      code_for_pred_indexed_load_x8_smaller_eew (
+			unspec, e.vector_mode ()));
+		  default:
+		    gcc_unreachable ();
+		  }
+	      }
+	  }
       }
     else if (LST_TYPE == LST_STRIDED)
       {
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 4dea46f4470..d44943ae7c3 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -99,6 +99,65 @@ 
   (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
 ])
 
+(define_mode_iterator VEEWEXT2 [
+  VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32")
+  VNx1SI VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32")
+  (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32")
+  (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32")
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+  (VNx1DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+])
+
+(define_mode_iterator VEEWEXT4 [
+  VNx1SI VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32")
+  (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32")
+  (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32")
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+  (VNx1DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+])
+
+(define_mode_iterator VEEWEXT8 [
+  (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32")
+  (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32")
+  (VNx1DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+])
+
+(define_mode_iterator VEEWTRUNC2 [
+  VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI
+  VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI
+  VNx1SI VNx2SI VNx4SI VNx8SI
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
+])
+
+(define_mode_iterator VEEWTRUNC4 [
+  VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI
+  VNx1HI VNx2HI VNx4HI VNx8HI
+])
+
+(define_mode_iterator VEEWTRUNC8 [
+  VNx1QI VNx2QI VNx4QI VNx8QI
+])
+
 (define_mode_iterator VLMULEXT2 [
   VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI
   VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI
@@ -484,6 +543,42 @@ 
   (VNx1DF "64") (VNx2DF "64") (VNx4DF "64") (VNx8DF "64")
 ])
 
+(define_mode_attr double_trunc_sew [
+  (VNx1HI "8") (VNx2HI "8") (VNx4HI "8") (VNx8HI "8") (VNx16HI "8") (VNx32HI "8")
+  (VNx1SI "16") (VNx2SI "16") (VNx4SI "16") (VNx8SI "16") (VNx16SI "16")
+  (VNx1DI "32") (VNx2DI "32") (VNx4DI "32") (VNx8DI "32")
+  (VNx1SF "16") (VNx2SF "16") (VNx4SF "16") (VNx8SF "16") (VNx16SF "16")
+  (VNx1DF "32") (VNx2DF "32") (VNx4DF "32") (VNx8DF "32")
+])
+
+(define_mode_attr quad_trunc_sew [
+  (VNx1SI "8") (VNx2SI "8") (VNx4SI "8") (VNx8SI "8") (VNx16SI "8")
+  (VNx1DI "16") (VNx2DI "16") (VNx4DI "16") (VNx8DI "16")
+  (VNx1SF "8") (VNx2SF "8") (VNx4SF "8") (VNx8SF "8") (VNx16SF "8")
+  (VNx1DF "16") (VNx2DF "16") (VNx4DF "16") (VNx8DF "16")
+])
+
+(define_mode_attr oct_trunc_sew [
+  (VNx1DI "8") (VNx2DI "8") (VNx4DI "8") (VNx8DI "8")
+  (VNx1DF "8") (VNx2DF "8") (VNx4DF "8") (VNx8DF "8")
+])
+
+(define_mode_attr double_ext_sew [
+  (VNx1QI "16") (VNx2QI "16") (VNx4QI "16") (VNx8QI "16") (VNx16QI "16") (VNx32QI "16")
+  (VNx1HI "32") (VNx2HI "32") (VNx4HI "32") (VNx8HI "32") (VNx16HI "32")
+  (VNx1SI "64") (VNx2SI "64") (VNx4SI "64") (VNx8SI "64")
+  (VNx1SF "64") (VNx2SF "64") (VNx4SF "64") (VNx8SF "64")
+])
+
+(define_mode_attr quad_ext_sew [
+  (VNx1QI "32") (VNx2QI "32") (VNx4QI "32") (VNx8QI "32") (VNx16QI "32")
+  (VNx1HI "64") (VNx2HI "64") (VNx4HI "64") (VNx8HI "64")
+])
+
+(define_mode_attr oct_ext_sew [
+  (VNx1QI "64") (VNx2QI "64") (VNx4QI "64") (VNx8QI "64")
+])
+
 (define_mode_attr V_DOUBLE_TRUNC [
   (VNx1HI "VNx1QI") (VNx2HI "VNx2QI")  (VNx4HI "VNx4QI")  (VNx8HI "VNx8QI")
   (VNx16HI "VNx16QI") (VNx32HI "VNx32QI")
@@ -504,6 +599,49 @@ 
   (VNx1DI "VNx1QI") (VNx2DI "VNx2QI") (VNx4DI "VNx4QI") (VNx8DI "VNx8QI")
 ])
 
+(define_mode_attr VINDEX_DOUBLE_TRUNC [
+  (VNx1HI "VNx1QI") (VNx2HI "VNx2QI")  (VNx4HI "VNx4QI")  (VNx8HI "VNx8QI")
+  (VNx16HI "VNx16QI") (VNx32HI "VNx32QI")
+  (VNx1SI "VNx1HI") (VNx2SI "VNx2HI") (VNx4SI "VNx4HI") (VNx8SI "VNx8HI")
+  (VNx16SI "VNx16HI")
+  (VNx1SF "VNx1HI") (VNx2SF "VNx2HI") (VNx4SF "VNx4HI") (VNx8SF "VNx8HI")
+  (VNx16SF "VNx16HI")
+  (VNx1DI "VNx1SI") (VNx2DI "VNx2SI") (VNx4DI "VNx4SI") (VNx8DI "VNx8SI")
+  (VNx1DF "VNx1SI") (VNx2DF "VNx2SI") (VNx4DF "VNx4SI") (VNx8DF "VNx8SI")
+])
+
+(define_mode_attr VINDEX_QUAD_TRUNC [
+  (VNx1SI "VNx1QI") (VNx2SI "VNx2QI") (VNx4SI "VNx4QI") (VNx8SI "VNx8QI")
+  (VNx16SI "VNx16QI")
+  (VNx1DI "VNx1HI") (VNx2DI "VNx2HI")
+  (VNx4DI "VNx4HI") (VNx8DI "VNx8HI")
+  (VNx1SF "VNx1QI") (VNx2SF "VNx2QI") (VNx4SF "VNx4QI") (VNx8SF "VNx8QI")
+  (VNx16SF "VNx16QI")
+  (VNx1DF "VNx1HI") (VNx2DF "VNx2HI")
+  (VNx4DF "VNx4HI") (VNx8DF "VNx8HI")
+])
+
+(define_mode_attr VINDEX_OCT_TRUNC [
+  (VNx1DI "VNx1QI") (VNx2DI "VNx2QI") (VNx4DI "VNx4QI") (VNx8DI "VNx8QI")
+  (VNx1DF "VNx1QI") (VNx2DF "VNx2QI") (VNx4DF "VNx4QI") (VNx8DF "VNx8QI")
+])
+
+(define_mode_attr VINDEX_DOUBLE_EXT [
+  (VNx1QI "VNx1HI") (VNx2QI "VNx2HI") (VNx4QI "VNx4HI") (VNx8QI "VNx8HI") (VNx16QI "VNx16HI") (VNx32QI "VNx32HI")
+  (VNx1HI "VNx1SI") (VNx2HI "VNx2SI") (VNx4HI "VNx4SI") (VNx8HI "VNx8SI") (VNx16HI "VNx16SI")
+  (VNx1SI "VNx1DI") (VNx2SI "VNx2DI") (VNx4SI "VNx4DI") (VNx8SI "VNx8DI")
+  (VNx1SF "VNx1DI") (VNx2SF "VNx2DI") (VNx4SF "VNx4DI") (VNx8SF "VNx8DI")
+])
+
+(define_mode_attr VINDEX_QUAD_EXT [
+  (VNx1QI "VNx1SI") (VNx2QI "VNx2SI") (VNx4QI "VNx4SI") (VNx8QI "VNx8SI") (VNx16QI "VNx16SI")
+  (VNx1HI "VNx1DI") (VNx2HI "VNx2DI") (VNx4HI "VNx4DI") (VNx8HI "VNx8DI")
+])
+
+(define_mode_attr VINDEX_OCT_EXT [
+  (VNx1QI "VNx1DI") (VNx2QI "VNx2DI") (VNx4QI "VNx4DI") (VNx8QI "VNx8DI")
+])
+
 (define_mode_attr VCONVERT [
   (VNx1SF "VNx1SI") (VNx2SF "VNx2SI") (VNx4SF "VNx4SI") (VNx8SF "VNx8SI") (VNx16SF "VNx16SI")
   (VNx1DF "VNx1DI") (VNx2DF "VNx2DI") (VNx4DF "VNx4DI") (VNx8DF "VNx8DI")
@@ -772,46 +910,46 @@ 
 			(us_minus "register_operand")])
 
 (define_code_attr binop_rhs1_constraint [
-			(plus "vr,vr,vr,vr,vr,vr")
-			(minus "vr,vr,vr,vr,vi,vi")
-			(ior "vr,vr,vr,vr,vr,vr")
-			(xor "vr,vr,vr,vr,vr,vr")
-			(and "vr,vr,vr,vr,vr,vr")
-			(ashift "vr,vr,vr,vr,vr,vr")
-			(ashiftrt "vr,vr,vr,vr,vr,vr")
-			(lshiftrt "vr,vr,vr,vr,vr,vr")
-			(smin "vr,vr,vr,vr,vr,vr")
-			(smax "vr,vr,vr,vr,vr,vr")
-			(umin "vr,vr,vr,vr,vr,vr")
-			(umax "vr,vr,vr,vr,vr,vr")
-			(mult "vr,vr,vr,vr,vr,vr")
-			(div "vr,vr,vr,vr,vr,vr")
-			(mod "vr,vr,vr,vr,vr,vr")
-			(udiv "vr,vr,vr,vr,vr,vr")
-			(umod "vr,vr,vr,vr,vr,vr")])
+			(plus "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(minus "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi")
+			(ior "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(xor "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(and "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(ashift "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(ashiftrt "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(lshiftrt "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(smin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(smax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(umin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(umax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(mult "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(div "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(mod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(udiv "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(umod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")])
 
 (define_code_attr binop_rhs2_constraint [
-			(plus "vr,vr,vi,vi,vr,vr")
-			(minus "vr,vr,vj,vj,vr,vr")
-			(ior "vr,vr,vi,vi,vr,vr")
-			(xor "vr,vr,vi,vi,vr,vr")
-			(and "vr,vr,vi,vi,vr,vr")
-			(ashift "vr,vr,vk,vk,vr,vr")
-			(ashiftrt "vr,vr,vk,vk,vr,vr")
-			(lshiftrt "vr,vr,vk,vk,vr,vr")
-			(smin "vr,vr,vr,vr,vr,vr")
-			(smax "vr,vr,vr,vr,vr,vr")
-			(umin "vr,vr,vr,vr,vr,vr")
-			(umax "vr,vr,vr,vr,vr,vr")
-			(mult "vr,vr,vr,vr,vr,vr")
-			(div "vr,vr,vr,vr,vr,vr")
-			(mod "vr,vr,vr,vr,vr,vr")
-			(udiv "vr,vr,vr,vr,vr,vr")
-			(umod "vr,vr,vr,vr,vr,vr")
-			(ss_plus "vr,vr,vi,vi")
-			(us_plus "vr,vr,vi,vi")
-			(ss_minus "vr,vr,vj,vj")
-			(us_minus "vr,vr,vr,vr")])
+			(plus "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
+			(minus "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr")
+			(ior "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
+			(xor "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
+			(and "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
+			(ashift "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr")
+			(ashiftrt "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr")
+			(lshiftrt "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr")
+			(smin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(smax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(umin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(umax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(mult "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(div "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(mod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(udiv "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(umod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
+			(ss_plus "vr,vr,vr,vr,vi,vi,vi,vi")
+			(us_plus "vr,vr,vr,vr,vi,vi,vi,vi")
+			(ss_minus "vr,vr,vr,vr,vj,vj,vj,vj")
+			(us_minus "vr,vr,vr,vr,vr,vr,vr,vr")])
 
 (define_code_attr int_binop_insn_type [
 			(plus "vialu")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3f8ad32fbc0..a4a68b67e24 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -906,18 +906,18 @@ 
 ;;               (nil)))))
 ;; Since both vmv.v.v and vmv.v.i doesn't have mask operand.
 (define_insn_and_split "@pred_mov<mode>"
-  [(set (match_operand:V 0 "nonimmediate_operand"      "=vr,    vr,    vd,     m,    vr,    vr")
+  [(set (match_operand:V 0 "nonimmediate_operand"      "=vr,    vr,    vd,     m,    vr,    vr,    vr,    vr")
     (if_then_else:V
       (unspec:<VM>
-        [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,   Wc1,    vm, vmWc1,   Wc1,   Wc1")
-         (match_operand 4 "vector_length_operand"    "   rK,    rK,    rK,    rK,    rK,    rK")
-         (match_operand 5 "const_int_operand"        "    i,     i,     i,     i,     i,     i")
-         (match_operand 6 "const_int_operand"        "    i,     i,     i,     i,     i,     i")
-         (match_operand 7 "const_int_operand"        "    i,     i,     i,     i,     i,     i")
+        [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,   Wc1,    vm, vmWc1,   Wc1,   Wc1,   Wc1,   Wc1")
+         (match_operand 4 "vector_length_operand"    "   rK,    rK,    rK,    rK,    rK,    rK,    rK,    rK")
+         (match_operand 5 "const_int_operand"        "    i,     i,     i,     i,     i,     i,     i,     i")
+         (match_operand 6 "const_int_operand"        "    i,     i,     i,     i,     i,     i,     i,     i")
+         (match_operand 7 "const_int_operand"        "    i,     i,     i,     i,     i,     i,     i,     i")
          (reg:SI VL_REGNUM)
          (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-      (match_operand:V 3 "vector_move_operand"       "    m,     m,     m,    vr,    vr, viWc0")
-      (match_operand:V 2 "vector_merge_operand"      "    0,    vu,    vu,    vu,   vu0,   vu0")))]
+      (match_operand:V 3 "vector_move_operand"       "    m,     m,     m,    vr,    vr,    vr, viWc0, viWc0")
+      (match_operand:V 2 "vector_merge_operand"      "    0,    vu,    vu,    vu,    vu,     0,    vu,     0")))]
   "TARGET_VECTOR && (MEM_P (operands[0]) || MEM_P (operands[3])
    || CONST_VECTOR_P (operands[1]))"
   "@
@@ -926,6 +926,8 @@ 
    vle<sew>.v\t%0,%3,%1.t
    vse<sew>.v\t%3,%0%p1
    vmv.v.v\t%0,%3
+   vmv.v.v\t%0,%3
+   vmv.v.i\t%0,%v3
    vmv.v.i\t%0,%v3"
   "&& register_operand (operands[0], <MODE>mode)
    && register_operand (operands[3], <MODE>mode)
@@ -933,7 +935,7 @@ 
    && INTVAL (operands[7]) == riscv_vector::VLMAX"
   [(set (match_dup 0) (match_dup 3))]
   ""
-  [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov")
+  [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov,vimov,vimov")
    (set_attr "mode" "<MODE>")])
 
 ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include
@@ -1006,41 +1008,41 @@ 
    (set_attr "vl_op_idx" "3")])
 
 (define_insn "@pred_merge<mode>"
-  [(set (match_operand:V 0 "register_operand"            "=vd,    vd")
+  [(set (match_operand:V 0 "register_operand"          "=vd,vd,vd,vd")
     (if_then_else:V
-      (match_operand:<VM> 4 "register_operand"         "   vm,    vm")
+      (match_operand:<VM> 4 "register_operand"         " vm,vm,vm,vm")
       (if_then_else:V
         (unspec:<VM>
           [(match_dup 4)
-           (match_operand 5 "vector_length_operand"    "   rK,    rK")
-           (match_operand 6 "const_int_operand"        "    i,     i")
-           (match_operand 7 "const_int_operand"        "    i,     i")
+           (match_operand 5 "vector_length_operand"    " rK,rK,rK,rK")
+           (match_operand 6 "const_int_operand"        "  i, i, i, i")
+           (match_operand 7 "const_int_operand"        "  i, i, i, i")
            (reg:SI VL_REGNUM)
            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-        (match_operand:V 3 "vector_arith_operand"      "   vr,    vi")
-        (match_operand:V 2 "register_operand"          "   vr,    vr"))
-      (match_operand:V 1 "vector_merge_operand"        "  0vu,   0vu")))]
+        (match_operand:V 3 "vector_arith_operand"      " vr,vr,vi,vi")
+        (match_operand:V 2 "register_operand"          " vr,vr,vr,vr"))
+      (match_operand:V 1 "vector_merge_operand"        " vu, 0,vu, 0")))]
   "TARGET_VECTOR"
   "vmerge.v%o3m\t%0,%2,%v3,%4"
   [(set_attr "type" "vimerge")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_merge<mode>_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"   "=vd")
+  [(set (match_operand:VI_QHS 0 "register_operand"   "=vd,vd")
     (if_then_else:VI_QHS
-      (match_operand:<VM> 4 "register_operand"       " vm")
+      (match_operand:<VM> 4 "register_operand"       " vm,vm")
       (if_then_else:VI_QHS
         (unspec:<VM>
           [(match_dup 4)
-           (match_operand 5 "vector_length_operand"  " rK")
-           (match_operand 6 "const_int_operand"      "  i")
-           (match_operand 7 "const_int_operand"      "  i")
+           (match_operand 5 "vector_length_operand"  " rK,rK")
+           (match_operand 6 "const_int_operand"      "  i, i")
+           (match_operand 7 "const_int_operand"      "  i, i")
            (reg:SI VL_REGNUM)
            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	(vec_duplicate:VI_QHS
-          (match_operand:<VEL> 3 "register_operand"  "  r"))
-        (match_operand:VI_QHS 2 "register_operand"   " vr"))
-      (match_operand:VI_QHS 1 "vector_merge_operand" "0vu")))]
+          (match_operand:<VEL> 3 "register_operand"  "  r, r"))
+        (match_operand:VI_QHS 2 "register_operand"   " vr,vr"))
+      (match_operand:VI_QHS 1 "vector_merge_operand" " vu, 0")))]
   "TARGET_VECTOR"
   "vmerge.vxm\t%0,%2,%3,%4"
   [(set_attr "type" "vimerge")
@@ -1080,43 +1082,43 @@ 
 })
 
 (define_insn "*pred_merge<mode>_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"     "=vd")
+  [(set (match_operand:VI_D 0 "register_operand"     "=vd,vd")
     (if_then_else:VI_D
-      (match_operand:<VM> 4 "register_operand"       " vm")
+      (match_operand:<VM> 4 "register_operand"       " vm,vm")
       (if_then_else:VI_D
         (unspec:<VM>
           [(match_dup 4)
-           (match_operand 5 "vector_length_operand"  " rK")
-           (match_operand 6 "const_int_operand"      "  i")
-           (match_operand 7 "const_int_operand"      "  i")
+           (match_operand 5 "vector_length_operand"  " rK,rK")
+           (match_operand 6 "const_int_operand"      "  i, i")
+           (match_operand 7 "const_int_operand"      "  i, i")
            (reg:SI VL_REGNUM)
            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	(vec_duplicate:VI_D
-          (match_operand:<VEL> 3 "register_operand" "  r"))
-        (match_operand:VI_D 2 "register_operand"     " vr"))
-      (match_operand:VI_D 1 "vector_merge_operand"   "0vu")))]
+          (match_operand:<VEL> 3 "register_operand"  "  r, r"))
+        (match_operand:VI_D 2 "register_operand"     " vr,vr"))
+      (match_operand:VI_D 1 "vector_merge_operand"   " vu, 0")))]
   "TARGET_VECTOR"
   "vmerge.vxm\t%0,%2,%3,%4"
   [(set_attr "type" "vimerge")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_merge<mode>_extended_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"     "=vd")
+  [(set (match_operand:VI_D 0 "register_operand"         "=vd,vd")
     (if_then_else:VI_D
-      (match_operand:<VM> 4 "register_operand"       " vm")
+      (match_operand:<VM> 4 "register_operand"           " vm,vm")
       (if_then_else:VI_D
         (unspec:<VM>
           [(match_dup 4)
-           (match_operand 5 "vector_length_operand"  " rK")
-           (match_operand 6 "const_int_operand"      "  i")
-           (match_operand 7 "const_int_operand"      "  i")
+           (match_operand 5 "vector_length_operand"      " rK,rK")
+           (match_operand 6 "const_int_operand"          "  i, i")
+           (match_operand 7 "const_int_operand"          "  i, i")
            (reg:SI VL_REGNUM)
            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	(vec_duplicate:VI_D
 	  (sign_extend:<VEL>
-            (match_operand:<VSUBEL> 3 "register_operand" "  r")))
-        (match_operand:VI_D 2 "register_operand"     " vr"))
-      (match_operand:VI_D 1 "vector_merge_operand"   "0vu")))]
+            (match_operand:<VSUBEL> 3 "register_operand" "  r, r")))
+        (match_operand:VI_D 2 "register_operand"         " vr,vr"))
+      (match_operand:VI_D 1 "vector_merge_operand"       " vu, 0")))]
   "TARGET_VECTOR"
   "vmerge.vxm\t%0,%2,%3,%4"
   [(set_attr "type" "vimerge")
@@ -1186,24 +1188,28 @@ 
 })
 
 (define_insn_and_split "*pred_broadcast<mode>"
-  [(set (match_operand:VI 0 "register_operand"                     "=vr,   vd,  vr,  vr")
+  [(set (match_operand:VI 0 "register_operand"                     "=vr, vr, vd, vd, vr, vr, vr, vr")
 	(if_then_else:VI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_broadcast_mask_operand" " Wc1,  vm, Wc1, Wb1")
-	     (match_operand 4 "vector_length_operand"              " rK,   rK,  rK,  rK")
-	     (match_operand 5 "const_int_operand"                  "  i,    i,   i,   i")
-	     (match_operand 6 "const_int_operand"                  "  i,    i,   i,   i")
-	     (match_operand 7 "const_int_operand"                  "  i,    i,   i,   i")
+	    [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
+	     (match_operand 4 "vector_length_operand"              " rK, rK, rK, rK, rK, rK, rK, rK")
+	     (match_operand 5 "const_int_operand"                  "  i,  i,  i,  i,  i,  i,  i,  i")
+	     (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i,  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i,  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (vec_duplicate:VI
-	    (match_operand:<VEL> 3 "direct_broadcast_operand"       "  r, Wdm, Wdm,   r"))
-	  (match_operand:VI 2 "vector_merge_operand"                "0vu, 0vu, 0vu, 0vu")))]
+	    (match_operand:<VEL> 3 "direct_broadcast_operand"       " r,  r,Wdm,Wdm,Wdm,Wdm,  r,  r"))
+	  (match_operand:VI 2 "vector_merge_operand"                "vu,  0, vu,  0, vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "@
    vmv.v.x\t%0,%3
+   vmv.v.x\t%0,%3
+   vlse<sew>.v\t%0,%3,zero,%1.t
    vlse<sew>.v\t%0,%3,zero,%1.t
    vlse<sew>.v\t%0,%3,zero
+   vlse<sew>.v\t%0,%3,zero
+   vmv.s.x\t%0,%3
    vmv.s.x\t%0,%3"
   "register_operand (operands[3], <VEL>mode)
   && GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)"
@@ -1234,52 +1240,58 @@ 
 	operands[1] = CONSTM1_RTX (<VM>mode);
       }
   }
-  [(set_attr "type" "vimov,vlds,vlds,vimovxv")
+  [(set_attr "type" "vimov,vimov,vlds,vlds,vlds,vlds,vimovxv,vimovxv")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_broadcast<mode>"
-  [(set (match_operand:VF 0 "register_operand"                     "=vr,   vr,  vr,  vr")
+  [(set (match_operand:VF 0 "register_operand"                     "=vr, vr, vr, vr, vr, vr, vr, vr")
 	(if_then_else:VF
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_broadcast_mask_operand" " Wc1,  vm, Wc1, Wb1")
-	     (match_operand 4 "vector_length_operand"              " rK,   rK,  rK,  rK")
-	     (match_operand 5 "const_int_operand"                  "  i,    i,   i,   i")
-	     (match_operand 6 "const_int_operand"                  "  i,    i,   i,   i")
-	     (match_operand 7 "const_int_operand"                  "  i,    i,   i,   i")
+	    [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
+	     (match_operand 4 "vector_length_operand"              " rK, rK, rK, rK, rK, rK, rK, rK")
+	     (match_operand 5 "const_int_operand"                  "  i,  i,  i,  i,  i,  i,  i,  i")
+	     (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i,  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i,  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (vec_duplicate:VF
-	    (match_operand:<VEL> 3 "direct_broadcast_operand"       "  f, Wdm, Wdm,   f"))
-	  (match_operand:VF 2 "vector_merge_operand"                "0vu, 0vu, 0vu, 0vu")))]
+	    (match_operand:<VEL> 3 "direct_broadcast_operand"       " f,  f,Wdm,Wdm,Wdm,Wdm,  f,  f"))
+	  (match_operand:VF 2 "vector_merge_operand"                "vu,  0, vu,  0, vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "@
+   vfmv.v.f\t%0,%3
    vfmv.v.f\t%0,%3
    vlse<sew>.v\t%0,%3,zero,%1.t
+   vlse<sew>.v\t%0,%3,zero,%1.t
+   vlse<sew>.v\t%0,%3,zero
    vlse<sew>.v\t%0,%3,zero
+   vfmv.s.f\t%0,%3
    vfmv.s.f\t%0,%3"
-  [(set_attr "type" "vfmov,vlds,vlds,vfmovfv")
+  [(set_attr "type" "vfmov,vfmov,vlds,vlds,vlds,vlds,vfmovfv,vfmovfv")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_broadcast<mode>_extended_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"                     "=vr,   vr")
+  [(set (match_operand:VI_D 0 "register_operand"                   "=vr, vr, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_broadcast_mask_operand" " Wc1, Wb1")
-	     (match_operand 4 "vector_length_operand"              " rK,   rK")
-	     (match_operand 5 "const_int_operand"                  "  i,    i")
-	     (match_operand 6 "const_int_operand"                  "  i,    i")
-	     (match_operand 7 "const_int_operand"                  "  i,    i")
+	    [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1,Wb1,Wb1")
+	     (match_operand 4 "vector_length_operand"              " rK, rK, rK, rK")
+	     (match_operand 5 "const_int_operand"                  "  i,  i,  i,  i")
+	     (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (vec_duplicate:VI_D
 	    (sign_extend:<VEL>
-	      (match_operand:<VSUBEL> 3 "register_operand"          "  r,   r")))
-	  (match_operand:VI_D 2 "vector_merge_operand"              "0vu, 0vu")))]
+	      (match_operand:<VSUBEL> 3 "register_operand"          " r,  r,  r,  r")))
+	  (match_operand:VI_D 2 "vector_merge_operand"              "vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "@
    vmv.v.x\t%0,%3
+   vmv.v.x\t%0,%3
+   vmv.s.x\t%0,%3
    vmv.s.x\t%0,%3"
-  [(set_attr "type" "vimov,vimovxv")
+  [(set_attr "type" "vimov,vimov,vimovxv,vimovxv")
    (set_attr "mode" "<MODE>")])
 
 ;; -------------------------------------------------------------------------------
@@ -1332,26 +1344,155 @@ 
 ;; - 7.6. Vector Indexed Instructions
 ;; -------------------------------------------------------------------------------
 
-(define_insn "@pred_indexed_<order>load<VNX1_QHSD:mode><VNX1_QHSDI:mode>"
-  [(set (match_operand:VNX1_QHSD 0 "register_operand"      "=&vr")
-	(if_then_else:VNX1_QHSD
+;; DEST eew is same as SOURCE eew, DEST register can overlap SOURCE.
+(define_insn "@pred_indexed_<order>load<mode>_same_eew"
+  [(set (match_operand:V 0 "register_operand"             "=vd, vr,vd, vr")
+	(if_then_else:V
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"  "vmWc1")
-	     (match_operand 5 "vector_length_operand"     "   rK")
-	     (match_operand 6 "const_int_operand"         "    i")
-	     (match_operand 7 "const_int_operand"         "    i")
-	     (match_operand 8 "const_int_operand"         "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"  " vm,Wc1,vm,Wc1")
+	     (match_operand 5 "vector_length_operand"     " rK, rK,rK, rK")
+	     (match_operand 6 "const_int_operand"         "  i,  i, i,  i")
+	     (match_operand 7 "const_int_operand"         "  i,  i, i,  i")
+	     (match_operand 8 "const_int_operand"         "  i,  i, i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VNX1_QHSD
-	    [(match_operand 3 "pmode_register_operand"    "    r")
+	  (unspec:V
+	    [(match_operand 3 "pmode_register_operand"    "  r,  r, r,  r")
 	     (mem:BLK (scratch))
-	     (match_operand:VNX1_QHSDI 4 "register_operand" " vr")] ORDER)
-	  (match_operand:VNX1_QHSD 2 "vector_merge_operand" "0vu")))]
+	     (match_operand:<VINDEX> 4 "register_operand" " vr, vr,vr, vr")] ORDER)
+	  (match_operand:V 2 "vector_merge_operand"       " vu, vu, 0,  0")))]
   "TARGET_VECTOR"
-  "vl<order>xei<VNX1_QHSDI:sew>.v\t%0,(%3),%4%p1"
+  "vl<order>xei<sew>.v\t%0,(%3),%4%p1"
   [(set_attr "type" "vld<order>x")
-   (set_attr "mode" "<VNX1_QHSD:MODE>")])
+   (set_attr "mode" "<MODE>")])
+
+;; DEST eew is greater than SOURCE eew.
+(define_insn "@pred_indexed_<order>load<mode>_x2_greater_eew"
+  [(set (match_operand:VEEWEXT2 0 "register_operand"                    "=&vr,  &vr")
+	(if_then_else:VEEWEXT2
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"               "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"                  "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                      "    i,    i")
+	     (match_operand 7 "const_int_operand"                      "    i,    i")
+	     (match_operand 8 "const_int_operand"                      "    i,    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (unspec:VEEWEXT2
+	    [(match_operand 3 "pmode_register_operand"                 "    r,    r")
+	     (mem:BLK (scratch))
+	     (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")] ORDER)
+	  (match_operand:VEEWEXT2 2 "vector_merge_operand"             "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vl<order>xei<double_trunc_sew>.v\t%0,(%3),%4%p1"
+  [(set_attr "type" "vld<order>x")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "@pred_indexed_<order>load<mode>_x4_greater_eew"
+  [(set (match_operand:VEEWEXT4 0 "register_operand"                    "=&vr,  &vr")
+	(if_then_else:VEEWEXT4
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"               "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"                  "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                      "    i,    i")
+	     (match_operand 7 "const_int_operand"                      "    i,    i")
+	     (match_operand 8 "const_int_operand"                      "    i,    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (unspec:VEEWEXT4
+	    [(match_operand 3 "pmode_register_operand"                 "    r,    r")
+	     (mem:BLK (scratch))
+	     (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand"   "   vr,   vr")] ORDER)
+	  (match_operand:VEEWEXT4 2 "vector_merge_operand"             "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vl<order>xei<quad_trunc_sew>.v\t%0,(%3),%4%p1"
+  [(set_attr "type" "vld<order>x")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "@pred_indexed_<order>load<mode>_x8_greater_eew"
+  [(set (match_operand:VEEWEXT8 0 "register_operand"                    "=&vr,  &vr")
+	(if_then_else:VEEWEXT8
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"               "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"                  "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                      "    i,    i")
+	     (match_operand 7 "const_int_operand"                      "    i,    i")
+	     (match_operand 8 "const_int_operand"                      "    i,    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (unspec:VEEWEXT8
+	    [(match_operand 3 "pmode_register_operand"                 "    r,    r")
+	     (mem:BLK (scratch))
+	     (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand"    "   vr,   vr")] ORDER)
+	  (match_operand:VEEWEXT8 2 "vector_merge_operand"             "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vl<order>xei<oct_trunc_sew>.v\t%0,(%3),%4%p1"
+  [(set_attr "type" "vld<order>x")
+   (set_attr "mode" "<MODE>")])
+
+;; DEST eew is smaller than SOURCE eew.
+(define_insn "@pred_indexed_<order>load<mode>_x2_smaller_eew"
+  [(set (match_operand:VEEWTRUNC2 0 "register_operand"                "=&vr,  &vr")
+	(if_then_else:VEEWTRUNC2
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"             "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"                "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                    "    i,    i")
+	     (match_operand 7 "const_int_operand"                    "    i,    i")
+	     (match_operand 8 "const_int_operand"                    "    i,    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (unspec:VEEWTRUNC2
+	    [(match_operand 3 "pmode_register_operand"               "    r,    r")
+	     (mem:BLK (scratch))
+	     (match_operand:<VINDEX_DOUBLE_EXT> 4 "register_operand" "   vr,   vr")] ORDER)
+	  (match_operand:VEEWTRUNC2 2 "vector_merge_operand"         "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vl<order>xei<double_ext_sew>.v\t%0,(%3),%4%p1"
+  [(set_attr "type" "vld<order>x")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "@pred_indexed_<order>load<mode>_x4_smaller_eew"
+  [(set (match_operand:VEEWTRUNC4 0 "register_operand"              "=&vr,  &vr")
+	(if_then_else:VEEWTRUNC4
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                  "    i,    i")
+	     (match_operand 7 "const_int_operand"                  "    i,    i")
+	     (match_operand 8 "const_int_operand"                  "    i,    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (unspec:VEEWTRUNC4
+	    [(match_operand 3 "pmode_register_operand"             "    r,    r")
+	     (mem:BLK (scratch))
+	     (match_operand:<VINDEX_QUAD_EXT> 4 "register_operand" "   vr,   vr")] ORDER)
+	  (match_operand:VEEWTRUNC4 2 "vector_merge_operand"       "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vl<order>xei<quad_ext_sew>.v\t%0,(%3),%4%p1"
+  [(set_attr "type" "vld<order>x")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "@pred_indexed_<order>load<mode>_x8_smaller_eew"
+  [(set (match_operand:VEEWTRUNC8 0 "register_operand"             "=&vr,  &vr")
+	(if_then_else:VEEWTRUNC8
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"          "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"             "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                 "    i,    i")
+	     (match_operand 7 "const_int_operand"                 "    i,    i")
+	     (match_operand 8 "const_int_operand"                 "    i,    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (unspec:VEEWTRUNC8
+	    [(match_operand 3 "pmode_register_operand"            "    r,    r")
+	     (mem:BLK (scratch))
+	     (match_operand:<VINDEX_OCT_EXT> 4 "register_operand" "   vr,   vr")] ORDER)
+	  (match_operand:VEEWTRUNC8 2 "vector_merge_operand"      "   vu,    0")))]
+  "TARGET_VECTOR"
+  "vl<order>xei<oct_ext_sew>.v\t%0,(%3),%4%p1"
+  [(set_attr "type" "vld<order>x")
+   (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_indexed_<order>store<VNX1_QHSD:mode><VNX1_QHSDI:mode>"
   [(set (mem:BLK (scratch))
@@ -1370,27 +1511,6 @@ 
   [(set_attr "type" "vst<order>x")
    (set_attr "mode" "<VNX1_QHSD:MODE>")])
 
-(define_insn "@pred_indexed_<order>load<VNX2_QHSD:mode><VNX2_QHSDI:mode>"
-  [(set (match_operand:VNX2_QHSD 0 "register_operand"      "=&vr")
-	(if_then_else:VNX2_QHSD
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"  "vmWc1")
-	     (match_operand 5 "vector_length_operand"     "   rK")
-	     (match_operand 6 "const_int_operand"         "    i")
-	     (match_operand 7 "const_int_operand"         "    i")
-	     (match_operand 8 "const_int_operand"         "    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VNX2_QHSD
-	    [(match_operand 3 "pmode_register_operand"    "    r")
-	     (mem:BLK (scratch))
-	     (match_operand:VNX2_QHSDI 4 "register_operand" " vr")] ORDER)
-	  (match_operand:VNX2_QHSD 2 "vector_merge_operand" "0vu")))]
-  "TARGET_VECTOR"
-  "vl<order>xei<VNX2_QHSDI:sew>.v\t%0,(%3),%4%p1"
-  [(set_attr "type" "vld<order>x")
-   (set_attr "mode" "<VNX2_QHSD:MODE>")])
-
 (define_insn "@pred_indexed_<order>store<VNX2_QHSD:mode><VNX2_QHSDI:mode>"
   [(set (mem:BLK (scratch))
 	(unspec:BLK
@@ -1408,27 +1528,6 @@ 
   [(set_attr "type" "vst<order>x")
    (set_attr "mode" "<VNX2_QHSD:MODE>")])
 
-(define_insn "@pred_indexed_<order>load<VNX4_QHSD:mode><VNX4_QHSDI:mode>"
-  [(set (match_operand:VNX4_QHSD 0 "register_operand"      "=&vr")
-	(if_then_else:VNX4_QHSD
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"  "vmWc1")
-	     (match_operand 5 "vector_length_operand"     "   rK")
-	     (match_operand 6 "const_int_operand"         "    i")
-	     (match_operand 7 "const_int_operand"         "    i")
-	     (match_operand 8 "const_int_operand"         "    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VNX4_QHSD
-	    [(match_operand 3 "pmode_register_operand"    "    r")
-	     (mem:BLK (scratch))
-	     (match_operand:VNX4_QHSDI 4 "register_operand" " vr")] ORDER)
-	  (match_operand:VNX4_QHSD 2 "vector_merge_operand" "0vu")))]
-  "TARGET_VECTOR"
-  "vl<order>xei<VNX4_QHSDI:sew>.v\t%0,(%3),%4%p1"
-  [(set_attr "type" "vld<order>x")
-   (set_attr "mode" "<VNX4_QHSD:MODE>")])
-
 (define_insn "@pred_indexed_<order>store<VNX4_QHSD:mode><VNX4_QHSDI:mode>"
   [(set (mem:BLK (scratch))
 	(unspec:BLK
@@ -1446,27 +1545,6 @@ 
   [(set_attr "type" "vst<order>x")
    (set_attr "mode" "<VNX4_QHSD:MODE>")])
 
-(define_insn "@pred_indexed_<order>load<VNX8_QHSD:mode><VNX8_QHSDI:mode>"
-  [(set (match_operand:VNX8_QHSD 0 "register_operand"      "=&vr")
-	(if_then_else:VNX8_QHSD
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"  "vmWc1")
-	     (match_operand 5 "vector_length_operand"     "   rK")
-	     (match_operand 6 "const_int_operand"         "    i")
-	     (match_operand 7 "const_int_operand"         "    i")
-	     (match_operand 8 "const_int_operand"         "    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VNX8_QHSD
-	    [(match_operand 3 "pmode_register_operand"    "    r")
-	     (mem:BLK (scratch))
-	     (match_operand:VNX8_QHSDI 4 "register_operand" " vr")] ORDER)
-	  (match_operand:VNX8_QHSD 2 "vector_merge_operand" "0vu")))]
-  "TARGET_VECTOR"
-  "vl<order>xei<VNX8_QHSDI:sew>.v\t%0,(%3),%4%p1"
-  [(set_attr "type" "vld<order>x")
-   (set_attr "mode" "<VNX8_QHSD:MODE>")])
-
 (define_insn "@pred_indexed_<order>store<VNX8_QHSD:mode><VNX8_QHSDI:mode>"
   [(set (mem:BLK (scratch))
 	(unspec:BLK
@@ -1484,27 +1562,6 @@ 
   [(set_attr "type" "vst<order>x")
    (set_attr "mode" "<VNX8_QHSD:MODE>")])
 
-(define_insn "@pred_indexed_<order>load<VNX16_QHS:mode><VNX16_QHSI:mode>"
-  [(set (match_operand:VNX16_QHS 0 "register_operand"      "=&vr")
-	(if_then_else:VNX16_QHS
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"  "vmWc1")
-	     (match_operand 5 "vector_length_operand"     "   rK")
-	     (match_operand 6 "const_int_operand"         "    i")
-	     (match_operand 7 "const_int_operand"         "    i")
-	     (match_operand 8 "const_int_operand"         "    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VNX16_QHS
-	    [(match_operand 3 "pmode_register_operand"    "    r")
-	     (mem:BLK (scratch))
-	     (match_operand:VNX16_QHSI 4 "register_operand" " vr")] ORDER)
-	  (match_operand:VNX16_QHS 2 "vector_merge_operand" "0vu")))]
-  "TARGET_VECTOR"
-  "vl<order>xei<VNX16_QHSI:sew>.v\t%0,(%3),%4%p1"
-  [(set_attr "type" "vld<order>x")
-   (set_attr "mode" "<VNX16_QHS:MODE>")])
-
 (define_insn "@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>"
   [(set (mem:BLK (scratch))
 	(unspec:BLK
@@ -1522,27 +1579,6 @@ 
   [(set_attr "type" "vst<order>x")
    (set_attr "mode" "<VNX16_QHS:MODE>")])
 
-(define_insn "@pred_indexed_<order>load<VNX32_QH:mode><VNX32_QHI:mode>"
-  [(set (match_operand:VNX32_QH 0 "register_operand"      "=&vr")
-	(if_then_else:VNX32_QH
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"  "vmWc1")
-	     (match_operand 5 "vector_length_operand"     "   rK")
-	     (match_operand 6 "const_int_operand"         "    i")
-	     (match_operand 7 "const_int_operand"         "    i")
-	     (match_operand 8 "const_int_operand"         "    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VNX32_QH
-	    [(match_operand 3 "pmode_register_operand"    "    r")
-	     (mem:BLK (scratch))
-	     (match_operand:VNX32_QHI 4 "register_operand"  " vr")] ORDER)
-	  (match_operand:VNX32_QH 2 "vector_merge_operand"  "0vu")))]
-  "TARGET_VECTOR"
-  "vl<order>xei<VNX32_QHI:sew>.v\t%0,(%3),%4%p1"
-  [(set_attr "type" "vld<order>x")
-   (set_attr "mode" "<VNX32_QH:MODE>")])
-
 (define_insn "@pred_indexed_<order>store<VNX32_QH:mode><VNX32_QHI:mode>"
   [(set (mem:BLK (scratch))
 	(unspec:BLK
@@ -1560,27 +1596,6 @@ 
   [(set_attr "type" "vst<order>x")
    (set_attr "mode" "<VNX32_QH:MODE>")])
 
-(define_insn "@pred_indexed_<order>load<VNX64_Q:mode><VNX64_Q:mode>"
-  [(set (match_operand:VNX64_Q 0 "register_operand"      "=&vr")
-	(if_then_else:VNX64_Q
-	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"  "vmWc1")
-	     (match_operand 5 "vector_length_operand"     "   rK")
-	     (match_operand 6 "const_int_operand"         "    i")
-	     (match_operand 7 "const_int_operand"         "    i")
-	     (match_operand 8 "const_int_operand"         "    i")
-	     (reg:SI VL_REGNUM)
-	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-	  (unspec:VNX64_Q
-	    [(match_operand 3 "pmode_register_operand"    "    r")
-	     (mem:BLK (scratch))
-	     (match_operand:VNX64_Q 4 "register_operand"    " vr")] ORDER)
-	  (match_operand:VNX64_Q 2 "vector_merge_operand"   "0vu")))]
-  "TARGET_VECTOR"
-  "vl<order>xei<VNX64_Q:sew>.v\t%0,(%3),%4%p1"
-  [(set_attr "type" "vld<order>x")
-   (set_attr "mode" "<VNX64_Q:MODE>")])
-
 (define_insn "@pred_indexed_<order>store<VNX64_Q:mode><VNX64_Q:mode>"
   [(set (mem:BLK (scratch))
 	(unspec:BLK
@@ -1612,26 +1627,32 @@ 
 ;; -------------------------------------------------------------------------------
 
 (define_insn "@pred_<optab><mode>"
-  [(set (match_operand:VI 0 "register_operand"           "=vd, vr, vd, vr, vd, vr")
+  [(set (match_operand:VI 0 "register_operand"           "=vd, vd, vr, vr, vd, vd, vr, vr, vd, vd, vr, vr")
 	(if_then_else:VI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK, rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i,  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i,  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i,  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    " rK, rK, rK,  rK, rK, rK, rK, rK, rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        "  i,  i,  i,   i,  i,  i,  i,  i,  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i,  i,   i,  i,  i,  i,  i,  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"        "  i,  i,  i,   i,  i,  i,  i,  i,  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_int_binop:VI
 	    (match_operand:VI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
 	    (match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
-	  (match_operand:VI 2 "vector_merge_operand"     "0vu,0vu,0vu,0vu,0vu,0vu")))]
+	  (match_operand:VI 2 "vector_merge_operand"     "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
   "TARGET_VECTOR"
   "@
+   v<insn>.vv\t%0,%3,%4%p1
+   v<insn>.vv\t%0,%3,%4%p1
    v<insn>.vv\t%0,%3,%4%p1
    v<insn>.vv\t%0,%3,%4%p1
    v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
    v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
+   v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
    v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
    v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1"
   [(set_attr "type" "<int_binop_insn_type>")
@@ -1642,20 +1663,20 @@ 
 ;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode wheras the
 ;; scalar mode is inner mode of the RVV mode for other vx patterns.
 (define_insn "@pred_<optab><mode>_scalar"
-  [(set (match_operand:VI 0 "register_operand"            "=vd, vr, vd, vr")
+  [(set (match_operand:VI 0 "register_operand"           "=vd,vd, vr, vr,vd,vd, vr, vr")
 	(if_then_else:VI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" "  vm,Wc1, vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    "  rK, rK, rK, rK")
-	     (match_operand 6 "const_int_operand"        "   i,  i,  i,  i")
-	     (match_operand 7 "const_int_operand"        "   i,  i,  i,  i")
-	     (match_operand 8 "const_int_operand"        "   i,  i,  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"  "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"     "rK,rK, rK, rK,rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"         " i, i,  i,  i, i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"         " i, i,  i,  i, i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"         " i, i,  i,  i, i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_shift:VI
-	    (match_operand:VI 3 "register_operand"        " vr, vr, vr, vr")
-	    (match_operand 4 "pmode_reg_or_uimm5_operand" "  r,  r,  K,  K"))
-	  (match_operand:VI 2 "vector_merge_operand"      "0vu,0vu,0vu,0vu")))]
+	    (match_operand:VI 3 "register_operand"        "vr,vr, vr, vr,vr,vr, vr, vr")
+	    (match_operand 4 "pmode_reg_or_uimm5_operand" " r, r,  r,  r, K, K,  K,  K"))
+	  (match_operand:VI 2 "vector_merge_operand"      "vu, 0, vu,  0,vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.v%o4\t%0,%3,%4%p1"
   [(set_attr "type" "vshift")
@@ -1663,65 +1684,65 @@ 
 
 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
 (define_insn "@pred_<optab><mode>_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vr")
+  [(set (match_operand:VI_QHS 0 "register_operand"      "=vd,vd, vr, vr")
 	(if_then_else:VI_QHS
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"        " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_commutative_binop:VI_QHS
 	    (vec_duplicate:VI_QHS
-	      (match_operand:<VEL> 4 "reg_or_0_operand"  " rJ, rJ"))
-	    (match_operand:VI_QHS 3 "register_operand"   " vr, vr"))
-	  (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "reg_or_0_operand"  "rJ,rJ, rJ, rJ"))
+	    (match_operand:VI_QHS 3 "register_operand"   "vr,vr, vr, vr"))
+	  (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_<optab><mode>_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vr")
+  [(set (match_operand:VI_QHS 0 "register_operand"      "=vd,vd, vr, vr")
 	(if_then_else:VI_QHS
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"        " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_non_commutative_binop:VI_QHS
-	    (match_operand:VI_QHS 3 "register_operand"   " vr, vr")
+	    (match_operand:VI_QHS 3 "register_operand"   "vr,vr, vr, vr")
 	    (vec_duplicate:VI_QHS
-	      (match_operand:<VEL> 4 "reg_or_0_operand"  " rJ, rJ")))
-	  (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "reg_or_0_operand"  "rJ,rJ, rJ, rJ")))
+	  (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_sub<mode>_reverse_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vr")
+  [(set (match_operand:VI_QHS 0 "register_operand"      "=vd,vd, vr, vr")
 	(if_then_else:VI_QHS
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"        " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (minus:VI_QHS
 	    (vec_duplicate:VI_QHS
-	      (match_operand:<VEL> 4 "register_operand"  "  r,  r"))
-	    (match_operand:VI_QHS 3 "register_operand"   " vr, vr"))
-	  (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "reg_or_0_operand"  "rJ,rJ, rJ, rJ"))
+	    (match_operand:VI_QHS 3 "register_operand"   "vr,vr, vr, vr"))
+	  (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vrsub.vx\t%0,%3,%4%p1"
+  "vrsub.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")])
 
@@ -1761,43 +1782,43 @@ 
 })
 
 (define_insn "*pred_<optab><mode>_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"         "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"         "=vd,vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"        " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_commutative_binop:VI_D
 	    (vec_duplicate:VI_D
-	      (match_operand:<VEL> 4 "reg_or_0_operand"  " rJ, rJ"))
-	    (match_operand:VI_D 3 "register_operand"     " vr, vr"))
-	  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "reg_or_0_operand"  "rJ,rJ, rJ, rJ"))
+	    (match_operand:VI_D 3 "register_operand"     "vr,vr, vr, vr"))
+	  (match_operand:VI_D 2 "vector_merge_operand"   "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_<optab><mode>_extended_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"             "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"             "=vd,vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"     " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"        " rK, rK")
-	     (match_operand 6 "const_int_operand"            "  i,  i")
-	     (match_operand 7 "const_int_operand"            "  i,  i")
-	     (match_operand 8 "const_int_operand"            "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"     "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"        "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"            " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"            " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"            " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_commutative_binop:VI_D
 	    (vec_duplicate:VI_D
 	      (sign_extend:<VEL>
-	        (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ")))
-	    (match_operand:VI_D 3 "register_operand"         " vr, vr"))
-	  (match_operand:VI_D 2 "vector_merge_operand"       "0vu,0vu")))]
+	        (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
+	    (match_operand:VI_D 3 "register_operand"         "vr,vr, vr, vr"))
+	  (match_operand:VI_D 2 "vector_merge_operand"       "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
@@ -1837,43 +1858,43 @@ 
 })
 
 (define_insn "*pred_<optab><mode>_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"         "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"         "=vd,vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"        " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_non_commutative_binop:VI_D
-	    (match_operand:VI_D 3 "register_operand"     " vr, vr")
+	    (match_operand:VI_D 3 "register_operand"     "vr,vr, vr, vr")
 	    (vec_duplicate:VI_D
-	      (match_operand:<VEL> 4 "reg_or_0_operand"  " rJ, rJ")))
-	  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "reg_or_0_operand"  "rJ,rJ, rJ, rJ")))
+	  (match_operand:VI_D 2 "vector_merge_operand"   "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_<optab><mode>_extended_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"             "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"             "=vd,vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"     " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"        " rK, rK")
-	     (match_operand 6 "const_int_operand"            "  i,  i")
-	     (match_operand 7 "const_int_operand"            "  i,  i")
-	     (match_operand 8 "const_int_operand"            "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"     "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"        "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"            " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"            " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"            " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_non_commutative_binop:VI_D
-	    (match_operand:VI_D 3 "register_operand"         " vr, vr")
+	    (match_operand:VI_D 3 "register_operand"         "vr,vr, vr, vr")
 	    (vec_duplicate:VI_D
 	      (sign_extend:<VEL>
-	        (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
-	  (match_operand:VI_D 2 "vector_merge_operand"       "0vu,0vu")))]
+	        (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))))
+	  (match_operand:VI_D 2 "vector_merge_operand"       "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
@@ -1913,85 +1934,85 @@ 
 })
 
 (define_insn "*pred_sub<mode>_reverse_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"         "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"         "=vd,vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"        " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (minus:VI_D
 	    (vec_duplicate:VI_D
-	      (match_operand:<VEL> 4 "register_operand"  "  r,  r"))
-	    (match_operand:VI_D 3 "register_operand"     " vr, vr"))
-	  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "reg_or_0_operand"  "rJ,rJ, rJ, rJ"))
+	    (match_operand:VI_D 3 "register_operand"     "vr,vr, vr, vr"))
+	  (match_operand:VI_D 2 "vector_merge_operand"   "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vrsub.vx\t%0,%3,%4%p1"
+  "vrsub.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_sub<mode>_extended_reverse_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"             "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"             "=vd,vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"     " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"        " rK, rK")
-	     (match_operand 6 "const_int_operand"            "  i,  i")
-	     (match_operand 7 "const_int_operand"            "  i,  i")
-	     (match_operand 8 "const_int_operand"            "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"     "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"        "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"            " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"            " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"            " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (minus:VI_D
 	    (vec_duplicate:VI_D
 	      (sign_extend:<VEL>
-	        (match_operand:<VSUBEL> 4 "register_operand" "  r,  r")))
-	    (match_operand:VI_D 3 "register_operand"         " vr, vr"))
-	  (match_operand:VI_D 2 "vector_merge_operand"       "0vu,0vu")))]
+	        (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
+	    (match_operand:VI_D 3 "register_operand"         "vr,vr, vr, vr"))
+	  (match_operand:VI_D 2 "vector_merge_operand"       "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
-  "vrsub.vx\t%0,%3,%4%p1"
+  "vrsub.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vialu")
    (set_attr "mode" "<MODE>")])
 
 ;; Multiply High instructions.
 (define_insn "@pred_mulh<v_su><mode>"
-  [(set (match_operand:VFULLI 0 "register_operand"       "=vd, vr")
+  [(set (match_operand:VFULLI 0 "register_operand"       "=vd,vd, vr, vr")
 	(if_then_else:VFULLI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"        " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VFULLI
-	    [(match_operand:VFULLI 3 "register_operand"  " vr, vr")
-	     (match_operand:VFULLI 4 "register_operand"  " vr, vr")] VMULH)
-	  (match_operand:VFULLI 2 "vector_merge_operand" "0vu,0vu")))]
+	    [(match_operand:VFULLI 3 "register_operand"  "vr,vr, vr, vr")
+	     (match_operand:VFULLI 4 "register_operand"  "vr,vr, vr, vr")] VMULH)
+	  (match_operand:VFULLI 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "vmulh<v_su>.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vimul")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_mulh<v_su><mode>_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vr")
+  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd,vd, vr, vr")
 	(if_then_else:VI_QHS
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"        " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_QHS
 	    [(vec_duplicate:VI_QHS
-	       (match_operand:<VEL> 4 "reg_or_0_operand"  " rJ, rJ"))
-	     (match_operand:VI_QHS 3 "register_operand"   " vr, vr")] VMULH)
-	  (match_operand:VI_QHS 2 "vector_merge_operand"  "0vu,0vu")))]
+	       (match_operand:<VEL> 4 "reg_or_0_operand"  "rJ,rJ, rJ, rJ"))
+	     (match_operand:VI_QHS 3 "register_operand"   "vr,vr, vr, vr")] VMULH)
+	  (match_operand:VI_QHS 2 "vector_merge_operand"  "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "vmulh<v_su>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vimul")
@@ -2031,43 +2052,43 @@ 
 })
 
 (define_insn "*pred_mulh<v_su><mode>_scalar"
-  [(set (match_operand:VFULLI_D 0 "register_operand"       "=vd, vr")
+  [(set (match_operand:VFULLI_D 0 "register_operand"       "=vd,vd, vr, vr")
 	(if_then_else:VFULLI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"   " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"      " rK, rK")
-	     (match_operand 6 "const_int_operand"          "  i,  i")
-	     (match_operand 7 "const_int_operand"          "  i,  i")
-	     (match_operand 8 "const_int_operand"          "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"   "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"      "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"          " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"          " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"          " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VFULLI_D
 	    [(vec_duplicate:VFULLI_D
-	       (match_operand:<VEL> 4 "reg_or_0_operand"   " rJ, rJ"))
-	     (match_operand:VFULLI_D 3 "register_operand"  " vr, vr")] VMULH)
-	  (match_operand:VFULLI_D 2 "vector_merge_operand" "0vu,0vu")))]
+	       (match_operand:<VEL> 4 "reg_or_0_operand"   "rJ,rJ, rJ, rJ"))
+	     (match_operand:VFULLI_D 3 "register_operand"  "vr,vr, vr, vr")] VMULH)
+	  (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "vmulh<v_su>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vimul")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_mulh<v_su><mode>_extended_scalar"
-  [(set (match_operand:VFULLI_D 0 "register_operand"          "=vd, vr")
+  [(set (match_operand:VFULLI_D 0 "register_operand"          "=vd,vd, vr, vr")
 	(if_then_else:VFULLI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"      " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"         " rK, rK")
-	     (match_operand 6 "const_int_operand"             "  i,  i")
-	     (match_operand 7 "const_int_operand"             "  i,  i")
-	     (match_operand 8 "const_int_operand"             "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"      "vm,vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"         "rK,rK, rK, rK")
+	     (match_operand 6 "const_int_operand"             " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"             " i, i,  i,  i")
+	     (match_operand 8 "const_int_operand"             " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VFULLI_D
 	    [(vec_duplicate:VFULLI_D
 	       (sign_extend:<VEL>
-	         (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ")))
-	     (match_operand:VFULLI_D 3 "register_operand"     " vr, vr")] VMULH)
-	  (match_operand:VFULLI_D 2 "vector_merge_operand"    "0vu,0vu")))]
+	         (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
+	     (match_operand:VFULLI_D 3 "register_operand"     "vr,vr, vr, vr")] VMULH)
+	  (match_operand:VFULLI_D 2 "vector_merge_operand"    "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "vmulh<v_su>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vimul")
@@ -2075,20 +2096,20 @@ 
 
 ;; Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
 (define_insn "@pred_adc<mode>"
-  [(set (match_operand:VI 0 "register_operand"            "=&vr, &vr")
+  [(set (match_operand:VI 0 "register_operand"           "=vd,vd,vd,vd")
 	(if_then_else:VI
 	  (unspec:<VM>
-	    [(match_operand 5 "vector_length_operand"     "  rK,  rK")
-	     (match_operand 6 "const_int_operand"         "   i,   i")
-	     (match_operand 7 "const_int_operand"         "   i,   i")
+	    [(match_operand 5 "vector_length_operand"     "rK,rK,rK,rK")
+	     (match_operand 6 "const_int_operand"         " i, i, i, i")
+	     (match_operand 7 "const_int_operand"         " i, i, i, i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI
 	     [(plus:VI
-	       (match_operand:VI 2 "register_operand"     "  vr,  vr")
-	       (match_operand:VI 3 "vector_arith_operand" "  vr,  vi"))
-	     (match_operand:<VM> 4 "register_operand"     "  vm,  vm")] UNSPEC_VADC)
-	  (match_operand:VI 1 "vector_merge_operand"      " 0vu, 0vu")))]
+	       (match_operand:VI 2 "register_operand"     "vr,vr,vr,vr")
+	       (match_operand:VI 3 "vector_arith_operand" "vr,vr,vi,vi"))
+	     (match_operand:<VM> 4 "register_operand"     "vm,vm,vm,vm")] UNSPEC_VADC)
+	  (match_operand:VI 1 "vector_merge_operand"      "vu, 0,vu, 0")))]
   "TARGET_VECTOR"
   "vadc.v%o3m\t%0,%2,%v3,%4"
   [(set_attr "type" "vicalu")
@@ -2099,20 +2120,20 @@ 
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
 
 (define_insn "@pred_sbc<mode>"
-  [(set (match_operand:VI 0 "register_operand"            "=&vr")
+  [(set (match_operand:VI 0 "register_operand"           "=vd,vd")
 	(if_then_else:VI
 	  (unspec:<VM>
-	    [(match_operand 5 "vector_length_operand"     "  rK")
-	     (match_operand 6 "const_int_operand"         "   i")
-	     (match_operand 7 "const_int_operand"         "   i")
+	    [(match_operand 5 "vector_length_operand"     "rK,rK")
+	     (match_operand 6 "const_int_operand"         " i, i")
+	     (match_operand 7 "const_int_operand"         " i, i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI
 	     [(minus:VI
-	       (match_operand:VI 2 "register_operand"     "  vr")
-	       (match_operand:VI 3 "register_operand"     "  vr"))
-	      (match_operand:<VM> 4 "register_operand"    "  vm")] UNSPEC_VSBC)
-	  (match_operand:VI 1 "vector_merge_operand"      " 0vu")))]
+	       (match_operand:VI 2 "register_operand"     "vr,vr")
+	       (match_operand:VI 3 "register_operand"     "vr,vr"))
+	      (match_operand:<VM> 4 "register_operand"    "vm,vm")] UNSPEC_VSBC)
+	  (match_operand:VI 1 "vector_merge_operand"      "vu, 0")))]
   "TARGET_VECTOR"
   "vsbc.vvm\t%0,%2,%3,%4"
   [(set_attr "type" "vicalu")
@@ -2123,21 +2144,21 @@ 
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
 
 (define_insn "@pred_adc<mode>_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"        "=&vr")
+  [(set (match_operand:VI_QHS 0 "register_operand"        "=vd,vd")
 	(if_then_else:VI_QHS
 	  (unspec:<VM>
-	    [(match_operand 5 "vector_length_operand"      " rK")
-	     (match_operand 6 "const_int_operand"          "  i")
-	     (match_operand 7 "const_int_operand"          "  i")
+	    [(match_operand 5 "vector_length_operand"      "rK,rK")
+	     (match_operand 6 "const_int_operand"          " i, i")
+	     (match_operand 7 "const_int_operand"          " i, i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_QHS
 	     [(plus:VI_QHS
 	       (vec_duplicate:VI_QHS
-	         (match_operand:<VEL> 3 "register_operand" "  r"))
-	       (match_operand:VI_QHS 2 "register_operand"  " vr"))
-	     (match_operand:<VM> 4 "register_operand"      " vm")] UNSPEC_VADC)
-	  (match_operand:VI_QHS 1 "vector_merge_operand"   "0vu")))]
+	         (match_operand:<VEL> 3 "register_operand" " r, r"))
+	       (match_operand:VI_QHS 2 "register_operand"  "vr,vr"))
+	     (match_operand:<VM> 4 "register_operand"      "vm,vm")] UNSPEC_VADC)
+	  (match_operand:VI_QHS 1 "vector_merge_operand"   "vu, 0")))]
   "TARGET_VECTOR"
   "vadc.vxm\t%0,%2,%3,%4"
   [(set_attr "type" "vicalu")
@@ -2148,21 +2169,21 @@ 
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
 
 (define_insn "@pred_sbc<mode>_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"         "=&vr")
+  [(set (match_operand:VI_QHS 0 "register_operand"         "=vd,vd")
 	(if_then_else:VI_QHS
 	  (unspec:<VM>
-	    [(match_operand 5 "vector_length_operand"      "  rK")
-	     (match_operand 6 "const_int_operand"          "   i")
-	     (match_operand 7 "const_int_operand"          "   i")
+	    [(match_operand 5 "vector_length_operand"       "rK,rK")
+	     (match_operand 6 "const_int_operand"           " i, i")
+	     (match_operand 7 "const_int_operand"           " i, i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_QHS
 	     [(minus:VI_QHS
-	        (match_operand:VI_QHS 2 "register_operand" "  vr")
+	        (match_operand:VI_QHS 2 "register_operand"  "vr,vr")
 	        (vec_duplicate:VI_QHS
-	          (match_operand:<VEL> 3 "reg_or_0_operand" " rJ")))
-	      (match_operand:<VM> 4 "register_operand"      " vm")] UNSPEC_VSBC)
-	  (match_operand:VI_QHS 1 "vector_merge_operand"   " 0vu")))]
+	          (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
+	      (match_operand:<VM> 4 "register_operand"      "vm,vm")] UNSPEC_VSBC)
+	  (match_operand:VI_QHS 1 "vector_merge_operand"    "vu, 0")))]
   "TARGET_VECTOR"
   "vsbc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
@@ -2206,21 +2227,21 @@ 
 })
 
 (define_insn "*pred_adc<mode>_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"           "=&vr")
+  [(set (match_operand:VI_D 0 "register_operand"           "=vd,vd")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand 5 "vector_length_operand"       " rK")
-	     (match_operand 6 "const_int_operand"           "  i")
-	     (match_operand 7 "const_int_operand"           "  i")
+	    [(match_operand 5 "vector_length_operand"       "rK,rK")
+	     (match_operand 6 "const_int_operand"           " i, i")
+	     (match_operand 7 "const_int_operand"           " i, i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_D
 	     [(plus:VI_D
 	        (vec_duplicate:VI_D
-	          (match_operand:<VEL> 3 "reg_or_0_operand" " rJ"))
-	        (match_operand:VI_D 2 "register_operand"    " vr"))
-	      (match_operand:<VM> 4 "register_operand"      " vm")] UNSPEC_VADC)
-	  (match_operand:VI_D 1 "vector_merge_operand"      "0vu")))]
+	          (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ"))
+	        (match_operand:VI_D 2 "register_operand"    "vr,vr"))
+	      (match_operand:<VM> 4 "register_operand"      "vm,vm")] UNSPEC_VADC)
+	  (match_operand:VI_D 1 "vector_merge_operand"      "vu, 0")))]
   "TARGET_VECTOR"
   "vadc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
@@ -2231,22 +2252,22 @@ 
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
 
 (define_insn "*pred_adc<mode>_extended_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"                "=&vr")
+  [(set (match_operand:VI_D 0 "register_operand"                "=vd,vd")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand 5 "vector_length_operand"            " rK")
-	     (match_operand 6 "const_int_operand"                "  i")
-	     (match_operand 7 "const_int_operand"                "  i")
+	    [(match_operand 5 "vector_length_operand"            "rK,rK")
+	     (match_operand 6 "const_int_operand"                " i, i")
+	     (match_operand 7 "const_int_operand"                " i, i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_D
 	     [(plus:VI_D
 	        (vec_duplicate:VI_D
 	          (sign_extend:<VEL>
-	            (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ")))
-	        (match_operand:VI_D 2 "register_operand"         " vr"))
-	      (match_operand:<VM> 4 "register_operand"           " vm")] UNSPEC_VADC)
-	  (match_operand:VI_D 1 "vector_merge_operand"           "0vu")))]
+	            (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ")))
+	        (match_operand:VI_D 2 "register_operand"         "vr,vr"))
+	      (match_operand:<VM> 4 "register_operand"           "vm,vm")] UNSPEC_VADC)
+	  (match_operand:VI_D 1 "vector_merge_operand"           "vu, 0")))]
   "TARGET_VECTOR"
   "vadc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
@@ -2290,21 +2311,21 @@ 
 })
 
 (define_insn "*pred_sbc<mode>_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"           "=&vr")
+  [(set (match_operand:VI_D 0 "register_operand"           "=vd,vd")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand 5 "vector_length_operand"       " rK")
-	     (match_operand 6 "const_int_operand"           "  i")
-	     (match_operand 7 "const_int_operand"           "  i")
+	    [(match_operand 5 "vector_length_operand"       "rK,rK")
+	     (match_operand 6 "const_int_operand"           " i, i")
+	     (match_operand 7 "const_int_operand"           " i, i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_D
 	     [(minus:VI_D
-	        (match_operand:VI_D 2 "register_operand"    " vr")
+	        (match_operand:VI_D 2 "register_operand"    "vr,vr")
 	        (vec_duplicate:VI_D
-	          (match_operand:<VEL> 3 "reg_or_0_operand" " rJ")))
-	      (match_operand:<VM> 4 "register_operand"      " vm")] UNSPEC_VSBC)
-	  (match_operand:VI_D 1 "vector_merge_operand"      "0vu")))]
+	          (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
+	      (match_operand:<VM> 4 "register_operand"      "vm,vm")] UNSPEC_VSBC)
+	  (match_operand:VI_D 1 "vector_merge_operand"      "vu, 0")))]
   "TARGET_VECTOR"
   "vsbc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
@@ -2315,22 +2336,22 @@ 
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
 
 (define_insn "*pred_sbc<mode>_extended_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"                "=&vr")
+  [(set (match_operand:VI_D 0 "register_operand"                "=vd,vd")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand 5 "vector_length_operand"            " rK")
-	     (match_operand 6 "const_int_operand"                "  i")
-	     (match_operand 7 "const_int_operand"                "  i")
+	    [(match_operand 5 "vector_length_operand"           "rK,rK")
+	     (match_operand 6 "const_int_operand"               " i, i")
+	     (match_operand 7 "const_int_operand"               " i, i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_D
 	     [(minus:VI_D
-	        (match_operand:VI_D 2 "register_operand"         " vr")
+	        (match_operand:VI_D 2 "register_operand"         "vr,vr")
 	        (vec_duplicate:VI_D
 	          (sign_extend:<VEL>
-	            (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ"))))
-	      (match_operand:<VM> 4 "register_operand"           " vm")] UNSPEC_VSBC)
-	  (match_operand:VI_D 1 "vector_merge_operand"           "0vu")))]
+	            (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ"))))
+	      (match_operand:<VM> 4 "register_operand"           "vm,vm")] UNSPEC_VSBC)
+	  (match_operand:VI_D 1 "vector_merge_operand"           "vu, 0")))]
   "TARGET_VECTOR"
   "vsbc.vxm\t%0,%2,%z3,%4"
   [(set_attr "type" "vicalu")
@@ -2774,19 +2795,19 @@ 
 ;; -------------------------------------------------------------------------------
 
 (define_insn "@pred_<optab><mode>"
-  [(set (match_operand:VI 0 "register_operand"           "=vd, vr")
+  [(set (match_operand:VI 0 "register_operand"          "=vd,vd, vr, vr")
 	(if_then_else:VI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 4 "vector_length_operand"    " rK, rK")
-	     (match_operand 5 "const_int_operand"        "  i,  i")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
+	     (match_operand 4 "vector_length_operand"    "rK,rK, rK, rK")
+	     (match_operand 5 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 6 "const_int_operand"        " i, i,  i,  i")
+	     (match_operand 7 "const_int_operand"        " i, i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_int_unop:VI
-	    (match_operand:VI 3 "register_operand"       " vr, vr"))
-	  (match_operand:VI 2 "vector_merge_operand"     "0vu,0vu")))]
+	    (match_operand:VI 3 "register_operand"       "vr,vr, vr, vr"))
+	  (match_operand:VI 2 "vector_merge_operand"     "vu, 0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.v\t%0,%3%p1"
   [(set_attr "type" "vialu")
@@ -2807,19 +2828,19 @@ 
 
 ;; Vector Double-Widening Sign-extend and Zero-extend.
 (define_insn "@pred_<optab><mode>_vf2"
-  [(set (match_operand:VWEXTI 0 "register_operand"            "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"            "=&vr,&vr")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"         "vmWc1")
-	     (match_operand 4 "vector_length_operand"            "   rK")
-	     (match_operand 5 "const_int_operand"                "    i")
-	     (match_operand 6 "const_int_operand"                "    i")
-	     (match_operand 7 "const_int_operand"                "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"         "vmWc1,vmWc1")
+	     (match_operand 4 "vector_length_operand"            "   rK,   rK")
+	     (match_operand 5 "const_int_operand"                "    i,    i")
+	     (match_operand 6 "const_int_operand"                "    i,    i")
+	     (match_operand 7 "const_int_operand"                "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_extend:VWEXTI
-	    (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr"))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"         "  0vu")))]
+	    (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"         "   vu,    0")))]
   "TARGET_VECTOR"
   "v<sz>ext.vf2\t%0,%3%p1"
   [(set_attr "type" "vext")
@@ -2827,19 +2848,19 @@ 
 
 ;; Vector Quad-Widening Sign-extend and Zero-extend.
 (define_insn "@pred_<optab><mode>_vf4"
-  [(set (match_operand:VQEXTI 0 "register_operand"          "=&vr")
+  [(set (match_operand:VQEXTI 0 "register_operand"          "=&vr,&vr")
 	(if_then_else:VQEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"       "vmWc1")
-	     (match_operand 4 "vector_length_operand"          "   rK")
-	     (match_operand 5 "const_int_operand"              "    i")
-	     (match_operand 6 "const_int_operand"              "    i")
-	     (match_operand 7 "const_int_operand"              "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"       "vmWc1,vmWc1")
+	     (match_operand 4 "vector_length_operand"          "   rK,   rK")
+	     (match_operand 5 "const_int_operand"              "    i,    i")
+	     (match_operand 6 "const_int_operand"              "    i,    i")
+	     (match_operand 7 "const_int_operand"              "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_extend:VQEXTI
-	    (match_operand:<V_QUAD_TRUNC> 3 "register_operand" "   vr"))
-	  (match_operand:VQEXTI 2 "vector_merge_operand"       "  0vu")))]
+	    (match_operand:<V_QUAD_TRUNC> 3 "register_operand" "   vr,   vr"))
+	  (match_operand:VQEXTI 2 "vector_merge_operand"       "   vu,    0")))]
   "TARGET_VECTOR"
   "v<sz>ext.vf4\t%0,%3%p1"
   [(set_attr "type" "vext")
@@ -2847,19 +2868,19 @@ 
 
 ;; Vector Oct-Widening Sign-extend and Zero-extend.
 (define_insn "@pred_<optab><mode>_vf8"
-  [(set (match_operand:VOEXTI 0 "register_operand"         "=&vr")
+  [(set (match_operand:VOEXTI 0 "register_operand"         "=&vr,&vr")
 	(if_then_else:VOEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1")
-	     (match_operand 4 "vector_length_operand"         "   rK")
-	     (match_operand 5 "const_int_operand"             "    i")
-	     (match_operand 6 "const_int_operand"             "    i")
-	     (match_operand 7 "const_int_operand"             "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
+	     (match_operand 4 "vector_length_operand"         "   rK,   rK")
+	     (match_operand 5 "const_int_operand"             "    i,    i")
+	     (match_operand 6 "const_int_operand"             "    i,    i")
+	     (match_operand 7 "const_int_operand"             "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_extend:VOEXTI
-	    (match_operand:<V_OCT_TRUNC> 3 "register_operand" "   vr"))
-	  (match_operand:VOEXTI 2 "vector_merge_operand"      "  0vu")))]
+	    (match_operand:<V_OCT_TRUNC> 3 "register_operand" "   vr,   vr"))
+	  (match_operand:VOEXTI 2 "vector_merge_operand"      "   vu,    0")))]
   "TARGET_VECTOR"
   "v<sz>ext.vf8\t%0,%3%p1"
   [(set_attr "type" "vext")
@@ -2867,133 +2888,133 @@ 
 
 ;; Vector Widening Add/Subtract/Multiply.
 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1")
-	     (match_operand 5 "vector_length_operand"              "   rK")
-	     (match_operand 6 "const_int_operand"                  "    i")
-	     (match_operand 7 "const_int_operand"                  "    i")
-	     (match_operand 8 "const_int_operand"                  "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                  "    i,    i")
+	     (match_operand 7 "const_int_operand"                  "    i,    i")
+	     (match_operand 8 "const_int_operand"                  "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_widen_binop:VWEXTI
 	    (any_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr"))
+	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
 	    (any_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"           "  0vu")))]
+	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
   "vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1")
-	     (match_operand 5 "vector_length_operand"              "   rK")
-	     (match_operand 6 "const_int_operand"                  "    i")
-	     (match_operand 7 "const_int_operand"                  "    i")
-	     (match_operand 8 "const_int_operand"                  "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                  "    i,    i")
+	     (match_operand 7 "const_int_operand"                  "    i,    i")
+	     (match_operand 8 "const_int_operand"                  "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_widen_binop:VWEXTI
 	    (any_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr"))
+	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
 	    (any_extend:VWEXTI
 	      (vec_duplicate:<V_DOUBLE_TRUNC>
-		(match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ"))))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"           "  0vu")))]
+		(match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ,   rJ"))))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
   "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1")
-	     (match_operand 5 "vector_length_operand"              "   rK")
-	     (match_operand 6 "const_int_operand"                  "    i")
-	     (match_operand 7 "const_int_operand"                  "    i")
-	     (match_operand 8 "const_int_operand"                  "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                  "    i,    i")
+	     (match_operand 7 "const_int_operand"                  "    i,    i")
+	     (match_operand 8 "const_int_operand"                  "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VWEXTI
-	    (match_operand:VWEXTI 3 "register_operand"             "   vr")
+	    (match_operand:VWEXTI 3 "register_operand"             "   vr,   vr")
 	    (any_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"           "  0vu")))]
+	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
   "vw<plus_minus:insn><any_extend:u>.wv\t%0,%3,%4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1")
-	     (match_operand 5 "vector_length_operand"              "   rK")
-	     (match_operand 6 "const_int_operand"                  "    i")
-	     (match_operand 7 "const_int_operand"                  "    i")
-	     (match_operand 8 "const_int_operand"                  "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                  "    i,    i")
+	     (match_operand 7 "const_int_operand"                  "    i,    i")
+	     (match_operand 8 "const_int_operand"                  "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus_minus:VWEXTI
-	    (match_operand:VWEXTI 3 "register_operand"             "   vr")
+	    (match_operand:VWEXTI 3 "register_operand"             "   vr,   vr")
 	    (any_extend:VWEXTI
 	      (vec_duplicate:<V_DOUBLE_TRUNC>
-		(match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ"))))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"           "  0vu")))]
+		(match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ,   rJ"))))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
   "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
   [(set_attr "type" "vi<widen_binop_insn_type>")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_widen_mulsu<mode>"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1")
-	     (match_operand 5 "vector_length_operand"              "   rK")
-	     (match_operand 6 "const_int_operand"                  "    i")
-	     (match_operand 7 "const_int_operand"                  "    i")
-	     (match_operand 8 "const_int_operand"                  "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                  "    i,    i")
+	     (match_operand 7 "const_int_operand"                  "    i,    i")
+	     (match_operand 8 "const_int_operand"                  "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (mult:VWEXTI
 	    (sign_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr"))
+	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
 	    (zero_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"           "  0vu")))]
+	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
   "vwmulsu.vv\t%0,%3,%4%p1"
   [(set_attr "type" "viwmul")
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_widen_mulsu<mode>_scalar"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1")
-	     (match_operand 5 "vector_length_operand"              "   rK")
-	     (match_operand 6 "const_int_operand"                  "    i")
-	     (match_operand 7 "const_int_operand"                  "    i")
-	     (match_operand 8 "const_int_operand"                  "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	     (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	     (match_operand 6 "const_int_operand"                  "    i,    i")
+	     (match_operand 7 "const_int_operand"                  "    i,    i")
+	     (match_operand 8 "const_int_operand"                  "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (mult:VWEXTI
 	    (sign_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr"))
+	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
 	    (zero_extend:VWEXTI
 	      (vec_duplicate:<V_DOUBLE_TRUNC>
-		(match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ"))))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"           "  0vu")))]
+		(match_operand:<VSUBEL> 4 "reg_or_0_operand"       "   rJ,   rJ"))))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
   "vwmulsu.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "viwmul")
@@ -3001,22 +3022,22 @@ 
 
 ;; vwcvt<u>.x.x.v
 (define_insn "@pred_<optab><mode>"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1")
-	     (match_operand 4 "vector_length_operand"              "   rK")
-	     (match_operand 5 "const_int_operand"                  "    i")
-	     (match_operand 6 "const_int_operand"                  "    i")
-	     (match_operand 7 "const_int_operand"                  "    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	     (match_operand 4 "vector_length_operand"              "   rK,   rK")
+	     (match_operand 5 "const_int_operand"                  "    i,    i")
+	     (match_operand 6 "const_int_operand"                  "    i,    i")
+	     (match_operand 7 "const_int_operand"                  "    i,    i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (plus:VWEXTI
 	    (any_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr"))
+	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
 	    (vec_duplicate:VWEXTI
 	      (reg:<VEL> X0_REGNUM)))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"           "  0vu")))]
+	  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
   "TARGET_VECTOR"
   "vwcvt<u>.x.x.v\t%0,%3%p1"
   [(set_attr "type" "viwalu")
@@ -3115,24 +3136,28 @@ 
 
 ;; Saturating Add and Subtract
 (define_insn "@pred_<optab><mode>"
-  [(set (match_operand:VI 0 "register_operand"                   "=vd, vr, vd, vr")
+  [(set (match_operand:VI 0 "register_operand"           "=vd, vd, vr, vr, vd, vd, vr, vr")
 	(if_then_else:VI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"         " vm,Wc1, vm,Wc1")
-	     (match_operand 5 "vector_length_operand"            " rK, rK, rK, rK")
-	     (match_operand 6 "const_int_operand"                "  i,  i,  i,  i")
-	     (match_operand 7 "const_int_operand"                "  i,  i,  i,  i")
-	     (match_operand 8 "const_int_operand"                "  i,  i,  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK, rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i,  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i,  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i,  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (any_sat_int_binop:VI
-	    (match_operand:VI 3 "<binop_rhs1_predicate>"         " vr, vr, vr, vr")
+	    (match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr, vr, vr")
 	    (match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
-	  (match_operand:VI 2 "vector_merge_operand"             "0vu,0vu,0vu,0vu")))]
+	  (match_operand:VI 2 "vector_merge_operand"     " vu,  0, vu,  0, vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "@
    v<insn>.vv\t%0,%3,%4%p1
    v<insn>.vv\t%0,%3,%4%p1
+   v<insn>.vv\t%0,%3,%4%p1
+   v<insn>.vv\t%0,%3,%4%p1
+   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
+   v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
    v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
    v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
   [(set_attr "type" "<int_binop_insn_type>")
@@ -3140,42 +3165,42 @@ 
 
 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
 (define_insn "@pred_<optab><mode>_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vr")
+  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vd, vr, vr")
 	(if_then_else:VI_QHS
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (sat_int_plus_binop:VI_QHS
 	    (vec_duplicate:VI_QHS
-	      (match_operand:<VEL> 4 "register_operand"  "  r,  r"))
-	    (match_operand:VI_QHS 3 "register_operand"   " vr, vr"))
-	  (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "register_operand"  "  r,  r,  r,  r"))
+	    (match_operand:VI_QHS 3 "register_operand"   " vr, vr, vr, vr"))
+	  (match_operand:VI_QHS 2 "vector_merge_operand" " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_<optab><mode>_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vr")
+  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vd, vr, vr")
 	(if_then_else:VI_QHS
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (sat_int_minus_binop:VI_QHS
-	    (match_operand:VI_QHS 3 "register_operand"   " vr, vr")
+	    (match_operand:VI_QHS 3 "register_operand"   " vr, vr, vr, vr")
 	    (vec_duplicate:VI_QHS
-	      (match_operand:<VEL> 4 "register_operand"  "  r,  r")))
-	  (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "register_operand"  "  r,  r,  r,  r")))
+	  (match_operand:VI_QHS 2 "vector_merge_operand" " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
@@ -3215,43 +3240,43 @@ 
 })
 
 (define_insn "*pred_<optab><mode>_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"         "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"         "=vd, vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (sat_int_plus_binop:VI_D
 	    (vec_duplicate:VI_D
-	      (match_operand:<VEL> 4 "register_operand"  "  r,  r"))
-	    (match_operand:VI_D 3 "register_operand"     " vr, vr"))
-	  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "register_operand"  "  r,  r,  r,  r"))
+	    (match_operand:VI_D 3 "register_operand"     " vr, vr, vr, vr"))
+	  (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_<optab><mode>_extended_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"             "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"             "=vd, vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"     " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"        " rK, rK")
-	     (match_operand 6 "const_int_operand"            "  i,  i")
-	     (match_operand 7 "const_int_operand"            "  i,  i")
-	     (match_operand 8 "const_int_operand"            "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"     " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"        " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"            "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"            "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"            "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (sat_int_plus_binop:VI_D
 	    (vec_duplicate:VI_D
 	      (sign_extend:<VEL>
-	        (match_operand:<VSUBEL> 4 "register_operand" "  r,  r")))
-	    (match_operand:VI_D 3 "register_operand"         " vr, vr"))
-	  (match_operand:VI_D 2 "vector_merge_operand"       "0vu,0vu")))]
+	        (match_operand:<VSUBEL> 4 "register_operand" "  r,  r,  r,  r")))
+	    (match_operand:VI_D 3 "register_operand"         " vr, vr, vr, vr"))
+	  (match_operand:VI_D 2 "vector_merge_operand"       " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
@@ -3291,63 +3316,63 @@ 
 })
 
 (define_insn "*pred_<optab><mode>_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"         "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"         "=vd, vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (sat_int_minus_binop:VI_D
-	    (match_operand:VI_D 3 "register_operand"     " vr, vr")
+	    (match_operand:VI_D 3 "register_operand"     " vr, vr, vr, vr")
 	    (vec_duplicate:VI_D
-	      (match_operand:<VEL> 4 "register_operand"  "  r,  r")))
-	  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
+	      (match_operand:<VEL> 4 "register_operand"  "  r,  r,  r,  r")))
+	  (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_<optab><mode>_extended_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"             "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"             "=vd, vd, vr, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"     " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"        " rK, rK")
-	     (match_operand 6 "const_int_operand"            "  i,  i")
-	     (match_operand 7 "const_int_operand"            "  i,  i")
-	     (match_operand 8 "const_int_operand"            "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"     " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"        " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"            "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"            "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"            "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (sat_int_minus_binop:VI_D
-	    (match_operand:VI_D 3 "register_operand"         " vr, vr")
+	    (match_operand:VI_D 3 "register_operand"         " vr, vr, vr, vr")
 	    (vec_duplicate:VI_D
 	      (sign_extend:<VEL>
-	        (match_operand:<VSUBEL> 4 "register_operand" "  r,  r"))))
-	  (match_operand:VI_D 2 "vector_merge_operand"       "0vu,0vu")))]
+	        (match_operand:<VSUBEL> 4 "register_operand" "  r,  r,  r,  r"))))
+	  (match_operand:VI_D 2 "vector_merge_operand"       " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<insn>.vx\t%0,%3,%4%p1"
   [(set_attr "type" "<int_binop_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_<sat_op><mode>"
-  [(set (match_operand:VI 0 "register_operand"           "=vd, vr")
+  [(set (match_operand:VI 0 "register_operand"           "=vd, vd, vr, vr")
 	(if_then_else:VI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI
-	    [(match_operand:VI 3 "register_operand"      " vr, vr")
-	     (match_operand:VI 4 "register_operand"      " vr, vr")] VSAT_OP)
-	  (match_operand:VI 2 "vector_merge_operand"     "0vu,0vu")))]
+	    [(match_operand:VI 3 "register_operand"      " vr, vr, vr, vr")
+	     (match_operand:VI 4 "register_operand"      " vr, vr, vr, vr")] VSAT_OP)
+	  (match_operand:VI 2 "vector_merge_operand"     " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<sat_op>.vv\t%0,%3,%4%p1"
   [(set_attr "type" "<sat_insn_type>")
@@ -3355,40 +3380,40 @@ 
 
 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
 (define_insn "@pred_<sat_op><mode>_scalar"
-  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vr")
+  [(set (match_operand:VI_QHS 0 "register_operand"       "=vd, vr, vd, vr")
 	(if_then_else:VI_QHS
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_QHS
-	    [(match_operand:VI_QHS 3 "register_operand"  " vr, vr")
-	     (match_operand:<VEL> 4 "reg_or_0_operand"   " rJ, rJ")] VSAT_ARITH_OP)
-	  (match_operand:VI_QHS 2 "vector_merge_operand" "0vu,0vu")))]
+	    [(match_operand:VI_QHS 3 "register_operand"  " vr, vr, vr, vr")
+	     (match_operand:<VEL> 4 "reg_or_0_operand"   " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
+	  (match_operand:VI_QHS 2 "vector_merge_operand" " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<sat_op>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<sat_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_<sat_op><mode>_scalar"
-  [(set (match_operand:VI 0 "register_operand"             "=vd, vr")
+  [(set (match_operand:VI 0 "register_operand"             "=vd, vr, vd, vr")
 	(if_then_else:VI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"   " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"      " rK, rK")
-	     (match_operand 6 "const_int_operand"          "  i,  i")
-	     (match_operand 7 "const_int_operand"          "  i,  i")
-	     (match_operand 8 "const_int_operand"          "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"   " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"      " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"          "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"          "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"          "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI
-	    [(match_operand:VI 3 "register_operand"        " vr, vr")
-	     (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] VSAT_SHIFT_OP)
-	  (match_operand:VI 2 "vector_merge_operand"       "0vu,0vu")))]
+	    [(match_operand:VI 3 "register_operand"        " vr, vr, vr, vr")
+	     (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSAT_SHIFT_OP)
+	  (match_operand:VI 2 "vector_merge_operand"       " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<sat_op>.v%o4\t%0,%3,%4%p1"
   [(set_attr "type" "<sat_insn_type>")
@@ -3429,41 +3454,41 @@ 
 })
 
 (define_insn "*pred_<sat_op><mode>_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"         "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"         "=vd, vr, vd, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"    " rK, rK")
-	     (match_operand 6 "const_int_operand"        "  i,  i")
-	     (match_operand 7 "const_int_operand"        "  i,  i")
-	     (match_operand 8 "const_int_operand"        "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"    " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"        "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"        "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_D
-	    [(match_operand:VI_D 3 "register_operand"    " vr, vr")
-	     (match_operand:<VEL> 4 "reg_or_0_operand"   " rJ, rJ")] VSAT_ARITH_OP)
-	  (match_operand:VI_D 2 "vector_merge_operand"   "0vu,0vu")))]
+	    [(match_operand:VI_D 3 "register_operand"    " vr, vr, vr, vr")
+	     (match_operand:<VEL> 4 "reg_or_0_operand"   " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
+	  (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<sat_op>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<sat_insn_type>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*pred_<sat_op><mode>_extended_scalar"
-  [(set (match_operand:VI_D 0 "register_operand"            "=vd, vr")
+  [(set (match_operand:VI_D 0 "register_operand"            "=vd, vr, vd, vr")
 	(if_then_else:VI_D
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"    " vm,Wc1")
-	     (match_operand 5 "vector_length_operand"       " rK, rK")
-	     (match_operand 6 "const_int_operand"           "  i,  i")
-	     (match_operand 7 "const_int_operand"           "  i,  i")
-	     (match_operand 8 "const_int_operand"           "  i,  i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"    " vm, vm,Wc1,Wc1")
+	     (match_operand 5 "vector_length_operand"       " rK, rK, rK, rK")
+	     (match_operand 6 "const_int_operand"           "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"           "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"           "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (unspec:VI_D
-	    [(match_operand:VI_D 3 "register_operand"       " vr, vr")
+	    [(match_operand:VI_D 3 "register_operand"       " vr, vr, vr, vr")
 	     (sign_extend:<VEL>
-	       (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))] VSAT_ARITH_OP)
-	  (match_operand:VI_D 2 "vector_merge_operand"      "0vu,0vu")))]
+	       (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSAT_ARITH_OP)
+	  (match_operand:VI_D 2 "vector_merge_operand"      " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "v<sat_op>.vx\t%0,%3,%z4%p1"
   [(set_attr "type" "<sat_insn_type>")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-1.c
new file mode 100644
index 00000000000..380d67fab53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/merge_constraint-1.c
@@ -0,0 +1,204 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+
+#include "riscv_vector.h"
+
+void f (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vmv_v_v_i8mf4 (v, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f2 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vmv_v_x_i8mf4_tu (v, 3, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f3 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  vint8mf4_t v2 = __riscv_vle8_v_i8mf4 (base1 + 100, 32);
+  vbool32_t m = __riscv_vlm_v_b32 (base1 + 200, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vmerge_vvm_i8mf4 (v, v2, m, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f4 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  vbool32_t m = __riscv_vlm_v_b32 (base1 + 200, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vmerge_vxm_i8mf4 (v, 3, m, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f5 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  vbool32_t m = __riscv_vlm_v_b32 (base1 + 200, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vmerge_vxm_i8mf4 (v, 100, m, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f6 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vuint8mf4_t v = __riscv_vle8_v_u8mf4 (base1 + 100, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vluxei8_v_u8mf4 (base2, v, 32);
+    v = __riscv_vle8_v_u8mf4_tu (v, base2 + 200, 32);
+  }
+  __riscv_vse8_v_u8mf4 (out, v, 32);
+}
+
+void f7 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vadd_vv_i8mf4 (v, v, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f8 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vadd_vv_i8mf4 (v, v, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f9 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vsll_vx_i8mf4 (v, 101, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f10 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vor_vx_i8mf4 (v, 101, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f11 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  vbool32_t m = __riscv_vlm_v_b32 (base1 + 200, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vadc_vvm_i8mf4 (v, v, m, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f12 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  vbool32_t m = __riscv_vlm_v_b32 (base1 + 200, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vsbc_vvm_i8mf4 (v, v, m, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f13 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  vbool32_t m = __riscv_vlm_v_b32 (base1 + 200, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vadc_vxm_i8mf4 (v, 100, m, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f14 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  vbool32_t m = __riscv_vlm_v_b32 (base1 + 200, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vsbc_vxm_i8mf4 (v, 100, m, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f15 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vneg_v_i8mf4 (v, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f16 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vsadd_vv_i8mf4 (v, v, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f17 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vsadd_vx_i8mf4 (v, 100, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f18 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vaadd_vv_i8mf4 (v, v, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+void f19 (int8_t* base1,int8_t* base2,int8_t* out,int n)
+{
+  vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32);
+  for (int i = 0; i < n; i++){
+    v = __riscv_vaadd_vx_i8mf4 (v, 100, 32);
+    v = __riscv_vle8_v_i8mf4_tu (v, base2, 32);
+  }
+  __riscv_vse8_v_i8mf4 (out, v, 32);
+}
+
+/* { dg-final { scan-assembler-not {vmv1r} } } */