RISC-V: Add permutation C/C++ support

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 9e017b49c19..0e342b5d832 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -185,6 +185,18 @@  bool has_vi_variant_p (rtx_code, rtx);
 bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, machine_mode,
 			  bool, void (*)(rtx *, rtx));
 rtx gen_scalar_move_mask (machine_mode);
+
+/* RVV vector register sizes.
+   TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to
+   support other values in the future.  */
+enum vlen_enum
+{
+  RVV_32 = 32,
+  RVV_64 = 64,
+  RVV_65536 = 65536
+};
+bool slide1_sew64_helper (int, machine_mode, machine_mode,
+			  machine_mode, rtx *);
 }
 
 /* We classify builtin types into two classes:
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index c2209990882..d65c65b26cd 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -495,4 +495,175 @@  gen_scalar_move_mask (machine_mode mode)
   return builder.build ();
 }
 
+static unsigned
+compute_vlmax (unsigned vector_bits, unsigned elt_size, unsigned min_size)
+{
+  // Original equation:
+  //   VLMAX = (VectorBits / EltSize) * LMUL
+  //   where LMUL = MinSize / TARGET_MIN_VLEN
+  // The following equations have been reordered to prevent loss of precision
+  // when calculating fractional LMUL.
+  return ((vector_bits / elt_size) * min_size) / TARGET_MIN_VLEN;
+}
+
+static unsigned
+get_unknown_min_value (machine_mode mode)
+{
+  enum vlmul_type vlmul = get_vlmul (mode);
+  switch (vlmul)
+    {
+    case LMUL_1:
+      return TARGET_MIN_VLEN;
+    case LMUL_2:
+      return TARGET_MIN_VLEN * 2;
+    case LMUL_4:
+      return TARGET_MIN_VLEN * 4;
+    case LMUL_8:
+      return TARGET_MIN_VLEN * 8;
+    default:
+      gcc_unreachable ();
+    }
+}
+
+static rtx
+force_vector_length_operand (rtx vl)
+{
+  if (CONST_INT_P (vl) && !satisfies_constraint_K (vl))
+    return force_reg (Pmode, vl);
+  return vl;
+}
+
+static rtx
+gen_no_side_effects_vsetvl_rtx (machine_mode vmode, rtx vl, rtx avl)
+{
+  unsigned int sew = GET_MODE_CLASS (vmode) == MODE_VECTOR_BOOL
+		       ? 8
+		       : GET_MODE_BITSIZE (GET_MODE_INNER (vmode));
+  return gen_vsetvl_no_side_effects (Pmode, vl, avl, gen_int_mode (sew, Pmode),
+				     gen_int_mode (get_vlmul (vmode), Pmode),
+				     const0_rtx, const0_rtx);
+}
+
+/* GET VL * 2 rtx.  */
+static rtx
+get_vl_x2_rtx (rtx avl, machine_mode mode, machine_mode demote_mode)
+{
+  rtx i32vl = NULL_RTX;
+  if (CONST_INT_P (avl))
+    {
+      unsigned elt_size = GET_MODE_BITSIZE (GET_MODE_INNER (mode));
+      unsigned min_size = get_unknown_min_value (mode);
+      unsigned vlen_max = RVV_65536;
+      unsigned vlmax_max = compute_vlmax (vlen_max, elt_size, min_size);
+      unsigned vlen_min = TARGET_MIN_VLEN;
+      unsigned vlmax_min = compute_vlmax (vlen_min, elt_size, min_size);
+
+      unsigned HOST_WIDE_INT avl_int = INTVAL (avl);
+      if (avl_int <= vlmax_min)
+	i32vl = gen_int_mode (2 * avl_int, Pmode);
+      else if (avl_int >= 2 * vlmax_max)
+	{
+	  // Just set i32vl to VLMAX in this situation
+	  i32vl = gen_reg_rtx (Pmode);
+	  emit_insn (
+	    gen_no_side_effects_vsetvl_rtx (demote_mode, i32vl, RVV_VLMAX));
+	}
+      else
+	{
+	  // For AVL between (MinVLMAX, 2 * MaxVLMAX), the actual working vl
+	  // is related to the hardware implementation.
+	  // So let the following code handle
+	}
+    }
+  if (!i32vl)
+    {
+      // Using vsetvli instruction to get actually used length which related to
+      // the hardware implementation
+      rtx i64vl = gen_reg_rtx (Pmode);
+      emit_insn (
+	gen_no_side_effects_vsetvl_rtx (mode, i64vl, force_reg (Pmode, avl)));
+      // scale 2 for 32-bit length
+      i32vl = gen_reg_rtx (Pmode);
+      emit_insn (
+	gen_rtx_SET (i32vl, gen_rtx_ASHIFT (Pmode, i64vl, const1_rtx)));
+    }
+
+  return force_vector_length_operand (i32vl);
+}
+
+bool
+slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode,
+		     machine_mode demote_mask_mode, rtx *ops)
+{
+  rtx scalar_op = ops[4];
+  rtx avl = ops[5];
+  machine_mode scalar_mode = GET_MODE_INNER (mode);
+  if (rtx_equal_p (scalar_op, const0_rtx))
+    {
+      ops[5] = force_vector_length_operand (ops[5]);
+      return false;
+    }
+
+  if (TARGET_64BIT)
+    {
+      ops[4] = force_reg (scalar_mode, scalar_op);
+      ops[5] = force_vector_length_operand (ops[5]);
+      return false;
+    }
+
+  if (immediate_operand (scalar_op, Pmode))
+    {
+      ops[4] = gen_rtx_SIGN_EXTEND (scalar_mode, force_reg (Pmode, scalar_op));
+      ops[5] = force_vector_length_operand (ops[5]);
+      return false;
+    }
+
+  if (CONST_INT_P (scalar_op))
+    scalar_op = force_reg (scalar_mode, scalar_op);
+
+  rtx vl_x2 = get_vl_x2_rtx (avl, mode, demote_mode);
+
+  rtx demote_scalar_op1, demote_scalar_op2;
+  if (unspec == UNSPEC_VSLIDE1UP)
+    {
+      demote_scalar_op1 = gen_highpart (Pmode, scalar_op);
+      demote_scalar_op2 = gen_lowpart (Pmode, scalar_op);
+    }
+  else
+    {
+      demote_scalar_op1 = gen_lowpart (Pmode, scalar_op);
+      demote_scalar_op2 = gen_highpart (Pmode, scalar_op);
+    }
+
+  rtx temp = gen_reg_rtx (demote_mode);
+  rtx ta = gen_int_mode (get_prefer_tail_policy (), Pmode);
+  rtx ma = gen_int_mode (get_prefer_mask_policy (), Pmode);
+  rtx merge = RVV_VUNDEF (demote_mode);
+  /* Handle vslide1<ud>_tu.  */
+  if (register_operand (ops[2], mode)
+      && rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]))))
+    {
+      merge = gen_lowpart (demote_mode, ops[2]);
+      ta = ops[6];
+      ma = ops[7];
+    }
+
+  emit_insn (gen_pred_slide (unspec, demote_mode, temp,
+			     CONSTM1_RTX (demote_mask_mode), merge,
+			     gen_lowpart (demote_mode, ops[3]),
+			     demote_scalar_op1, vl_x2, ta, ma, ops[8]));
+  emit_insn (gen_pred_slide (unspec, demote_mode,
+			     gen_lowpart (demote_mode, ops[0]),
+			     CONSTM1_RTX (demote_mask_mode), merge, temp,
+			     demote_scalar_op2, vl_x2, ta, ma, ops[8]));
+
+  if (rtx_equal_p (ops[1], CONSTM1_RTX (GET_MODE (ops[1]))))
+    return true;
+  else
+    emit_insn (gen_pred_merge (mode, ops[0], ops[2], ops[2], ops[0], ops[1],
+			       force_vector_length_operand (ops[5]), ops[6],
+			       ops[8]));
+  return true;
+}
+
 } // namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 7b27cc31fc7..1797c70e7b1 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1367,6 +1367,61 @@  public:
   }
 };
 
+template<int UNSPEC>
+class slideop : public function_base
+{
+public:
+  bool has_merge_operand_p () const override
+  {
+    if (UNSPEC == UNSPEC_VSLIDEUP)
+      return false;
+    return true;
+  }
+
+  rtx expand (function_expander &e) const override
+  {
+    return e.use_exact_insn (code_for_pred_slide (UNSPEC, e.vector_mode ()));
+  }
+};
+
+class vrgather : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+    switch (e.op_info->op)
+      {
+      case OP_TYPE_vx:
+	return e.use_exact_insn (
+	  code_for_pred_gather_scalar (e.vector_mode ()));
+      case OP_TYPE_vv:
+	return e.use_exact_insn (code_for_pred_gather (e.vector_mode ()));
+      default:
+	gcc_unreachable ();
+      }
+  }
+};
+
+class vrgatherei16 : public function_base
+{
+public:
+  rtx expand (function_expander &e) const override
+  {
+    return e.use_exact_insn (code_for_pred_gatherei16 (e.vector_mode ()));
+  }
+};
+
+class vcompress : public function_base
+{
+public:
+  bool apply_mask_policy_p () const override { return false; }
+  bool use_mask_predication_p () const override { return false; }
+  rtx expand (function_expander &e) const override
+  {
+    return e.use_exact_insn (code_for_pred_compress (e.vector_mode ()));
+  }
+};
+
 static CONSTEXPR const vsetvl<false> vsetvl_obj;
 static CONSTEXPR const vsetvl<true> vsetvlmax_obj;
 static CONSTEXPR const loadstore<false, LST_UNIT_STRIDE, false> vle_obj;
@@ -1560,6 +1615,15 @@  static CONSTEXPR const vmv vmv_x_obj;
 static CONSTEXPR const vmv_s vmv_s_obj;
 static CONSTEXPR const vmv vfmv_f_obj;
 static CONSTEXPR const vmv_s vfmv_s_obj;
+static CONSTEXPR const slideop<UNSPEC_VSLIDEUP> vslideup_obj;
+static CONSTEXPR const slideop<UNSPEC_VSLIDEDOWN> vslidedown_obj;
+static CONSTEXPR const slideop<UNSPEC_VSLIDE1UP> vslide1up_obj;
+static CONSTEXPR const slideop<UNSPEC_VSLIDE1DOWN> vslide1down_obj;
+static CONSTEXPR const slideop<UNSPEC_VFSLIDE1UP> vfslide1up_obj;
+static CONSTEXPR const slideop<UNSPEC_VFSLIDE1DOWN> vfslide1down_obj;
+static CONSTEXPR const vrgather vrgather_obj;
+static CONSTEXPR const vrgatherei16 vrgatherei16_obj;
+static CONSTEXPR const vcompress vcompress_obj;
 
 /* Declare the function base NAME, pointing it to an instance
    of class <NAME>_obj.  */
@@ -1759,5 +1823,14 @@  BASE (vmv_x)
 BASE (vmv_s)
 BASE (vfmv_f)
 BASE (vfmv_s)
+BASE (vslideup)
+BASE (vslidedown)
+BASE (vslide1up)
+BASE (vslide1down)
+BASE (vfslide1up)
+BASE (vfslide1down)
+BASE (vrgather)
+BASE (vrgatherei16)
+BASE (vcompress)
 
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h
index ad1ee207d2f..5078bcf9c72 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -223,6 +223,15 @@  extern const function_base *const vmv_x;
 extern const function_base *const vmv_s;
 extern const function_base *const vfmv_f;
 extern const function_base *const vfmv_s;
+extern const function_base *const vslideup;
+extern const function_base *const vslidedown;
+extern const function_base *const vslide1up;
+extern const function_base *const vslide1down;
+extern const function_base *const vfslide1up;
+extern const function_base *const vfslide1down;
+extern const function_base *const vrgather;
+extern const function_base *const vrgatherei16;
+extern const function_base *const vcompress;
 }
 
 } // end namespace riscv_vector
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index cad98f6230d..638daa24596 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -475,11 +475,19 @@  DEF_RVV_FUNCTION (vfmv_f, scalar_move, none_preds, f_f_s_ops)
 DEF_RVV_FUNCTION (vfmv_s, move, none_tu_preds, f_s_f_ops)
 
 // 16.3. Vector Slide Instructions
+DEF_RVV_FUNCTION (vslideup, alu, full_preds, all_vvvx_ops)
+DEF_RVV_FUNCTION (vslidedown, alu, full_preds, all_vvx_ops)
+DEF_RVV_FUNCTION (vslide1up, alu, full_preds, iu_vvx_ops)
+DEF_RVV_FUNCTION (vslide1down, alu, full_preds, iu_vvx_ops)
+DEF_RVV_FUNCTION (vfslide1up, alu, full_preds, f_vvf_ops)
+DEF_RVV_FUNCTION (vfslide1down, alu, full_preds, f_vvf_ops)
 
 // 16.4. Vector Register Gather Instructions
+DEF_RVV_FUNCTION (vrgather, alu, full_preds, all_gather_vvv_ops)
+DEF_RVV_FUNCTION (vrgather, alu, full_preds, all_gather_vvx_ops)
+DEF_RVV_FUNCTION (vrgatherei16, alu, full_preds, all_gatherei16_vvv_ops)
 
 // 16.5. Vector Compress Instruction
-
-// 16.6. Whole Vector Register Move
+DEF_RVV_FUNCTION (vcompress, alu, none_tu_preds, all_vvm_ops)
 
 #undef DEF_RVV_FUNCTION
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def
index a15e54c1572..a77024f823f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -151,6 +151,12 @@  along with GCC; see the file COPYING3. If not see
 #define DEF_RVV_WF_OPS(TYPE, REQUIRE)
 #endif
 
+/* Use "DEF_RVV_EI16_OPS" macro include all types for vrgatherei16 which will be
+   iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_EI16_OPS
+#define DEF_RVV_EI16_OPS(TYPE, REQUIRE)
+#endif
+
 DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
 DEF_RVV_I_OPS (vint8mf4_t, 0)
 DEF_RVV_I_OPS (vint8mf2_t, 0)
@@ -407,6 +413,58 @@  DEF_RVV_WF_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
 DEF_RVV_WF_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
 DEF_RVV_WF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
 
+DEF_RVV_EI16_OPS (vint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint8mf4_t, 0)
+DEF_RVV_EI16_OPS (vint8mf2_t, 0)
+DEF_RVV_EI16_OPS (vint8m1_t, 0)
+DEF_RVV_EI16_OPS (vint8m2_t, 0)
+DEF_RVV_EI16_OPS (vint8m4_t, 0)
+DEF_RVV_EI16_OPS (vint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint16mf2_t, 0)
+DEF_RVV_EI16_OPS (vint16m1_t, 0)
+DEF_RVV_EI16_OPS (vint16m2_t, 0)
+DEF_RVV_EI16_OPS (vint16m4_t, 0)
+DEF_RVV_EI16_OPS (vint16m8_t, 0)
+DEF_RVV_EI16_OPS (vint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint32m1_t, 0)
+DEF_RVV_EI16_OPS (vint32m2_t, 0)
+DEF_RVV_EI16_OPS (vint32m4_t, 0)
+DEF_RVV_EI16_OPS (vint32m8_t, 0)
+DEF_RVV_EI16_OPS (vint64m1_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint64m2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint64m4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint8mf8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint8mf4_t, 0)
+DEF_RVV_EI16_OPS (vuint8mf2_t, 0)
+DEF_RVV_EI16_OPS (vuint8m1_t, 0)
+DEF_RVV_EI16_OPS (vuint8m2_t, 0)
+DEF_RVV_EI16_OPS (vuint8m4_t, 0)
+DEF_RVV_EI16_OPS (vuint16mf4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint16mf2_t, 0)
+DEF_RVV_EI16_OPS (vuint16m1_t, 0)
+DEF_RVV_EI16_OPS (vuint16m2_t, 0)
+DEF_RVV_EI16_OPS (vuint16m4_t, 0)
+DEF_RVV_EI16_OPS (vuint16m8_t, 0)
+DEF_RVV_EI16_OPS (vuint32mf2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint32m1_t, 0)
+DEF_RVV_EI16_OPS (vuint32m2_t, 0)
+DEF_RVV_EI16_OPS (vuint32m4_t, 0)
+DEF_RVV_EI16_OPS (vuint32m8_t, 0)
+DEF_RVV_EI16_OPS (vuint64m1_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint64m2_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint64m4_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vuint64m8_t, RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_ZVE64)
+DEF_RVV_EI16_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_EI16_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_EI16_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_EI16_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
+DEF_RVV_EI16_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
+DEF_RVV_EI16_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
+DEF_RVV_EI16_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
+DEF_RVV_EI16_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64)
+
 #undef DEF_RVV_I_OPS
 #undef DEF_RVV_U_OPS
 #undef DEF_RVV_F_OPS
@@ -428,3 +486,4 @@  DEF_RVV_WF_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
 #undef DEF_RVV_WI_OPS
 #undef DEF_RVV_WU_OPS
 #undef DEF_RVV_WF_OPS
+#undef DEF_RVV_EI16_OPS
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index af11758e9b4..6b32b28952a 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -219,6 +219,12 @@  static const rvv_type_info all_ops[] = {
 #include "riscv-vector-builtins-types.def"
   {NUM_VECTOR_TYPES, 0}};
 
+/* A list of all types will be registered for intrinsic functions.  */
+static const rvv_type_info ei16_ops[] = {
+#define DEF_RVV_EI16_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
+#include "riscv-vector-builtins-types.def"
+  {NUM_VECTOR_TYPES, 0}};
+
 /* A list of all bool will be registered for intrinsic functions.  */
 static const rvv_type_info b_ops[] = {
 #define DEF_RVV_B_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
@@ -399,6 +405,12 @@  static CONSTEXPR const rvv_arg_type_info vvm_args[]
   = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info (RVV_BASE_vector),
      rvv_arg_type_info (RVV_BASE_mask), rvv_arg_type_info_end};
 
+/* A list of args for vector_type func (vector_type, mask_type)
+ * function.  */
+static CONSTEXPR const rvv_arg_type_info vm_args[]
+  = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info (RVV_BASE_mask),
+     rvv_arg_type_info_end};
+
 /* A list of args for vector_type func (vector_type, scalar_type, mask_type)
  * function.  */
 static CONSTEXPR const rvv_arg_type_info vxm_args[]
@@ -427,6 +439,16 @@  static CONSTEXPR const rvv_arg_type_info shift_vv_args[]
   = {rvv_arg_type_info (RVV_BASE_vector),
      rvv_arg_type_info (RVV_BASE_shift_vector), rvv_arg_type_info_end};
 
+/* A list of args for vector_type func (vector_type, shift_type) function.  */
+static CONSTEXPR const rvv_arg_type_info gather_vv_args[]
+  = {rvv_arg_type_info (RVV_BASE_vector),
+     rvv_arg_type_info (RVV_BASE_unsigned_vector), rvv_arg_type_info_end};
+
+/* A list of args for vector_type func (vector_type, shift_type) function.  */
+static CONSTEXPR const rvv_arg_type_info gatherei16_vv_args[]
+  = {rvv_arg_type_info (RVV_BASE_vector),
+     rvv_arg_type_info (RVV_BASE_uint16_index), rvv_arg_type_info_end};
+
 /* A list of args for double demote type func (vector_type, shift_type)
  * function.  */
 static CONSTEXPR const rvv_arg_type_info shift_wv_args[]
@@ -471,10 +493,16 @@  static CONSTEXPR const rvv_arg_type_info x_args[]
   = {rvv_arg_type_info (RVV_BASE_scalar), rvv_arg_type_info_end};
 
 /* A list of args for vector_type func (vector_type, size) function.  */
-static CONSTEXPR const rvv_arg_type_info vector_size_args[]
+static CONSTEXPR const rvv_arg_type_info v_size_args[]
   = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info (RVV_BASE_size),
      rvv_arg_type_info_end};
 
+/* A list of args for vector_type func (vector_type, vector_type, size)
+ * function.  */
+static CONSTEXPR const rvv_arg_type_info vv_size_args[]
+  = {rvv_arg_type_info (RVV_BASE_vector), rvv_arg_type_info (RVV_BASE_vector),
+     rvv_arg_type_info (RVV_BASE_size), rvv_arg_type_info_end};
+
 /* A list of args for vector_type func (double demote type) function.  */
 static CONSTEXPR const rvv_arg_type_info vf2_args[]
   = {rvv_arg_type_info (RVV_BASE_double_trunc_vector), rvv_arg_type_info_end};
@@ -848,6 +876,14 @@  static CONSTEXPR const rvv_op_info all_vvvm_ops
      rvv_arg_type_info (RVV_BASE_vector), /* Return type */
      vvm_args /* Args */};
 
+/* A static operand information for vector_type func (vector_type, vector_type,
+ * mask_type) function registration. */
+static CONSTEXPR const rvv_op_info all_vvm_ops
+  = {all_ops,				  /* Types */
+     OP_TYPE_vm,			  /* Suffix */
+     rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+     vm_args /* Args */};
+
 /* A static operand information for vector_type func (vector_type, scalar_type,
  * mask_type) function registration. */
 static CONSTEXPR const rvv_op_info iu_vvxm_ops
@@ -1008,6 +1044,22 @@  static CONSTEXPR const rvv_op_info iu_vvx_ops
      rvv_arg_type_info (RVV_BASE_vector), /* Return type */
      vx_args /* Args */};
 
+/* A static operand information for vector_type func (vector_type, scalar_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info all_vvx_ops
+  = {all_ops,				  /* Types */
+     OP_TYPE_vx,			  /* Suffix */
+     rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+     v_size_args /* Args */};
+
+/* A static operand information for vector_type func (vector_type, vector_type,
+ * scalar_type) function registration. */
+static CONSTEXPR const rvv_op_info all_vvvx_ops
+  = {all_ops,				  /* Types */
+     OP_TYPE_vx,			  /* Suffix */
+     rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+     vv_size_args /* Args */};
+
 /* A static operand information for vector_type func (vector_type, scalar_type)
  * function registration. */
 static CONSTEXPR const rvv_op_info i_vvx_ops
@@ -1063,7 +1115,7 @@  static CONSTEXPR const rvv_op_info iu_shift_vvx_ops
   = {iu_ops,				  /* Types */
      OP_TYPE_vx,			  /* Suffix */
      rvv_arg_type_info (RVV_BASE_vector), /* Return type */
-     vector_size_args /* Args */};
+     v_size_args /* Args */};
 
 /* A static operand information for vector_type func (vector_type, shift_type)
  * function registration. */
@@ -1079,7 +1131,7 @@  static CONSTEXPR const rvv_op_info i_shift_vvx_ops
   = {i_ops,				  /* Types */
      OP_TYPE_vx,			  /* Suffix */
      rvv_arg_type_info (RVV_BASE_vector), /* Return type */
-     vector_size_args /* Args */};
+     v_size_args /* Args */};
 
 /* A static operand information for vector_type func (vector_type, shift_type)
  * function registration. */
@@ -1095,7 +1147,31 @@  static CONSTEXPR const rvv_op_info u_shift_vvx_ops
   = {u_ops,				  /* Types */
      OP_TYPE_vx,			  /* Suffix */
      rvv_arg_type_info (RVV_BASE_vector), /* Return type */
-     vector_size_args /* Args */};
+     v_size_args /* Args */};
+
+/* A static operand information for vector_type func (vector_type, index_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info all_gather_vvv_ops
+  = {all_ops,				  /* Types */
+     OP_TYPE_vv,			  /* Suffix */
+     rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+     gather_vv_args /* Args */};
+
+/* A static operand information for vector_type func (vector_type, size_t)
+ * function registration. */
+static CONSTEXPR const rvv_op_info all_gather_vvx_ops
+  = {all_ops,				  /* Types */
+     OP_TYPE_vx,			  /* Suffix */
+     rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+     v_size_args /* Args */};
+
+/* A static operand information for vector_type func (vector_type, index_type)
+ * function registration. */
+static CONSTEXPR const rvv_op_info all_gatherei16_vvv_ops
+  = {ei16_ops,				  /* Types */
+     OP_TYPE_vv,			  /* Suffix */
+     rvv_arg_type_info (RVV_BASE_vector), /* Return type */
+     gatherei16_vv_args /* Args */};
 
 /* A static operand information for vector_type func (vector_type)
  * function registration. */
@@ -1600,7 +1676,7 @@  static CONSTEXPR const rvv_op_info i_narrow_shift_vwx_ops
   = {wexti_ops,					       /* Types */
      OP_TYPE_wx,				       /* Suffix */
      rvv_arg_type_info (RVV_BASE_double_trunc_vector), /* Return type */
-     vector_size_args /* Args */};
+     v_size_args /* Args */};
 
 /* A static operand information for double demote type func (vector_type,
  * size_t) function registration. */
@@ -1608,7 +1684,7 @@  static CONSTEXPR const rvv_op_info u_narrow_shift_vwx_ops
   = {wextu_ops,					       /* Types */
      OP_TYPE_wx,				       /* Suffix */
      rvv_arg_type_info (RVV_BASE_double_trunc_vector), /* Return type */
-     vector_size_args /* Args */};
+     v_size_args /* Args */};
 
 /* A static operand information for double demote type func (vector_type)
  * function registration. */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 55f7b12aaa9..a08b5edbc3d 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -311,7 +311,7 @@ 
 ;; viwred      vector widening integer reduction instructions
 ;; vfredu      vector single-width floating-point un-ordered reduction instruction
 ;; vfredo      vector single-width floating-point ordered reduction instruction
-;; vfwredu      vector widening floating-point un-ordered reduction instruction
+;; vfwredu     vector widening floating-point un-ordered reduction instruction
 ;; vfwredo     vector widening floating-point ordered reduction instruction
 ;; 15. Vector mask instructions
 ;; vmalu       vector mask-register logical instructions
@@ -321,16 +321,19 @@ 
 ;; vmiota      vector iota
 ;; vmidx       vector element index instruction
 ;; 16. Vector permutation instructions
-;; vimovvx     integer scalar move instructions
-;; vimovxv     integer scalar move instructions
-;; vfmovvf     floating-point scalar move instructions
-;; vfmovfv     floating-point scalar move instructions
-;; vislide     vector slide instructions
-;; vislide1    vector slide instructions
-;; vfslide1    vector slide instructions
-;; vgather     vector register gather instructions
-;; vcompress   vector compress instruction
-;; vmov        whole vector register move
+;; vimovvx      integer scalar move instructions
+;; vimovxv      integer scalar move instructions
+;; vfmovvf      floating-point scalar move instructions
+;; vfmovfv      floating-point scalar move instructions
+;; vslideup     vector slide instructions
+;; vslidedown   vector slide instructions
+;; vislide1up   vector slide instructions
+;; vislide1down vector slide instructions
+;; vfslide1up   vector slide instructions
+;; vfslide1down vector slide instructions
+;; vgather      vector register gather instructions
+;; vcompress    vector compress instruction
+;; vmov         whole vector register move
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
@@ -346,7 +349,8 @@ 
    vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,
    vired,viwred,vfredu,vfredo,vfwredu,vfwredo,
    vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,
-   vislide,vislide1,vfslide1,vgather,vcompress,vmov"
+   vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,
+   vgather,vcompress,vmov"
   (cond [(eq_attr "got" "load") (const_string "load")
 
 	 ;; If a doubleword move uses these expensive instructions,
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index a4211c70e51..0eebe53f121 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -70,6 +70,15 @@ 
   UNSPEC_REDUC
   UNSPEC_WREDUC_SUM
   UNSPEC_WREDUC_USUM
+  UNSPEC_VSLIDEUP
+  UNSPEC_VSLIDEDOWN
+  UNSPEC_VSLIDE1UP
+  UNSPEC_VSLIDE1DOWN
+  UNSPEC_VFSLIDE1UP
+  UNSPEC_VFSLIDE1DOWN
+  UNSPEC_VRGATHER
+  UNSPEC_VRGATHEREI16
+  UNSPEC_VCOMPRESS
 ])
 
 (define_mode_iterator V [
@@ -89,6 +98,23 @@ 
   (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
 ])
 
+(define_mode_iterator VEI16 [
+  VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI
+  VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32")
+  VNx1SI VNx2SI VNx4SI VNx8SI (VNx16SI "TARGET_MIN_VLEN > 32")
+  (VNx1DI "TARGET_MIN_VLEN > 32") (VNx2DI "TARGET_MIN_VLEN > 32")
+  (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32")
+  (VNx1SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx8SF "TARGET_VECTOR_ELEN_FP_32")
+  (VNx16SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+  (VNx1DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx2DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx4DF "TARGET_VECTOR_ELEN_FP_64")
+  (VNx8DF "TARGET_VECTOR_ELEN_FP_64")
+])
+
 (define_mode_iterator VI [
   VNx1QI VNx2QI VNx4QI VNx8QI VNx16QI VNx32QI (VNx64QI "TARGET_MIN_VLEN > 32")
   VNx1HI VNx2HI VNx4HI VNx8HI VNx16HI (VNx32HI "TARGET_MIN_VLEN > 32")
@@ -291,6 +317,32 @@ 
   (VNx4DI "TARGET_MIN_VLEN > 32") (VNx8DI "TARGET_MIN_VLEN > 32")
 ])
 
+(define_mode_attr VINDEX [
+  (VNx1QI "VNx1QI") (VNx2QI "VNx2QI") (VNx4QI "VNx4QI") (VNx8QI "VNx8QI")
+  (VNx16QI "VNx16QI") (VNx32QI "VNx32QI") (VNx64QI "VNx64QI")
+  (VNx1HI "VNx1HI") (VNx2HI "VNx2HI") (VNx4HI "VNx4HI") (VNx8HI "VNx8HI")
+  (VNx16HI "VNx16HI") (VNx32HI "VNx32HI")
+  (VNx1SI "VNx1SI") (VNx2SI "VNx2SI") (VNx4SI "VNx4SI") (VNx8SI "VNx8SI")
+  (VNx16SI "VNx16SI")
+  (VNx1DI "VNx1DI") (VNx2DI "VNx2DI") (VNx4DI "VNx4DI") (VNx8DI "VNx8DI")
+  (VNx1SF "VNx1SI") (VNx2SF "VNx2SI") (VNx4SF "VNx4SI") (VNx8SF "VNx8SI")
+  (VNx16SF "VNx16SI")
+  (VNx1DF "VNx1DI") (VNx2DF "VNx2DI") (VNx4DF "VNx4DI") (VNx8DF "VNx8DI")
+])
+
+(define_mode_attr VINDEXEI16 [
+  (VNx1QI "VNx1HI") (VNx2QI "VNx2HI") (VNx4QI "VNx4HI") (VNx8QI "VNx8HI")
+  (VNx16QI "VNx16HI") (VNx32QI "VNx32HI")
+  (VNx1HI "VNx1HI") (VNx2HI "VNx2HI") (VNx4HI "VNx4HI") (VNx8HI "VNx8HI")
+  (VNx16HI "VNx16HI") (VNx32HI "VNx32HI")
+  (VNx1SI "VNx1HI") (VNx2SI "VNx2HI") (VNx4SI "VNx4HI") (VNx8SI "VNx8HI")
+  (VNx16SI "VNx16HI")
+  (VNx1DI "VNx1HI") (VNx2DI "VNx2HI") (VNx4DI "VNx4HI") (VNx8DI "VNx8HI")
+  (VNx1SF "VNx1HI") (VNx2SF "VNx2HI") (VNx4SF "VNx4HI") (VNx8SF "VNx8HI")
+  (VNx16SF "VNx16HI")
+  (VNx1DF "VNx1HI") (VNx2DF "VNx2HI") (VNx4DF "VNx4HI") (VNx8DF "VNx8HI")
+])
+
 (define_mode_attr VM [
   (VNx1QI "VNx1BI") (VNx2QI "VNx2BI") (VNx4QI "VNx4BI") (VNx8QI "VNx8BI") (VNx16QI "VNx16BI") (VNx32QI "VNx32BI") (VNx64QI "VNx64BI")
   (VNx1HI "VNx1BI") (VNx2HI "VNx2BI") (VNx4HI "VNx4BI") (VNx8HI "VNx8BI") (VNx16HI "VNx16BI") (VNx32HI "VNx32BI")
@@ -454,6 +506,16 @@ 
   (VNx8HI "vnx1si") (VNx16HI "vnx1SI")
 ])
 
+(define_mode_attr VDEMOTE [
+  (VNx1DI "VNx2SI") (VNx2DI "VNx4SI")
+  (VNx4DI "VNx8SI") (VNx8DI "VNx16SI")
+])
+
+(define_mode_attr VMDEMOTE [
+  (VNx1DI "VNx2BI") (VNx2DI "VNx4BI")
+  (VNx4DI "VNx8BI") (VNx8DI "VNx16BI")
+])
+
 (define_int_iterator WREDUC [UNSPEC_WREDUC_SUM UNSPEC_WREDUC_USUM])
 
 (define_int_iterator ORDER [UNSPEC_ORDERED UNSPEC_UNORDERED])
@@ -462,6 +524,10 @@ 
 
 (define_int_iterator VNCLIP [UNSPEC_VNCLIP UNSPEC_VNCLIPU])
 
+(define_int_iterator VSLIDES [UNSPEC_VSLIDEUP UNSPEC_VSLIDEDOWN])
+(define_int_iterator VSLIDES1 [UNSPEC_VSLIDE1UP UNSPEC_VSLIDE1DOWN])
+(define_int_iterator VFSLIDES1 [UNSPEC_VFSLIDE1UP UNSPEC_VFSLIDE1DOWN])
+
 (define_int_iterator VSAT_OP [UNSPEC_VAADDU UNSPEC_VAADD
 			      UNSPEC_VASUBU UNSPEC_VASUB UNSPEC_VSMUL
 			      UNSPEC_VSSRL UNSPEC_VSSRA])
@@ -508,6 +574,17 @@ 
 (define_int_attr nx [(UNSPEC_VCOPYSIGN "") (UNSPEC_VNCOPYSIGN "n")
 		     (UNSPEC_VXORSIGN "x")])
 
+(define_int_attr ud [(UNSPEC_VSLIDEUP "up") (UNSPEC_VSLIDEDOWN "down")
+		     (UNSPEC_VSLIDE1UP "1up") (UNSPEC_VSLIDE1DOWN "1down")
+		     (UNSPEC_VFSLIDE1UP "1up") (UNSPEC_VFSLIDE1DOWN "1down")])
+
+(define_int_attr ud_constraint [(UNSPEC_VSLIDEUP "=&vr,&vr") (UNSPEC_VSLIDEDOWN "=vd,vr")
+				(UNSPEC_VSLIDE1UP "=&vr,&vr") (UNSPEC_VSLIDE1DOWN "=vd,vr")
+				(UNSPEC_VFSLIDE1UP "=&vr,&vr") (UNSPEC_VFSLIDE1DOWN "=vd,vr")])
+
+(define_int_attr UNSPEC [(UNSPEC_VSLIDE1UP "UNSPEC_VSLIDE1UP")
+			 (UNSPEC_VSLIDE1DOWN "UNSPEC_VSLIDE1DOWN")])
+
 (define_code_iterator any_int_binop [plus minus and ior xor ashift ashiftrt lshiftrt
   smax umax smin umin mult div udiv mod umod
 ])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 60ac1e6bf79..b41b20dceaa 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -50,7 +50,8 @@ 
 			  vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
 			  vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
 			  vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,\
-			  vislide,vislide1,vfslide1,vgather,vcompress")
+			  vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
+			  vgather,vcompress")
 	 (const_string "true")]
 	(const_string "false")))
 
@@ -70,7 +71,8 @@ 
 			  vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
 			  vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
 			  vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovxv,vfmovfv,\
-			  vislide,vislide1,vfslide1,vgather,vcompress")
+			  vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
+			  vgather,vcompress")
 	 (const_string "true")]
 	(const_string "false")))
 
@@ -153,7 +155,9 @@ 
 			  vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
 			  vfncvtftof,vfmuladd,vfwmuladd,vfclass,vired,\
 			  viwred,vfredu,vfredo,vfwredu,vfwredo,vimovvx,\
-			  vimovxv,vfmovvf,vfmovfv")
+			  vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,\
+			  vislide1up,vislide1down,vfslide1up,vfslide1down,\
+			  vgather,vcompress")
 	   (const_int INVALID_ATTRIBUTE)
 	 (eq_attr "mode" "VNx1QI,VNx1BI")
 	   (symbol_ref "riscv_vector::get_ratio(E_VNx1QImode)")
@@ -209,10 +213,12 @@ 
 				vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
 				vfsqrt,vfrecp,vfsgnj,vfcmp,vfcvtitof,vfcvtftoi,vfwcvtitof,\
 				vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,\
-				vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv")
+				vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv,\
+				vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
+				vgather")
 	       (const_int 2)
 
-	       (eq_attr "type" "vimerge,vfmerge")
+	       (eq_attr "type" "vimerge,vfmerge,vcompress")
 	       (const_int 1)
 
 	       (eq_attr "type" "vimuladd,viwmuladd,vfmuladd,vfwmuladd")
@@ -224,7 +230,7 @@ 
   (cond [(eq_attr "type" "vlde,vste,vimov,vfmov,vldm,vstm,vmalu,vsts,vstux,\
 			  vstox,vext,vmsfs,vmiota,vfsqrt,vfrecp,vfcvtitof,\
 			  vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
-			  vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv")
+			  vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress")
 	   (const_int 4)
 
 	 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
@@ -237,7 +243,9 @@ 
 	 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
 			  viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
 			  vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
-			  vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo")
+			  vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
+			  vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
+			  vgather")
 	   (const_int 5)
 
 	 (eq_attr "type" "vicmp,vimuladd,viwmuladd,vfcmp,vfmuladd,vfwmuladd")
@@ -251,7 +259,8 @@ 
 (define_attr "ta" ""
   (cond [(eq_attr "type" "vlde,vimov,vfmov,vext,vmiota,vfsqrt,vfrecp,\
 			  vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\
-			  vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv")
+			  vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\
+			  vcompress")
 	   (symbol_ref "riscv_vector::get_ta(operands[5])")
 
 	 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
@@ -265,7 +274,8 @@ 
 			  viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
 			  vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,\
 			  vfwalu,vfwmul,vfsgnj,vfmerge,vired,viwred,vfredu,\
-			  vfredo,vfwredu,vfwredo")
+			  vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\
+			  vislide1down,vfslide1up,vfslide1down,vgather")
 	   (symbol_ref "riscv_vector::get_ta(operands[6])")
 
 	 (eq_attr "type" "vimuladd,viwmuladd,vfmuladd,vfwmuladd")
@@ -292,7 +302,8 @@ 
 	 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
 			  viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
 			  vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,\
-			  vfwalu,vfwmul,vfsgnj,vfcmp")
+			  vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\
+			  vislide1up,vislide1down,vfslide1up,vfslide1down,vgather")
 	   (symbol_ref "riscv_vector::get_ma(operands[7])")
 
 	 (eq_attr "type" "vimuladd,viwmuladd,vfmuladd,vfwmuladd")
@@ -323,7 +334,8 @@ 
 	 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
 			  viwalu,viwmul,vnshift,vimuladd,vaalu,vsmul,vsshift,\
 			  vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
-			  vfsgnj,vfcmp,vfmuladd")
+			  vfsgnj,vfcmp,vfmuladd,vslideup,vslidedown,vislide1up,\
+			  vislide1down,vfslide1up,vfslide1down,vgather")
 	   (symbol_ref "INTVAL (operands[8])")
 	 (eq_attr "type" "vstux,vstox")
 	   (symbol_ref "INTVAL (operands[5])")
@@ -331,7 +343,7 @@ 
 	 (eq_attr "type" "vimuladd,viwmuladd,vfwmuladd")
 	   (symbol_ref "INTVAL (operands[9])")
 
-	 (eq_attr "type" "vmsfs,vmidx")
+	 (eq_attr "type" "vmsfs,vmidx,vcompress")
 	   (symbol_ref "INTVAL (operands[6])")
 
 	 (eq_attr "type" "vmpop,vmffs")
@@ -4838,7 +4850,7 @@ 
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (commutative_float_binop:VF
 	    (vec_duplicate:VF
-	      (match_operand:<VEL> 4 "register_operand"  "  r,  r"))
+	      (match_operand:<VEL> 4 "register_operand"  "  f,  f"))
 	    (match_operand:VF 3 "register_operand"       " vr, vr"))
 	  (match_operand:VF 2 "vector_merge_operand"     "0vu,0vu")))]
   "TARGET_VECTOR"
@@ -4860,7 +4872,7 @@ 
 	  (non_commutative_float_binop:VF
 	    (match_operand:VF 3 "register_operand"       " vr, vr")
 	    (vec_duplicate:VF
-	      (match_operand:<VEL> 4 "register_operand"  "  r,  r")))
+	      (match_operand:<VEL> 4 "register_operand"  "  f,  f")))
 	  (match_operand:VF 2 "vector_merge_operand"     "0vu,0vu")))]
   "TARGET_VECTOR"
   "vf<insn>.vf\t%0,%3,%4%p1"
@@ -4880,7 +4892,7 @@ 
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (non_commutative_float_binop:VF
 	    (vec_duplicate:VF
-	      (match_operand:<VEL> 4 "register_operand"  "  r,  r"))
+	      (match_operand:<VEL> 4 "register_operand"  "  f,  f"))
 	    (match_operand:VF 3 "register_operand"       " vr, vr"))
 	  (match_operand:VF 2 "vector_merge_operand"     "0vu,0vu")))]
   "TARGET_VECTOR"
@@ -5748,7 +5760,7 @@ 
 	    (mult:VWEXTF
 	      (float_extend:VWEXTF
 	        (vec_duplicate:<V_DOUBLE_TRUNC>
-	          (match_operand:<VSUBEL> 3 "register_operand"       "    r")))
+	          (match_operand:<VSUBEL> 3 "register_operand"       "    f")))
 	      (float_extend:VWEXTF
 	        (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr"))))
 	  (match_operand:VWEXTF 5 "vector_merge_operand"             "  0vu")))]
@@ -5799,7 +5811,7 @@ 
 	      (mult:VWEXTF
 	        (float_extend:VWEXTF
 	          (vec_duplicate:<V_DOUBLE_TRUNC>
-	            (match_operand:<VSUBEL> 3 "register_operand"       "    r")))
+	            (match_operand:<VSUBEL> 3 "register_operand"       "    f")))
 	        (float_extend:VWEXTF
 	          (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr")))))
 	  (match_operand:VWEXTF 5 "vector_merge_operand"               "  0vu")))]
@@ -5904,7 +5916,7 @@ 
 	  (match_operator:<VM> 3 "signed_order_operator"
 	     [(match_operand:VF 4 "register_operand"          "   vr")
 	      (vec_duplicate:VF
-	        (match_operand:<VEL> 5 "register_operand"     "    r"))])
+	        (match_operand:<VEL> 5 "register_operand"     "    f"))])
 	  (match_operand:<VM> 2 "vector_merge_operand"        "  0vu")))]
   "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
   "vmf%B3.vf\t%0,%4,%5%p1"
@@ -5925,7 +5937,7 @@ 
 	  (match_operator:<VM> 3 "signed_order_operator"
 	     [(match_operand:VF 4 "register_operand"          "   vr")
 	      (vec_duplicate:VF
-	        (match_operand:<VEL> 5 "register_operand"     "    r"))])
+	        (match_operand:<VEL> 5 "register_operand"     "    f"))])
 	  (match_operand:<VM> 2 "vector_merge_operand"        "  0vu")))]
   "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
   "vmf%B3.vf\t%0,%4,%5%p1"
@@ -5963,7 +5975,7 @@ 
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (match_operator:<VM> 3 "equality_operator"
 	     [(vec_duplicate:VF
-	        (match_operand:<VEL> 5 "register_operand"     "    r"))
+	        (match_operand:<VEL> 5 "register_operand"     "    f"))
 	      (match_operand:VF 4 "register_operand"          "   vr")])
 	  (match_operand:<VM> 2 "vector_merge_operand"        "  0vu")))]
   "TARGET_VECTOR && known_le (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
@@ -5984,7 +5996,7 @@ 
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (match_operator:<VM> 3 "equality_operator"
 	     [(vec_duplicate:VF
-	        (match_operand:<VEL> 5 "register_operand"     "    r"))
+	        (match_operand:<VEL> 5 "register_operand"     "    f"))
 	      (match_operand:VF 4 "register_operand"          "   vr")])
 	  (match_operand:<VM> 2 "vector_merge_operand"        "  0vu")))]
   "TARGET_VECTOR && known_gt (GET_MODE_SIZE (<MODE>mode), BYTES_PER_RISCV_VECTOR)"
@@ -6577,3 +6589,203 @@ 
   "vfmv.f.s\t%0,%1"
   [(set_attr "type" "vfmovvf")
    (set_attr "mode" "<MODE>")])
+
+;; vslide instructions
+(define_insn "@pred_slide<ud><mode>"
+  [(set (match_operand:V 0 "register_operand"             "<ud_constraint>")
+	(unspec:V
+	  [(unspec:<VM>
+	     [(match_operand:<VM> 1 "vector_mask_operand" "     vm,    Wc1")
+	      (match_operand 5 "vector_length_operand"    "     rK,     rK")
+	      (match_operand 6 "const_int_operand"        "      i,      i")
+	      (match_operand 7 "const_int_operand"        "      i,      i")
+	      (match_operand 8 "const_int_operand"        "      i,      i")
+	      (reg:SI VL_REGNUM)
+	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	   (match_operand:V 2 "vector_merge_operand"      "    0vu,    0vu")
+	   (match_operand:V 3 "register_operand"          "     vr,     vr")
+	   (match_operand 4 "pmode_reg_or_uimm5_operand"  "     rK,     rK")] VSLIDES))]
+  "TARGET_VECTOR"
+  "vslide<ud>.v%o4\t%0,%3,%4%p1"
+  [(set_attr "type" "vslide<ud>")
+   (set_attr "mode" "<MODE>")])
+
+;; vslide1 instructions
+(define_insn "@pred_slide<ud><mode>"
+  [(set (match_operand:VI_QHS 0 "register_operand"        "<ud_constraint>")
+	(unspec:VI_QHS
+	  [(unspec:<VM>
+	     [(match_operand:<VM> 1 "vector_mask_operand" "     vm,    Wc1")
+	      (match_operand 5 "vector_length_operand"    "     rK,     rK")
+	      (match_operand 6 "const_int_operand"        "      i,      i")
+	      (match_operand 7 "const_int_operand"        "      i,      i")
+	      (match_operand 8 "const_int_operand"        "      i,      i")
+	      (reg:SI VL_REGNUM)
+	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	   (match_operand:VI_QHS 2 "vector_merge_operand" "    0vu,    0vu")
+	   (match_operand:VI_QHS 3 "register_operand"     "     vr,     vr")
+	   (match_operand:<VEL> 4 "reg_or_0_operand"      "     rJ,     rJ")] VSLIDES1))]
+  "TARGET_VECTOR"
+  "vslide<ud>.vx\t%0,%3,%z4%p1"
+  [(set_attr "type" "vislide<ud>")
+   (set_attr "mode" "<MODE>")])
+
+(define_expand "@pred_slide<ud><mode>"
+  [(set (match_operand:VI_D 0 "register_operand")
+	(unspec:VI_D
+	  [(unspec:<VM>
+	     [(match_operand:<VM> 1 "vector_mask_operand")
+	      (match_operand 5 "reg_or_int_operand")
+	      (match_operand 6 "const_int_operand")
+	      (match_operand 7 "const_int_operand")
+	      (match_operand 8 "const_int_operand")
+	      (reg:SI VL_REGNUM)
+	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	   (match_operand:VI_D 2 "vector_merge_operand")
+	   (match_operand:VI_D 3 "register_operand")
+	   (match_operand:<VEL> 4 "reg_or_int_operand")] VSLIDES1))]
+  "TARGET_VECTOR"
+{
+  if (riscv_vector::slide1_sew64_helper (<UNSPEC>, <MODE>mode,
+  			<VDEMOTE>mode, <VMDEMOTE>mode, operands))
+    DONE;
+})
+
+(define_insn "*pred_slide<ud><mode>"
+  [(set (match_operand:VI_D 0 "register_operand"          "<ud_constraint>")
+	(unspec:VI_D
+	  [(unspec:<VM>
+	     [(match_operand:<VM> 1 "vector_mask_operand" "     vm,    Wc1")
+	      (match_operand 5 "vector_length_operand"    "     rK,     rK")
+	      (match_operand 6 "const_int_operand"        "      i,      i")
+	      (match_operand 7 "const_int_operand"        "      i,      i")
+	      (match_operand 8 "const_int_operand"        "      i,      i")
+	      (reg:SI VL_REGNUM)
+	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	   (match_operand:VI_D 2 "vector_merge_operand"   "    0vu,    0vu")
+	   (match_operand:VI_D 3 "register_operand"       "     vr,     vr")
+	   (match_operand:<VEL> 4 "reg_or_0_operand"      "     rJ,     rJ")] VSLIDES1))]
+  "TARGET_VECTOR"
+  "vslide<ud>.vx\t%0,%3,%z4%p1"
+  [(set_attr "type" "vislide<ud>")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "*pred_slide<ud><mode>_extended"
+  [(set (match_operand:VI_D 0 "register_operand"          "<ud_constraint>")
+	(unspec:VI_D
+	  [(unspec:<VM>
+	     [(match_operand:<VM> 1 "vector_mask_operand" "     vm,    Wc1")
+	      (match_operand 5 "vector_length_operand"    "     rK,     rK")
+	      (match_operand 6 "const_int_operand"        "      i,      i")
+	      (match_operand 7 "const_int_operand"        "      i,      i")
+	      (match_operand 8 "const_int_operand"        "      i,      i")
+	      (reg:SI VL_REGNUM)
+	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	   (match_operand:VI_D 2 "vector_merge_operand"   "    0vu,    0vu")
+	   (match_operand:VI_D 3 "register_operand"       "     vr,     vr")
+	   (sign_extend:<VEL>
+	     (match_operand:<VSUBEL> 4 "reg_or_0_operand" "     rJ,     rJ"))] VSLIDES1))]
+  "TARGET_VECTOR"
+  "vslide<ud>.vx\t%0,%3,%z4%p1"
+  [(set_attr "type" "vislide<ud>")
+   (set_attr "mode" "<MODE>")])
+
+;; vfslide1 instructions
+(define_insn "@pred_slide<ud><mode>"
+  [(set (match_operand:VF 0 "register_operand"            "<ud_constraint>")
+	(unspec:VF
+	  [(unspec:<VM>
+	     [(match_operand:<VM> 1 "vector_mask_operand" "     vm,    Wc1")
+	      (match_operand 5 "vector_length_operand"    "     rK,     rK")
+	      (match_operand 6 "const_int_operand"        "      i,      i")
+	      (match_operand 7 "const_int_operand"        "      i,      i")
+	      (match_operand 8 "const_int_operand"        "      i,      i")
+	      (reg:SI VL_REGNUM)
+	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	   (match_operand:VF 2 "vector_merge_operand"     "    0vu,    0vu")
+	   (match_operand:VF 3 "register_operand"         "     vr,     vr")
+	   (match_operand:<VEL> 4 "register_operand"      "      f,      f")] VFSLIDES1))]
+  "TARGET_VECTOR"
+  "vfslide<ud>.vf\t%0,%3,%4%p1"
+  [(set_attr "type" "vfslide<ud>")
+   (set_attr "mode" "<MODE>")])
+
+;; vrgather
+(define_insn "@pred_gather<mode>"
+  [(set (match_operand:V 0 "register_operand"              "=&vr")
+	(if_then_else:V
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"  "vmWc1")
+	     (match_operand 5 "vector_length_operand"     "   rK")
+	     (match_operand 6 "const_int_operand"         "    i")
+	     (match_operand 7 "const_int_operand"         "    i")
+	     (match_operand 8 "const_int_operand"         "    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (unspec:V
+	    [(match_operand:V 3 "register_operand"        "   vr")
+	     (match_operand:<VINDEX> 4 "register_operand" "   vr")] UNSPEC_VRGATHER)
+	  (match_operand:V 2 "vector_merge_operand"       "  0vu")))]
+  "TARGET_VECTOR"
+  "vrgather.vv\t%0,%3,%4%p1"
+  [(set_attr "type" "vgather")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "@pred_gather<mode>_scalar"
+  [(set (match_operand:V 0 "register_operand"               "=&vr")
+	(if_then_else:V
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"   "vmWc1")
+	     (match_operand 5 "vector_length_operand"      "   rK")
+	     (match_operand 6 "const_int_operand"          "    i")
+	     (match_operand 7 "const_int_operand"          "    i")
+	     (match_operand 8 "const_int_operand"          "    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (unspec:V
+	    [(match_operand:V 3 "register_operand"         "   vr")
+	     (match_operand 4 "pmode_reg_or_uimm5_operand" "   rK")] UNSPEC_VRGATHER)
+	  (match_operand:V 2 "vector_merge_operand"        "  0vu")))]
+  "TARGET_VECTOR"
+  "vrgather.v%o4\t%0,%3,%4%p1"
+  [(set_attr "type" "vgather")
+   (set_attr "mode" "<MODE>")])
+
+;; vrgatherei16
+(define_insn "@pred_gatherei16<mode>"
+  [(set (match_operand:VEI16 0 "register_operand"              "=&vr")
+	(if_then_else:VEI16
+	  (unspec:<VM>
+	    [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1")
+	     (match_operand 5 "vector_length_operand"         "   rK")
+	     (match_operand 6 "const_int_operand"             "    i")
+	     (match_operand 7 "const_int_operand"             "    i")
+	     (match_operand 8 "const_int_operand"             "    i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	  (unspec:VEI16
+	    [(match_operand:VEI16 3 "register_operand"        "   vr")
+	     (match_operand:<VINDEXEI16> 4 "register_operand" "   vr")] UNSPEC_VRGATHEREI16)
+	  (match_operand:VEI16 2 "vector_merge_operand"       "  0vu")))]
+  "TARGET_VECTOR"
+  "vrgatherei16.vv\t%0,%3,%4%p1"
+  [(set_attr "type" "vgather")
+   (set_attr "mode" "<MODE>")])
+
+;; vcompress
+(define_insn "@pred_compress<mode>"
+  [(set (match_operand:V 0 "register_operand"            "=&vr")
+	(unspec:V
+	  [(unspec:<VM>
+	    [(match_operand:<VM> 3 "register_operand"    "  vm")
+	     (match_operand 4 "vector_length_operand"    "  rK")
+	     (match_operand 5 "const_int_operand"        "   i")
+	     (match_operand 6 "const_int_operand"        "   i")
+	     (reg:SI VL_REGNUM)
+	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+	   (match_operand:V 2 "register_operand"          "  vr")
+	   (match_operand:V 1 "vector_merge_operand"        " 0vu")] UNSPEC_VCOMPRESS))]
+  "TARGET_VECTOR"
+  "vcompress.vm\t%0,%2,%3"
+  [(set_attr "type" "vcompress")
+   (set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-167.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-167.c
new file mode 100644
index 00000000000..9095faf58ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-167.c
@@ -0,0 +1,143 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** f0:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, -16, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, -16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f1:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 15, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 15, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 16, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 0xAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 0xAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f4:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f5:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f6:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, x, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, x, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f7:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**  ...
+**	ret
+*/
+void f7 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 0, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 0, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-not {vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-168.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-168.c
new file mode 100644
index 00000000000..f671ffa3058
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-168.c
@@ -0,0 +1,143 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** f0:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, -16, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, -16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f1:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 15, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 15, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 16, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 0xAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 0xAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f4:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f5:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f6:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, x, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, x, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f7:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**  ...
+**	ret
+*/
+void f7 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 0, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 0, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-not {vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-169.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-169.c
new file mode 100644
index 00000000000..8585d552668
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-169.c
@@ -0,0 +1,163 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** f0:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, -16, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, -16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f1:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 15, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 15, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 16, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**  ...
+**	ret
+*/
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 0xAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 0xAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f4:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f5:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f6:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, x, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, x, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f7:
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**  ...
+**	ret
+*/
+void f7 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, 0, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1 (v3, 0, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-not {vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-170.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-170.c
new file mode 100644
index 00000000000..0596417b32c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-170.c
@@ -0,0 +1,163 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** f0:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f0 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, -16, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, -16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f1:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 15, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 15, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f2:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 16, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 16, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f3:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f3 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 0xAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 0xAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f4:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f4 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f5:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f5 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f6:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	ret
+*/
+void f6 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, x, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, x, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/*
+** f7:
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*zero
+**  ...
+**	ret
+*/
+void f7 (void * in, void *out, int64_t x, int n)
+{
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, 0, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1 (v3, 0, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-not {vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
new file mode 100644
index 00000000000..dae5eff42ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
@@ -0,0 +1,75 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** f1:
+**  ...
+**	vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au]
+**  ...
+**	vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vmerge\.vvm\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t m = __riscv_vlm_v_b64 (in, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, x, 4);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1_tu (v3, v3, x, 4);
+  vint64m1_t v5 = __riscv_vslide1down_vx_i64m1_tumu (m, v4, v4, x, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v5, 4);
+}
+
+/*
+** f2:
+**  ...
+**	vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au]
+**  ...
+**	vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vmerge\.vvm\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t m = __riscv_vlm_v_b64 (in, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, x, 4);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1_tu (v3, v3, x, 4);
+  vint64m1_t v5 = __riscv_vslide1up_vx_i64m1_tumu (m, v4, v4, x, 4);
+  __riscv_vse64_v_i64m1 (out + 2, v5, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c
new file mode 100644
index 00000000000..060c853a698
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c
@@ -0,0 +1,71 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** f1:
+**  ...
+**	vsetivli\tzero,\s*4,e32,m1,tu,m[au]
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vmerge\.vvm\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t m = __riscv_vlm_v_b64 (in, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, x, 2);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1_tu (v3, v3, x, 2);
+  vint64m1_t v5 = __riscv_vslide1down_vx_i64m1_tumu (m, v4, v4, x, 2);
+  __riscv_vse64_v_i64m1 (out + 2, v5, 4);
+}
+
+/*
+** f2:
+**  ...
+**	vsetivli\tzero,\s*4,e32,m1,tu,m[au]
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vmerge\.vvm\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int n)
+{
+  vbool64_t m = __riscv_vlm_v_b64 (in, 4);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, x, 2);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1_tu (v3, v3, x, 2);
+  vint64m1_t v5 = __riscv_vslide1up_vx_i64m1_tumu (m, v4, v4, x, 2);
+  __riscv_vse64_v_i64m1 (out + 2, v5, 4);
+}
+
+/* { dg-final { scan-assembler-times {vmv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
new file mode 100644
index 00000000000..0d5a2603856
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
@@ -0,0 +1,75 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** f1:
+**  ...
+**	vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au]
+**  ...
+**	vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vmerge\.vvm\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int vl)
+{
+  vbool64_t m = __riscv_vlm_v_b64 (in, vl);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, vl);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, vl);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, x, vl);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1_tu (v3, v3, x, vl);
+  vint64m1_t v5 = __riscv_vslide1down_vx_i64m1_tumu (m, v4, v4, x, vl);
+  __riscv_vse64_v_i64m1 (out + 2, v5, vl);
+}
+
+/*
+** f2:
+**  ...
+**	vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au]
+**  ...
+**	vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vmerge\.vvm\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int vl)
+{
+  vbool64_t m = __riscv_vlm_v_b64 (in, vl);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, vl);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, vl);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, x, vl);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1_tu (v3, v3, x, vl);
+  vint64m1_t v5 = __riscv_vslide1up_vx_i64m1_tumu (m, v4, v4, x, vl);
+  __riscv_vse64_v_i64m1 (out + 2, v5, vl);
+}
+
+/* { dg-final { scan-assembler-times {vmv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c
new file mode 100644
index 00000000000..f2e5d40ceb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c
@@ -0,0 +1,71 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+** f1:
+**  ...
+**	vsetvli\t[a-x0-9]+,\s*zero,e32,m1,tu,m[au]
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vmerge\.vvm\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+**  ...
+**	ret
+*/
+void f1 (void * in, void *out, int64_t x, int vl)
+{
+  vbool64_t m = __riscv_vlm_v_b64 (in, vl);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, vl);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, vl);
+  vint64m1_t v3 = __riscv_vslide1down_vx_i64m1 (v2, x, 0x80000000);
+  vint64m1_t v4 = __riscv_vslide1down_vx_i64m1_tu (v3, v3, x, 0x80000000);
+  vint64m1_t v5 = __riscv_vslide1down_vx_i64m1_tumu (m, v4, v4, x, 0x80000000);
+  __riscv_vse64_v_i64m1 (out + 2, v5, vl);
+}
+
+/*
+** f2:
+**  ...
+**	vsetvli\t[a-x0-9]+,\s*zero,e32,m1,tu,m[au]
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
+**  ...
+**	vmerge\.vvm\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+**  ...
+**	ret
+*/
+void f2 (void * in, void *out, int64_t x, int vl)
+{
+  vbool64_t m = __riscv_vlm_v_b64 (in, vl);
+  vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, vl);
+  vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, vl);
+  vint64m1_t v3 = __riscv_vslide1up_vx_i64m1 (v2, x, 0x80000000);
+  vint64m1_t v4 = __riscv_vslide1up_vx_i64m1_tu (v3, v3, x, 0x80000000);
+  vint64m1_t v5 = __riscv_vslide1up_vx_i64m1_tumu (m, v4, v4, x, 0x80000000);
+  __riscv_vse64_v_i64m1 (out + 2, v5, vl);
+}
+
+/* { dg-final { scan-assembler-times {vmv} 3 } } */