diff mbox series

RISC-V: Add vwcvt C++ api test

Message ID 20230207064913.45829-1-juzhe.zhong@rivai.ai
State Committed
Commit 98767d253c1c05258113d71829755bcae2dc15d3
Headers
Series RISC-V: Add vwcvt C++ api test |

Commit Message

钟居哲 Feb. 7, 2023, 6:49 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vwcvt_x-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x-3.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvt_x_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x-3.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vwcvtu_x_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vwcvt_x-1.C     | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x-2.C     | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x-3.C     | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x_mu-1.C  | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x_mu-2.C  | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x_mu-3.C  | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x_tu-1.C  | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x_tu-2.C  | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x_tu-3.C  | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x_tum-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x_tum-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvt_x_tum-3.C | 111 +++++++++
 .../riscv/rvv/base/vwcvt_x_tumu-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwcvt_x_tumu-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwcvt_x_tumu-3.C           | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvtu_x-1.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwcvtu_x-2.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwcvtu_x-3.C    | 216 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vwcvtu_x_mu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvtu_x_mu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvtu_x_mu-3.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvtu_x_tu-1.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvtu_x_tu-2.C | 111 +++++++++
 .../g++.target/riscv/rvv/base/vwcvtu_x_tu-3.C | 111 +++++++++
 .../riscv/rvv/base/vwcvtu_x_tum-1.C           | 111 +++++++++
 .../riscv/rvv/base/vwcvtu_x_tum-2.C           | 111 +++++++++
 .../riscv/rvv/base/vwcvtu_x_tum-3.C           | 111 +++++++++
 .../riscv/rvv/base/vwcvtu_x_tumu-1.C          | 111 +++++++++
 .../riscv/rvv/base/vwcvtu_x_tumu-2.C          | 111 +++++++++
 .../riscv/rvv/base/vwcvtu_x_tumu-3.C          | 111 +++++++++
 30 files changed, 3960 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-1.C
new file mode 100644
index 00000000000..4898fb360a3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x(vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x(vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x(vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x(vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x(vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x(vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x(vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x(vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x(vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x(vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x(vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x(vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,vl);
+}
+
+
+vint16mf4_t test___riscv_vwcvt_x(vbool64_t mask,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x(vbool32_t mask,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x(vbool16_t mask,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x(vbool8_t mask,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x(vbool4_t mask,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x(vbool2_t mask,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x(vbool64_t mask,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x(vbool32_t mask,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x(vbool16_t mask,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x(vbool8_t mask,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x(vbool4_t mask,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x(vbool64_t mask,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x(vbool32_t mask,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x(vbool16_t mask,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x(vbool8_t mask,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-2.C
new file mode 100644
index 00000000000..0f7cbed555a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x(vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x(vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x(vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x(vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x(vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x(vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x(vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x(vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x(vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x(vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x(vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x(vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,31);
+}
+
+
+vint16mf4_t test___riscv_vwcvt_x(vbool64_t mask,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x(vbool32_t mask,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x(vbool16_t mask,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x(vbool8_t mask,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x(vbool4_t mask,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x(vbool2_t mask,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x(vbool64_t mask,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x(vbool32_t mask,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x(vbool16_t mask,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x(vbool8_t mask,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x(vbool4_t mask,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x(vbool64_t mask,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x(vbool32_t mask,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x(vbool16_t mask,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x(vbool8_t mask,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-3.C
new file mode 100644
index 00000000000..f3a3b49f48c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x(vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x(vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x(vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x(vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x(vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x(vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x(vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x(vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x(vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x(vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x(vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x(vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x(vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x(vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x(vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(src,32);
+}
+
+
+vint16mf4_t test___riscv_vwcvt_x(vbool64_t mask,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x(vbool32_t mask,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x(vbool16_t mask,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x(vbool8_t mask,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x(vbool4_t mask,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x(vbool2_t mask,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x(vbool64_t mask,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x(vbool32_t mask,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x(vbool16_t mask,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x(vbool8_t mask,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x(vbool4_t mask,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x(vbool64_t mask,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x(vbool32_t mask,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x(vbool16_t mask,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x(vbool8_t mask,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x(mask,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-1.C
new file mode 100644
index 00000000000..9d37ff264c3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-2.C
new file mode 100644
index 00000000000..d74dbf61071
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-3.C
new file mode 100644
index 00000000000..ae138cc6f77
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_mu(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-1.C
new file mode 100644
index 00000000000..75624c488e1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_tu(vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_tu(vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_tu(vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_tu(vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_tu(vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_tu(vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_tu(vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_tu(vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_tu(vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_tu(vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_tu(vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_tu(vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_tu(vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_tu(vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_tu(vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-2.C
new file mode 100644
index 00000000000..cd155b74349
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_tu(vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_tu(vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_tu(vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_tu(vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_tu(vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_tu(vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_tu(vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_tu(vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_tu(vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_tu(vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_tu(vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_tu(vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_tu(vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_tu(vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_tu(vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-3.C
new file mode 100644
index 00000000000..163a7536e94
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_tu(vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_tu(vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_tu(vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_tu(vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_tu(vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_tu(vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_tu(vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_tu(vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_tu(vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_tu(vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_tu(vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_tu(vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_tu(vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_tu(vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_tu(vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tu(merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-1.C
new file mode 100644
index 00000000000..f296905163a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-2.C
new file mode 100644
index 00000000000..1db6f4f51b2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-3.C
new file mode 100644
index 00000000000..9a24b9230b2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tum(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-1.C
new file mode 100644
index 00000000000..d413b38b039
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-2.C
new file mode 100644
index 00000000000..05db04b499b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-3.C
new file mode 100644
index 00000000000..d51dcef3cb0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvt_x_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint16mf4_t test___riscv_vwcvt_x_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16mf2_t test___riscv_vwcvt_x_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16m1_t test___riscv_vwcvt_x_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16m2_t test___riscv_vwcvt_x_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16m4_t test___riscv_vwcvt_x_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint16m8_t test___riscv_vwcvt_x_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint32mf2_t test___riscv_vwcvt_x_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint32m1_t test___riscv_vwcvt_x_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint32m2_t test___riscv_vwcvt_x_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint32m4_t test___riscv_vwcvt_x_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint32m8_t test___riscv_vwcvt_x_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint64m1_t test___riscv_vwcvt_x_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint64m2_t test___riscv_vwcvt_x_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint64m4_t test___riscv_vwcvt_x_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+vint64m8_t test___riscv_vwcvt_x_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvt_x_tumu(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvt\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-1.C
new file mode 100644
index 00000000000..0f4b7c5029c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-1.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x(vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x(vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x(vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x(vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x(vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x(vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,vl);
+}
+
+
+vuint16mf4_t test___riscv_vwcvtu_x(vbool64_t mask,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x(vbool32_t mask,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x(vbool16_t mask,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x(vbool8_t mask,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x(vbool4_t mask,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x(vbool2_t mask,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x(vbool64_t mask,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x(vbool32_t mask,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x(vbool16_t mask,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x(vbool8_t mask,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x(vbool4_t mask,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x(vbool64_t mask,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x(vbool32_t mask,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x(vbool16_t mask,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x(vbool8_t mask,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-2.C
new file mode 100644
index 00000000000..3c9bca1a196
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-2.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x(vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x(vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x(vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x(vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x(vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x(vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,31);
+}
+
+
+vuint16mf4_t test___riscv_vwcvtu_x(vbool64_t mask,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x(vbool32_t mask,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x(vbool16_t mask,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x(vbool8_t mask,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x(vbool4_t mask,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x(vbool2_t mask,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x(vbool64_t mask,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x(vbool32_t mask,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x(vbool16_t mask,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x(vbool8_t mask,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x(vbool4_t mask,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x(vbool64_t mask,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x(vbool32_t mask,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x(vbool16_t mask,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x(vbool8_t mask,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-3.C
new file mode 100644
index 00000000000..bf602d064f6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x-3.C
@@ -0,0 +1,216 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x(vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x(vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x(vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x(vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x(vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x(vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x(vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x(vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x(vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x(vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x(vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x(vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x(vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x(vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x(vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(src,32);
+}
+
+
+vuint16mf4_t test___riscv_vwcvtu_x(vbool64_t mask,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x(vbool32_t mask,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x(vbool16_t mask,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x(vbool8_t mask,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x(vbool4_t mask,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x(vbool2_t mask,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x(vbool64_t mask,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x(vbool32_t mask,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x(vbool16_t mask,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x(vbool8_t mask,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x(vbool4_t mask,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x(vbool64_t mask,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x(vbool32_t mask,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x(vbool16_t mask,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x(vbool8_t mask,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x(mask,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-1.C
new file mode 100644
index 00000000000..e4654827eb5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-2.C
new file mode 100644
index 00000000000..d3eaf9ad700
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-3.C
new file mode 100644
index 00000000000..42bbb9143fc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_mu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_mu(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-1.C
new file mode 100644
index 00000000000..da4d01def66
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_tu(vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_tu(vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_tu(vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_tu(vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_tu(vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_tu(vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_tu(vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_tu(vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_tu(vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_tu(vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_tu(vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_tu(vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_tu(vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_tu(vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_tu(vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-2.C
new file mode 100644
index 00000000000..d48589deb73
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_tu(vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_tu(vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_tu(vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_tu(vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_tu(vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_tu(vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_tu(vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_tu(vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_tu(vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_tu(vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_tu(vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_tu(vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_tu(vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_tu(vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_tu(vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-3.C
new file mode 100644
index 00000000000..4c1aa07248c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_tu(vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_tu(vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_tu(vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_tu(vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_tu(vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_tu(vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_tu(vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_tu(vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_tu(vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_tu(vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_tu(vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_tu(vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_tu(vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_tu(vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_tu(vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tu(merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-1.C
new file mode 100644
index 00000000000..48c7cba96a9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-2.C
new file mode 100644
index 00000000000..8f446af835b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-3.C
new file mode 100644
index 00000000000..c1bce66c8ef
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tum-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tum(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-1.C
new file mode 100644
index 00000000000..3ac26f97aba
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-1.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-2.C
new file mode 100644
index 00000000000..352bc10fbce
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-2.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-3.C
new file mode 100644
index 00000000000..c59aff56261
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwcvtu_x_tumu-3.C
@@ -0,0 +1,111 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint16mf4_t test___riscv_vwcvtu_x_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16mf2_t test___riscv_vwcvtu_x_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16m1_t test___riscv_vwcvtu_x_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16m2_t test___riscv_vwcvtu_x_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16m4_t test___riscv_vwcvtu_x_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint16m8_t test___riscv_vwcvtu_x_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint32mf2_t test___riscv_vwcvtu_x_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint32m1_t test___riscv_vwcvtu_x_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint32m2_t test___riscv_vwcvtu_x_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint32m4_t test___riscv_vwcvtu_x_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint32m8_t test___riscv_vwcvtu_x_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint64m1_t test___riscv_vwcvtu_x_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint64m2_t test___riscv_vwcvtu_x_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint64m4_t test___riscv_vwcvtu_x_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+vuint64m8_t test___riscv_vwcvtu_x_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t src,size_t vl)
+{
+    return __riscv_vwcvtu_x_tumu(mask,merge,src,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwcvtu\.x\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */