diff mbox series

[v2,1/1] Add unit-stride load store intrinsics

Message ID 20220531103356.332482-2-juzhe.zhong@rivai.ai
State Committed
Headers
Series RISC-V: Add RVV (RISC-V 'V' Extension) support |

Commit Message

juzhe.zhong@rivai.ai May 31, 2022, 10:33 a.m. UTC 
  From: zhongjuzhe <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins-functions.cc (loadstore::assemble_name): New function.
        (loadstore::get_argument_types): New function.
        (vle::call_properties): New function.
        (vle::get_return_type): New function.
        (vle::can_be_overloaded_p): New function.
        (vle::expand): New function.
        (vse::call_properties): New function.
        (vse::can_be_overloaded_p): New function.
        (vse::expand): New function.
        * config/riscv/riscv-vector-builtins-functions.def (vle): New macro define.
        (vse): New macro define.
        * config/riscv/riscv-vector-builtins-functions.h (class loadstore): New class.
        (class vle): New class.
        (class vse): New class.
        * config/riscv/riscv-vector-builtins.cc (init_def_variables): New local constant declare.

---
 .../riscv/riscv-vector-builtins-functions.cc  | 80 +++++++++++++++++++
 .../riscv/riscv-vector-builtins-functions.def |  7 ++
 .../riscv/riscv-vector-builtins-functions.h   | 42 ++++++++++
 gcc/config/riscv/riscv-vector-builtins.cc     | 14 ++++
 4 files changed, 143 insertions(+)
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.cc b/gcc/config/riscv/riscv-vector-builtins-functions.cc
index a25f167f40e..fa39eedcd86 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.cc
@@ -1510,6 +1510,86 @@  vundefined::expand (const function_instance &, tree, rtx target) const
   return target;
 }
 
+/* A function implementation for loadstore functions.  */
+char *
+loadstore::assemble_name (function_instance &instance)
+{
+  machine_mode mode = instance.get_arg_pattern ().arg_list[0];
+  bool unsigned_p = instance.get_data_type_list ()[0] == DT_unsigned;
+  int sew = GET_MODE_BITSIZE (GET_MODE_INNER (mode));
+  char name[8];
+  snprintf (name, 8, "%s%d", instance.get_base_name (), sew);
+  const char *op = get_operation_str (instance.get_operation ());
+  const char *dt = mode2data_type_str (mode, unsigned_p, false);
+  const char *pred = get_pred_str (instance.get_pred ());
+  snprintf (instance.function_name, NAME_MAXLEN, "%s%s%s%s", name, op, dt, pred);
+  if (this->can_be_overloaded_p (instance))
+    {
+      append_name (name);
+      append_name (get_pred_str (instance.get_pred (), true));
+      return finish_name ();
+    }
+  return nullptr;
+}
+
+void
+loadstore::get_argument_types (const function_instance &instance,
+                               vec<tree> &argument_types) const
+{
+  for (unsigned int i = 1; i < instance.get_arg_pattern ().arg_len; i++)
+    argument_types.quick_push (get_dt_t_with_index (instance, i));
+}
+
+/* A function implementation for vle functions.  */
+unsigned int
+vle::call_properties () const
+{
+  return CP_READ_MEMORY;
+}
+
+tree
+vle::get_return_type (const function_instance &instance) const
+{
+  return get_dt_t_with_index (instance, 0);
+}
+
+bool
+vle::can_be_overloaded_p (const function_instance &instance) const
+{
+  return instance.get_pred () == PRED_m || instance.get_pred () == PRED_tu ||
+         instance.get_pred () == PRED_tamu ||
+         instance.get_pred () == PRED_tuma || instance.get_pred () == PRED_tumu;
+}
+
+rtx
+vle::expand (const function_instance &instance, tree exp, rtx target) const
+{
+  machine_mode mode = TYPE_MODE (TREE_TYPE (exp));
+  enum insn_code icode = code_for_vle (mode);
+  return expand_builtin_insn (icode, exp, target, instance);
+}
+
+/* A function implementation for vse functions.  */
+unsigned int
+vse::call_properties () const
+{
+  return CP_WRITE_MEMORY;
+}
+
+bool
+vse::can_be_overloaded_p (const function_instance &) const
+{
+  return true;
+}
+
+rtx
+vse::expand (const function_instance &instance, tree exp, rtx target) const
+{
+  machine_mode mode = instance.get_arg_pattern ().arg_list[0];
+  enum insn_code icode = code_for_vse (mode);
+  return expand_builtin_insn (icode, exp, target, instance);
+}
+
 } // end namespace riscv_vector
 
 using namespace riscv_vector;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 86130e02381..deb32ccd031 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -56,6 +56,13 @@  DEF_RVV_FUNCTION(vlmul_trunc, vlmul_trunc, (2, VITER(VLMULTRUNC, signed), VITER(
 DEF_RVV_FUNCTION(vundefined, vundefined, (1, VITER(VI, signed)), PAT_none, PRED_none, OP_none)
 DEF_RVV_FUNCTION(vundefined, vundefined, (1, VITER(VI, unsigned)), PAT_none, PRED_none, OP_none)
 DEF_RVV_FUNCTION(vundefined, vundefined, (1, VITER(VF, signed)), PAT_none, PRED_none, OP_none)
+/* 7. Vector Loads and Stores. */
+DEF_RVV_FUNCTION(vle, vle, (2, VITER(VI, signed), VATTR(0, VSUB, c_ptr)), pat_mask_tail, pred_all, OP_v)
+DEF_RVV_FUNCTION(vle, vle, (2, VITER(VI, unsigned), VATTR(0, VSUB, c_uptr)), pat_mask_tail, pred_all, OP_v)
+DEF_RVV_FUNCTION(vle, vle, (2, VITER(VF, signed), VATTR(0, VSUB, c_ptr)), pat_mask_tail, pred_all, OP_v)
+DEF_RVV_FUNCTION(vse, vse, (3, VITER(VI, signed), VATTR(0, VSUB, ptr), VATTR(0, VI, signed)), pat_mask_ignore_policy, pred_mask2, OP_v)
+DEF_RVV_FUNCTION(vse, vse, (3, VITER(VI, unsigned), VATTR(0, VSUB, uptr), VATTR(0, VI, unsigned)), pat_mask_ignore_policy, pred_mask2, OP_v)
+DEF_RVV_FUNCTION(vse, vse, (3, VITER(VF, signed), VATTR(0, VSUB, ptr), VATTR(0, VF, signed)), pat_mask_ignore_policy, pred_mask2, OP_v)
 #undef REQUIRED_EXTENSIONS
 #undef DEF_RVV_FUNCTION
 #undef VITER
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.h b/gcc/config/riscv/riscv-vector-builtins-functions.h
index 85e4af5f079..c9e1b2a34ca 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.h
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.h
@@ -584,6 +584,48 @@  public:
   virtual rtx expand (const function_instance &, tree, rtx) const override;
 };
 
+/* A function_base for loadstore functions.  */
+class loadstore : public function_builder
+{
+public:
+  // use the same construction function as the function_builder
+  using function_builder::function_builder;
+  
+  virtual char * assemble_name (function_instance &) override;
+
+  virtual void get_argument_types (const function_instance &, vec<tree> &) const override;
+};
+
+/* A function_base for vle functions.  */
+class vle : public loadstore
+{
+public:
+  // use the same construction function as the loadstore
+  using loadstore::loadstore;
+  
+  virtual unsigned int call_properties () const override;
+
+  virtual tree get_return_type (const function_instance &) const override;
+  
+  virtual bool can_be_overloaded_p (const function_instance &) const override;
+
+  virtual rtx expand (const function_instance &, tree, rtx) const override;
+};
+
+/* A function_base for vse functions.  */
+class vse : public loadstore
+{
+public:
+  // use the same construction function as the loadstore
+  using loadstore::loadstore;
+
+  virtual unsigned int call_properties () const override;
+  
+  virtual bool can_be_overloaded_p (const function_instance &) const override;
+
+  virtual rtx expand (const function_instance &, tree, rtx) const override;
+};
+
 } // namespace riscv_vector
 
 #endif // end GCC_RISCV_VECTOR_BUILTINS_FUNCTIONS_H
\ No newline at end of file
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index ef734572add..ee86d5a18c7 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -684,6 +684,20 @@  static void
 init_def_variables ()
 {
 
+/* define local help variables */
+uint64_t pred_all = PRED_void | PRED_ta | PRED_tu | PRED_m | PRED_tama | PRED_tamu | PRED_tuma | PRED_tumu;
+uint64_t pred_tail = PRED_void | PRED_ta | PRED_tu;
+uint64_t pred_mask = PRED_void | PRED_m | PRED_ma | PRED_mu;
+uint64_t pred_mask2 = PRED_void | PRED_m;
+uint64_t pred_reduce = PRED_void | PRED_ta | PRED_tu | PRED_m | PRED_tam | PRED_tum;
+
+uint64_t pat_mask_tail = PAT_mask | PAT_tail;
+uint64_t pat_mask_tail_dest = PAT_mask | PAT_tail | PAT_dest;
+uint64_t pat_tail_void_dest = PAT_tail | PAT_void_dest;
+uint64_t pat_void_dest_ignore_mp = PAT_mask | PAT_tail | PAT_void_dest | PAT_ignore_mask_policy;
+uint64_t pat_mask_ignore_tp = PAT_mask | PAT_ignore_tail_policy;
+uint64_t pat_mask_ignore_policy = PAT_mask | PAT_ignore_policy;
+
 /* define vector arg mode category */
 #define VVAR(NAME) vector_mode_attr_list_list[vector_mode_attr_##NAME]
 #define VITER(NAME, SIGN) riscv_vector::vector_arg_attr_info{-1, DT_##SIGN, &VVAR(NAME)}