| Message ID | 20220315091013.1036-1-shihua@iscas.ac.cn |
|---|---|
| State | Deferred, archived |
| Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C9227385DC00 for <patchwork@sourceware.org>; Tue, 15 Mar 2022 09:10:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id 9FA6E3858021 for <gcc-patches@gcc.gnu.org>; Tue, 15 Mar 2022 09:10:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9FA6E3858021 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [58.213.0.226]) by APP-05 (Coremail) with SMTP id zQCowABnbtoEWDBi7eeIAw--.12743S2; Tue, 15 Mar 2022 17:10:30 +0800 (CST) From: shihua@iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Implement ZTSO extension. Date: Tue, 15 Mar 2022 17:10:13 +0800 Message-Id: <20220315091013.1036-1-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: zQCowABnbtoEWDBi7eeIAw--.12743S2 X-Coremail-Antispam: 1UD129KBjvJXoW7AF17GFW3Wryruw4UKF15urg_yoW5JFy5pF 45G3yYy34rAFsagw4xtr48W3y5Jwnagw1rAr1kCw17AayDXrW8AFn0gw1I9r4kXFWUZrnF ka4FkrWYya1UA37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkv14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwAKzVCY07xG64k0F24l 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r 4UMIIF0xvE42xK8VAvwI8IcIk0rVWrZr1j6s0DMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUSiihUUUUU= X-Originating-IP: [58.213.0.226] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCQoGEV02bAGNiwAAsU X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Cc: cmuellner@ventanamicro.com, andrew@sifive.com, kito.cheng@sifive.com, LiaoShihua <shihua@iscas.ac.cn> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
| Series |
RISC-V: Implement ZTSO extension.
|
|
Commit Message
Liao Shihua
March 15, 2022, 9:10 a.m. UTC
From: LiaoShihua <shihua@iscas.ac.cn>
ZTSO is the extension of tatol store order model.
This extension adds no new instructions to the ISA, and you can use it with arch "ztso".
If you use it, TSO flag will be generate in the ELF header.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: define new arch.
* config/riscv/riscv-opts.h (MASK_ZTSO): Ditto.
(TARGET_ZTSO):Ditto.
* config/riscv/riscv.opt:Ditto.
---
gcc/common/config/riscv/riscv-common.cc | 4 +++-
gcc/config/riscv/riscv-opts.h | 3 +++
gcc/config/riscv/riscv.opt | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
Comments
Hi Shi-Hua: Thanks, this patch is LGTM, but I would defer that until stage 1, because the binutils part isn't merget yet. On Tue, Mar 15, 2022 at 5:10 PM <shihua@iscas.ac.cn> wrote: > > From: LiaoShihua <shihua@iscas.ac.cn> > > ZTSO is the extension of tatol store order model. > This extension adds no new instructions to the ISA, and you can use it with arch "ztso". > If you use it, TSO flag will be generate in the ELF header. > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: define new arch. > * config/riscv/riscv-opts.h (MASK_ZTSO): Ditto. > (TARGET_ZTSO):Ditto. > * config/riscv/riscv.opt:Ditto. > > --- > gcc/common/config/riscv/riscv-common.cc | 4 +++- > gcc/config/riscv/riscv-opts.h | 3 +++ > gcc/config/riscv/riscv.opt | 3 +++ > 3 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc > index a904893b9ed..f4730b991d7 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -185,6 +185,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = > {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, > {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, > > + {"ztso", ISA_SPEC_CLASS_NONE, 0, 1}, > + > /* Terminate the list. */ > {NULL, ISA_SPEC_CLASS_NONE, 0, 0} > }; > @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = > {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, > {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, > > - > + {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, > {NULL, NULL, 0} > }; > > diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h > index 929e4e3a7c5..9cb5f2a550a 100644 > --- a/gcc/config/riscv/riscv-opts.h > +++ b/gcc/config/riscv/riscv-opts.h > @@ -136,4 +136,7 @@ enum stack_protector_guard { > #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) > #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) > > +#define MASK_ZTSO (1 << 0) > +#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0) > + > #endif /* ! GCC_RISCV_OPTS_H */ > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index 9fffc08220d..6128bfa31dc 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -209,6 +209,9 @@ int riscv_vector_eew_flags > TargetVariable > int riscv_zvl_flags > > +TargetVariable > +int riscv_ztso_subext > + > Enum > Name(isa_spec_class) Type(enum riscv_isa_spec_class) > Supported ISA specs (for use with the -misa-spec= option): > -- > 2.31.1.windows.1 >
On Thu, 17 Mar 2022 23:52:04 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > Hi Shi-Hua: > > Thanks, this patch is LGTM, but I would defer that until stage 1, > because the binutils part isn't merget yet. IMO we should at least have a __riscv_ztso define, and ideally have the relevent builtins ported (atomics, fences, etc) as well. Otherwise this is really just setting a bit that makes binaries incompatible without providing any real benefit. That'll also let us work through how these mappings should be implemented, so we don't end up with issues like we did with WMO. > > On Tue, Mar 15, 2022 at 5:10 PM <shihua@iscas.ac.cn> wrote: >> >> From: LiaoShihua <shihua@iscas.ac.cn> >> >> ZTSO is the extension of tatol store order model. >> This extension adds no new instructions to the ISA, and you can use it with arch "ztso". >> If you use it, TSO flag will be generate in the ELF header. >> >> gcc/ChangeLog: >> >> * common/config/riscv/riscv-common.cc: define new arch. >> * config/riscv/riscv-opts.h (MASK_ZTSO): Ditto. >> (TARGET_ZTSO):Ditto. >> * config/riscv/riscv.opt:Ditto. >> >> --- >> gcc/common/config/riscv/riscv-common.cc | 4 +++- >> gcc/config/riscv/riscv-opts.h | 3 +++ >> gcc/config/riscv/riscv.opt | 3 +++ >> 3 files changed, 9 insertions(+), 1 deletion(-) >> >> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc >> index a904893b9ed..f4730b991d7 100644 >> --- a/gcc/common/config/riscv/riscv-common.cc >> +++ b/gcc/common/config/riscv/riscv-common.cc >> @@ -185,6 +185,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = >> {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, >> {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, >> >> + {"ztso", ISA_SPEC_CLASS_NONE, 0, 1}, >> + >> /* Terminate the list. */ >> {NULL, ISA_SPEC_CLASS_NONE, 0, 0} >> }; >> @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = >> {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, >> {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, >> >> - >> + {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, >> {NULL, NULL, 0} >> }; >> >> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h >> index 929e4e3a7c5..9cb5f2a550a 100644 >> --- a/gcc/config/riscv/riscv-opts.h >> +++ b/gcc/config/riscv/riscv-opts.h >> @@ -136,4 +136,7 @@ enum stack_protector_guard { >> #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) >> #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) >> >> +#define MASK_ZTSO (1 << 0) >> +#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0) >> + >> #endif /* ! GCC_RISCV_OPTS_H */ >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt >> index 9fffc08220d..6128bfa31dc 100644 >> --- a/gcc/config/riscv/riscv.opt >> +++ b/gcc/config/riscv/riscv.opt >> @@ -209,6 +209,9 @@ int riscv_vector_eew_flags >> TargetVariable >> int riscv_zvl_flags >> >> +TargetVariable >> +int riscv_ztso_subext >> + >> Enum >> Name(isa_spec_class) Type(enum riscv_isa_spec_class) >> Supported ISA specs (for use with the -misa-spec= option): >> -- >> 2.31.1.windows.1 >>
Hi Palmer: I guess the problem is binutils isn't included and it's too close to the GCC release, and binutils will report errors if it has any unsupported extensions. Most distro will use GCC 12 + binutils 2.38 or GCC 11 + binutils 2.38, so either combination doesn't work for march string with ztso. So that's why I am not intending to include that at this moment, but maybe we could include that first and it'll work once binutils 2.39 released, then we can have GCC 12 + binutils 2.39 in the next few months. Anyway, I think I am fine with that, and I'll ping Nelson for the binutils part. On Tue, Mar 22, 2022 at 9:13 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > On Thu, 17 Mar 2022 23:52:04 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > > Hi Shi-Hua: > > > > Thanks, this patch is LGTM, but I would defer that until stage 1, > > because the binutils part isn't merget yet. > > IMO we should at least have a __riscv_ztso define, and ideally have the > relevent builtins ported (atomics, fences, etc) as well. Otherwise this > is really just setting a bit that makes binaries incompatible without > providing any real benefit. That'll also let us work through how these > mappings should be implemented, so we don't end up with issues like we > did with WMO. > > > > > On Tue, Mar 15, 2022 at 5:10 PM <shihua@iscas.ac.cn> wrote: > >> > >> From: LiaoShihua <shihua@iscas.ac.cn> > >> > >> ZTSO is the extension of tatol store order model. > >> This extension adds no new instructions to the ISA, and you can > use it with arch "ztso". > >> If you use it, TSO flag will be generate in the ELF header. > >> > >> gcc/ChangeLog: > >> > >> * common/config/riscv/riscv-common.cc: define new arch. > >> * config/riscv/riscv-opts.h (MASK_ZTSO): Ditto. > >> (TARGET_ZTSO):Ditto. > >> * config/riscv/riscv.opt:Ditto. > >> > >> --- > >> gcc/common/config/riscv/riscv-common.cc | 4 +++- > >> gcc/config/riscv/riscv-opts.h | 3 +++ > >> gcc/config/riscv/riscv.opt | 3 +++ > >> 3 files changed, 9 insertions(+), 1 deletion(-) > >> > >> diff --git a/gcc/common/config/riscv/riscv-common.cc > b/gcc/common/config/riscv/riscv-common.cc > >> index a904893b9ed..f4730b991d7 100644 > >> --- a/gcc/common/config/riscv/riscv-common.cc > >> +++ b/gcc/common/config/riscv/riscv-common.cc > >> @@ -185,6 +185,8 @@ static const struct riscv_ext_version > riscv_ext_version_table[] = > >> {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, > >> {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, > >> > >> + {"ztso", ISA_SPEC_CLASS_NONE, 0, 1}, > >> + > >> /* Terminate the list. */ > >> {NULL, ISA_SPEC_CLASS_NONE, 0, 0} > >> }; > >> @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t > riscv_ext_flag_table[] = > >> {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, > >> {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, > >> > >> - > >> + {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, > >> {NULL, NULL, 0} > >> }; > >> > >> diff --git a/gcc/config/riscv/riscv-opts.h > b/gcc/config/riscv/riscv-opts.h > >> index 929e4e3a7c5..9cb5f2a550a 100644 > >> --- a/gcc/config/riscv/riscv-opts.h > >> +++ b/gcc/config/riscv/riscv-opts.h > >> @@ -136,4 +136,7 @@ enum stack_protector_guard { > >> #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) > >> #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) > >> > >> +#define MASK_ZTSO (1 << 0) > >> +#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0) > >> + > >> #endif /* ! GCC_RISCV_OPTS_H */ > >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > >> index 9fffc08220d..6128bfa31dc 100644 > >> --- a/gcc/config/riscv/riscv.opt > >> +++ b/gcc/config/riscv/riscv.opt > >> @@ -209,6 +209,9 @@ int riscv_vector_eew_flags > >> TargetVariable > >> int riscv_zvl_flags > >> > >> +TargetVariable > >> +int riscv_ztso_subext > >> + > >> Enum > >> Name(isa_spec_class) Type(enum riscv_isa_spec_class) > >> Supported ISA specs (for use with the -misa-spec= option): > >> -- > >> 2.31.1.windows.1 > >> >
On Mon, 21 Mar 2022 19:39:24 PDT (-0700), kito.cheng@sifive.com wrote: > Hi Palmer: > > I guess the problem is binutils isn't included and it's too close to the > GCC release, and binutils will report errors if it has any unsupported > extensions. Ya, sorry, I was trying to say that we should have more than just the binutils support -- IIUC having binutils support the GCC flags at release is the standard way to do things, and I don't see any reason to rush this. > > Most distro will use GCC 12 + binutils 2.38 or GCC 11 + binutils 2.38, so > either combination doesn't work for march string with ztso. > > So that's why I am not intending to include that at this moment, but maybe > we could include that first and it'll work once binutils 2.39 released, > then we can have GCC 12 + binutils 2.39 in the next few months. > > Anyway, I think I am fine with that, and I'll ping Nelson for the binutils > part. > > On Tue, Mar 22, 2022 at 9:13 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > >> On Thu, 17 Mar 2022 23:52:04 PDT (-0700), gcc-patches@gcc.gnu.org wrote: >> > Hi Shi-Hua: >> > >> > Thanks, this patch is LGTM, but I would defer that until stage 1, >> > because the binutils part isn't merget yet. >> >> IMO we should at least have a __riscv_ztso define, and ideally have the >> relevent builtins ported (atomics, fences, etc) as well. Otherwise this >> is really just setting a bit that makes binaries incompatible without >> providing any real benefit. That'll also let us work through how these >> mappings should be implemented, so we don't end up with issues like we >> did with WMO. >> >> > >> > On Tue, Mar 15, 2022 at 5:10 PM <shihua@iscas.ac.cn> wrote: >> >> >> >> From: LiaoShihua <shihua@iscas.ac.cn> >> >> >> >> ZTSO is the extension of tatol store order model. >> >> This extension adds no new instructions to the ISA, and you can >> use it with arch "ztso". >> >> If you use it, TSO flag will be generate in the ELF header. >> >> >> >> gcc/ChangeLog: >> >> >> >> * common/config/riscv/riscv-common.cc: define new arch. >> >> * config/riscv/riscv-opts.h (MASK_ZTSO): Ditto. >> >> (TARGET_ZTSO):Ditto. >> >> * config/riscv/riscv.opt:Ditto. >> >> >> >> --- >> >> gcc/common/config/riscv/riscv-common.cc | 4 +++- >> >> gcc/config/riscv/riscv-opts.h | 3 +++ >> >> gcc/config/riscv/riscv.opt | 3 +++ >> >> 3 files changed, 9 insertions(+), 1 deletion(-) >> >> >> >> diff --git a/gcc/common/config/riscv/riscv-common.cc >> b/gcc/common/config/riscv/riscv-common.cc >> >> index a904893b9ed..f4730b991d7 100644 >> >> --- a/gcc/common/config/riscv/riscv-common.cc >> >> +++ b/gcc/common/config/riscv/riscv-common.cc >> >> @@ -185,6 +185,8 @@ static const struct riscv_ext_version >> riscv_ext_version_table[] = >> >> {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, >> >> {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, >> >> >> >> + {"ztso", ISA_SPEC_CLASS_NONE, 0, 1}, >> >> + >> >> /* Terminate the list. */ >> >> {NULL, ISA_SPEC_CLASS_NONE, 0, 0} >> >> }; >> >> @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t >> riscv_ext_flag_table[] = >> >> {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, >> >> {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, >> >> >> >> - >> >> + {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, >> >> {NULL, NULL, 0} >> >> }; >> >> >> >> diff --git a/gcc/config/riscv/riscv-opts.h >> b/gcc/config/riscv/riscv-opts.h >> >> index 929e4e3a7c5..9cb5f2a550a 100644 >> >> --- a/gcc/config/riscv/riscv-opts.h >> >> +++ b/gcc/config/riscv/riscv-opts.h >> >> @@ -136,4 +136,7 @@ enum stack_protector_guard { >> >> #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) >> >> #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) >> >> >> >> +#define MASK_ZTSO (1 << 0) >> >> +#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0) >> >> + >> >> #endif /* ! GCC_RISCV_OPTS_H */ >> >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt >> >> index 9fffc08220d..6128bfa31dc 100644 >> >> --- a/gcc/config/riscv/riscv.opt >> >> +++ b/gcc/config/riscv/riscv.opt >> >> @@ -209,6 +209,9 @@ int riscv_vector_eew_flags >> >> TargetVariable >> >> int riscv_zvl_flags >> >> >> >> +TargetVariable >> >> +int riscv_ztso_subext >> >> + >> >> Enum >> >> Name(isa_spec_class) Type(enum riscv_isa_spec_class) >> >> Supported ISA specs (for use with the -misa-spec= option): >> >> -- >> >> 2.31.1.windows.1 >> >> >>
Hi Palmer: Cool, so I keep that on the GCC 13 queue :) On Tue, Mar 22, 2022 at 10:41 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Mon, 21 Mar 2022 19:39:24 PDT (-0700), kito.cheng@sifive.com wrote: > > Hi Palmer: > > > > I guess the problem is binutils isn't included and it's too close to the > > GCC release, and binutils will report errors if it has any unsupported > > extensions. > > Ya, sorry, I was trying to say that we should have more than just the > binutils support -- IIUC having binutils support the GCC flags at > release is the standard way to do things, and I don't see any reason to > rush this. > > > > > Most distro will use GCC 12 + binutils 2.38 or GCC 11 + binutils 2.38, so > > either combination doesn't work for march string with ztso. > > > > So that's why I am not intending to include that at this moment, but maybe > > we could include that first and it'll work once binutils 2.39 released, > > then we can have GCC 12 + binutils 2.39 in the next few months. > > > > Anyway, I think I am fine with that, and I'll ping Nelson for the binutils > > part. > > > > On Tue, Mar 22, 2022 at 9:13 AM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > > >> On Thu, 17 Mar 2022 23:52:04 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > >> > Hi Shi-Hua: > >> > > >> > Thanks, this patch is LGTM, but I would defer that until stage 1, > >> > because the binutils part isn't merget yet. > >> > >> IMO we should at least have a __riscv_ztso define, and ideally have the > >> relevent builtins ported (atomics, fences, etc) as well. Otherwise this > >> is really just setting a bit that makes binaries incompatible without > >> providing any real benefit. That'll also let us work through how these > >> mappings should be implemented, so we don't end up with issues like we > >> did with WMO. > >> > >> > > >> > On Tue, Mar 15, 2022 at 5:10 PM <shihua@iscas.ac.cn> wrote: > >> >> > >> >> From: LiaoShihua <shihua@iscas.ac.cn> > >> >> > >> >> ZTSO is the extension of tatol store order model. > >> >> This extension adds no new instructions to the ISA, and you can > >> use it with arch "ztso". > >> >> If you use it, TSO flag will be generate in the ELF header. > >> >> > >> >> gcc/ChangeLog: > >> >> > >> >> * common/config/riscv/riscv-common.cc: define new arch. > >> >> * config/riscv/riscv-opts.h (MASK_ZTSO): Ditto. > >> >> (TARGET_ZTSO):Ditto. > >> >> * config/riscv/riscv.opt:Ditto. > >> >> > >> >> --- > >> >> gcc/common/config/riscv/riscv-common.cc | 4 +++- > >> >> gcc/config/riscv/riscv-opts.h | 3 +++ > >> >> gcc/config/riscv/riscv.opt | 3 +++ > >> >> 3 files changed, 9 insertions(+), 1 deletion(-) > >> >> > >> >> diff --git a/gcc/common/config/riscv/riscv-common.cc > >> b/gcc/common/config/riscv/riscv-common.cc > >> >> index a904893b9ed..f4730b991d7 100644 > >> >> --- a/gcc/common/config/riscv/riscv-common.cc > >> >> +++ b/gcc/common/config/riscv/riscv-common.cc > >> >> @@ -185,6 +185,8 @@ static const struct riscv_ext_version > >> riscv_ext_version_table[] = > >> >> {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, > >> >> {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, > >> >> > >> >> + {"ztso", ISA_SPEC_CLASS_NONE, 0, 1}, > >> >> + > >> >> /* Terminate the list. */ > >> >> {NULL, ISA_SPEC_CLASS_NONE, 0, 0} > >> >> }; > >> >> @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t > >> riscv_ext_flag_table[] = > >> >> {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, > >> >> {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, > >> >> > >> >> - > >> >> + {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, > >> >> {NULL, NULL, 0} > >> >> }; > >> >> > >> >> diff --git a/gcc/config/riscv/riscv-opts.h > >> b/gcc/config/riscv/riscv-opts.h > >> >> index 929e4e3a7c5..9cb5f2a550a 100644 > >> >> --- a/gcc/config/riscv/riscv-opts.h > >> >> +++ b/gcc/config/riscv/riscv-opts.h > >> >> @@ -136,4 +136,7 @@ enum stack_protector_guard { > >> >> #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) > >> >> #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) > >> >> > >> >> +#define MASK_ZTSO (1 << 0) > >> >> +#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0) > >> >> + > >> >> #endif /* ! GCC_RISCV_OPTS_H */ > >> >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > >> >> index 9fffc08220d..6128bfa31dc 100644 > >> >> --- a/gcc/config/riscv/riscv.opt > >> >> +++ b/gcc/config/riscv/riscv.opt > >> >> @@ -209,6 +209,9 @@ int riscv_vector_eew_flags > >> >> TargetVariable > >> >> int riscv_zvl_flags > >> >> > >> >> +TargetVariable > >> >> +int riscv_ztso_subext > >> >> + > >> >> Enum > >> >> Name(isa_spec_class) Type(enum riscv_isa_spec_class) > >> >> Supported ISA specs (for use with the -misa-spec= option): > >> >> -- > >> >> 2.31.1.windows.1 > >> >> > >>
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index a904893b9ed..f4730b991d7 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -185,6 +185,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"ztso", ISA_SPEC_CLASS_NONE, 0, 1}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -1080,7 +1082,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, - + {"ztso", &gcc_options::x_riscv_ztso_subext, MASK_ZTSO}, {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 929e4e3a7c5..9cb5f2a550a 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -136,4 +136,7 @@ enum stack_protector_guard { #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) +#define MASK_ZTSO (1 << 0) +#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 9fffc08220d..6128bfa31dc 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -209,6 +209,9 @@ int riscv_vector_eew_flags TargetVariable int riscv_zvl_flags +TargetVariable +int riscv_ztso_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option):