Message ID | 20220223092126.78821-1-hongtao.liu@intel.com |
---|---|
State | New |
Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8669D3947C36 for <patchwork@sourceware.org>; Wed, 23 Feb 2022 09:21:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8669D3947C36 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1645608118; bh=eAcoc7uNo+lC3D3sPspXPDtbVsxCdzo1RMVKZJIVb4o=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=GSBf44M5zG3OiUgi7shP844Ya2b/PagDCfQHQEk369zs9BjhTwVl5XpahSvM5NUCg dqIJ45EGTlm7p6uDPJSkNUiDyzhMkb6q9IZhUX5H9lEJJ5KrUfa8bJNksnTxHoCkld ndITn6hsf98f0EgVzwYRTWVCk2vIzBm+XN7Ii5Eo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 7A8C03858D20 for <gcc-patches@gcc.gnu.org>; Wed, 23 Feb 2022 09:21:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7A8C03858D20 X-IronPort-AV: E=McAfee;i="6200,9189,10266"; a="251658994" X-IronPort-AV: E=Sophos;i="5.88,390,1635231600"; d="scan'208";a="251658994" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2022 01:21:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,390,1635231600"; d="scan'208";a="548160634" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga008.jf.intel.com with ESMTP; 23 Feb 2022 01:21:28 -0800 Received: from shliclel051.sh.intel.com (shliclel051.sh.intel.com [10.239.236.51]) by scymds01.sc.intel.com with ESMTP id 21N9LQL2026628; Wed, 23 Feb 2022 01:21:27 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Fix typo in <code>v1ti3. Date: Wed, 23 Feb 2022 17:21:26 +0800 Message-Id: <20220223092126.78821-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: liuhongt via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: liuhongt <hongtao.liu@intel.com> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
[i386] Fix typo in <code>v1ti3.
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Commit Message
Liu, Hongtao
Feb. 23, 2022, 9:21 a.m. UTC
For evex encoding vp{xor,or,and}, suffix is needed. Or there would be an error for vpxor %ymm0, %ymm31, %ymm1 Error: unsupported instruction `vpxor' Bootstrapped and regtested x86_64-pc-linux-gnu{-m32,}. Pushed to trunk. gcc/ChangeLog: * config/i386/sse.md (<code>v1ti3): Add suffix and replace isa attr of alternative 2 from avx to avx512vl. --- gcc/config/i386/sse.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Comments
On Wed, Feb 23, 2022 at 05:21:26PM +0800, liuhongt via Gcc-patches wrote: > For evex encoding vp{xor,or,and}, suffix is needed. > > Or there would be an error for > vpxor %ymm0, %ymm31, %ymm1 The insn is about V1TImode, so the error would be on vpxor %xmm0, %xmm31, %xmm1 > > Error: unsupported instruction `vpxor' > > Bootstrapped and regtested x86_64-pc-linux-gnu{-m32,}. > Pushed to trunk. > > gcc/ChangeLog: > > * config/i386/sse.md (<code>v1ti3): Add suffix and replace > isa attr of alternative 2 from avx to avx512vl. The patch looks good, but I think it would be nice to have a dg-do assemble testcase for it. Something like untested: /* { dg-do assemble { target { int128 && avx512vl } } } */ /* { dg-options "-O2 -mavx512vl" } */ typedef __int128 V __attribute__((vector_size (16))); void foo (V *x, V *y, V *z) { register V a __asm ("xmm31") = *z; __asm ("" : "+v" (a)); x[0] = y[0] & a; x[1] = y[1] | a; x[2] = y[2] ^ a; } Jakub
On Wed, Feb 23, 2022 at 5:48 PM Jakub Jelinek via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > On Wed, Feb 23, 2022 at 05:21:26PM +0800, liuhongt via Gcc-patches wrote: > > For evex encoding vp{xor,or,and}, suffix is needed. > > > > Or there would be an error for > > vpxor %ymm0, %ymm31, %ymm1 > > The insn is about V1TImode, so the error would be on > vpxor %xmm0, %xmm31, %xmm1 > > > > > Error: unsupported instruction `vpxor' > > > > Bootstrapped and regtested x86_64-pc-linux-gnu{-m32,}. > > Pushed to trunk. > > > > gcc/ChangeLog: > > > > * config/i386/sse.md (<code>v1ti3): Add suffix and replace > > isa attr of alternative 2 from avx to avx512vl. > > The patch looks good, but I think it would be nice to have a dg-do assemble > testcase for it. Yes will add. > Something like untested: > /* { dg-do assemble { target { int128 && avx512vl } } } */ > /* { dg-options "-O2 -mavx512vl" } */ > > typedef __int128 V __attribute__((vector_size (16))); > > void > foo (V *x, V *y, V *z) > { > register V a __asm ("xmm31") = *z; > __asm ("" : "+v" (a)); > x[0] = y[0] & a; > x[1] = y[1] | a; > x[2] = y[2] ^ a; > } > > Jakub >
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b2f56345c65..3066ea3734a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17025,8 +17025,8 @@ (define_insn "<code>v1ti3" "@ p<logic>\t{%2, %0|%0, %2} vp<logic>\t{%2, %1, %0|%0, %1, %2} - vp<logic>\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "isa" "noavx,avx,avx") + vp<logic>d\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,avx,avx512vl") (set_attr "prefix" "orig,vex,evex") (set_attr "prefix_data16" "1,*,*") (set_attr "type" "sselog")