diff mbox series

[Gimple] Fix ICE. [PR103682]

Message ID 20211214045810.60928-1-hongtao.liu@intel.com
State New
Headers
Series [Gimple] Fix ICE. [PR103682] |

Commit Message

liuhongt Dec. 14, 2021, 4:58 a.m. UTC 
  Check is_gimple_assign before gimple_assign_rhs_code.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?

gcc/ChangeLog:

	PR target/103682
	* tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check
	is_gimple_assign before gimple_assign_rhs_code.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr103682.c: New test.
---
 gcc/testsuite/gcc.target/i386/pr103682.c | 6 ++++++
 gcc/tree-ssa-ccp.c                       | 4 ++--
 2 files changed, 8 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr103682.c

Comments

Andrew Pinski Dec. 14, 2021, 5:03 a.m. UTC | #1 
On Mon, Dec 13, 2021 at 8:59 PM liuhongt via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Check is_gimple_assign before gimple_assign_rhs_code.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
> Ok for trunk?
>
> gcc/ChangeLog:
>
>         PR target/103682
>         * tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check
>         is_gimple_assign before gimple_assign_rhs_code.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/i386/pr103682.c: New test.

This testcase should just go in gcc.c-torture/compile and remove the
dg-options too.
The main reason there is nothing specific to x86 here.

Thanks,
Andrew Pinski

> ---
>  gcc/testsuite/gcc.target/i386/pr103682.c | 6 ++++++
>  gcc/tree-ssa-ccp.c                       | 4 ++--
>  2 files changed, 8 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr103682.c
>
> diff --git a/gcc/testsuite/gcc.target/i386/pr103682.c b/gcc/testsuite/gcc.target/i386/pr103682.c
> new file mode 100644
> index 00000000000..52371879a69
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr103682.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +int bug(unsigned *ready, unsigned u) {
> +  return __atomic_fetch_and (ready, ~u, 0) & u;
> +}
> diff --git a/gcc/tree-ssa-ccp.c b/gcc/tree-ssa-ccp.c
> index 9e12da8f011..a5b1f60f979 100644
> --- a/gcc/tree-ssa-ccp.c
> +++ b/gcc/tree-ssa-ccp.c
> @@ -3703,8 +3703,8 @@ optimize_atomic_bit_test_and (gimple_stmt_iterator *gsip,
>               g = SSA_NAME_DEF_STMT (mask);
>             }
>
> -         rhs_code = gimple_assign_rhs_code (g);
> -         if (rhs_code != LSHIFT_EXPR
> +         if (!is_gimple_assign (g)
> +             || gimple_assign_rhs_code (g) != LSHIFT_EXPR
>               || !integer_onep (gimple_assign_rhs1 (g)))
>             return;
>           bit = gimple_assign_rhs2 (g);
> --
> 2.18.1
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/i386/pr103682.c b/gcc/testsuite/gcc.target/i386/pr103682.c
new file mode 100644
index 00000000000..52371879a69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr103682.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int bug(unsigned *ready, unsigned u) {
+  return __atomic_fetch_and (ready, ~u, 0) & u;
+}
diff --git a/gcc/tree-ssa-ccp.c b/gcc/tree-ssa-ccp.c
index 9e12da8f011..a5b1f60f979 100644
--- a/gcc/tree-ssa-ccp.c
+++ b/gcc/tree-ssa-ccp.c
@@ -3703,8 +3703,8 @@  optimize_atomic_bit_test_and (gimple_stmt_iterator *gsip,
 	      g = SSA_NAME_DEF_STMT (mask);
 	    }
 
-	  rhs_code = gimple_assign_rhs_code (g);
-	  if (rhs_code != LSHIFT_EXPR
+	  if (!is_gimple_assign (g)
+	      || gimple_assign_rhs_code (g) != LSHIFT_EXPR
 	      || !integer_onep (gimple_assign_rhs1 (g)))
 	    return;
 	  bit = gimple_assign_rhs2 (g);