Message ID | 1660860233-11175-11-git-send-email-apinski@marvell.com |
---|---|
State | New |
Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 583EF38560A4 for <patchwork@sourceware.org>; Thu, 18 Aug 2022 22:07:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 583EF38560A4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660860469; bh=dMXZcIuSX5tUsXJmdzAbwh6nG2+RoH1xqW6QcNDu4vo=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Wij8rbguo9dlDHizjM/kqzbvheRJFTfTjG/ZYSqpYAHyM9w0dxhkwjJXX/oEViuSB BVzsCJTYwTh0qmfKVnY7HPpAhjrx2aM6wGcKXfKXrgTv/rccM+/IajW6vWcG4PD0Ck 0J5oZ7IzZU3UhdU6LipHviy0DEvTivLaHsuxAgp0= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 9E1E438582A2 for <gcc-patches@gcc.gnu.org>; Thu, 18 Aug 2022 22:04:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9E1E438582A2 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27IHqWrH002457 for <gcc-patches@gcc.gnu.org>; Thu, 18 Aug 2022 15:04:05 -0700 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3j1t6r10wr-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for <gcc-patches@gcc.gnu.org>; Thu, 18 Aug 2022 15:04:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 18 Aug 2022 15:04:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 18 Aug 2022 15:04:04 -0700 Received: from linux.wrightpinski.org.com (unknown [10.69.242.198]) by maili.marvell.com (Postfix) with ESMTP id 41F0B3F7080; Thu, 18 Aug 2022 15:04:04 -0700 (PDT) To: <gcc-patches@gcc.gnu.org> Subject: [PATCH 10/10] [RISCV] Fix PR 106632 and PR 106588 a few constraints in bitmanip.md Date: Thu, 18 Aug 2022 15:03:53 -0700 Message-ID: <1660860233-11175-11-git-send-email-apinski@marvell.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1660860233-11175-1-git-send-email-apinski@marvell.com> References: <1660860233-11175-1-git-send-email-apinski@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: khEe3rJrtfgJ71rnKBaFx3wM7fEl93ng X-Proofpoint-GUID: khEe3rJrtfgJ71rnKBaFx3wM7fEl93ng X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: apinski--- via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: apinski@marvell.com Cc: Andrew Pinski <apinski@marvell.com> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
Fix/improve the RISCV backend
|
|
Commit Message
Li, Pan2 via Gcc-patches
Aug. 18, 2022, 10:03 p.m. UTC
From: Andrew Pinski <apinski@marvell.com>
The constraints should be n instead of i. Also there
needs to a check for out of bounds zero_extract for
*bexti.
gcc/ChangeLog:
PR target/106632
PR target/106588
* config/riscv/bitmanip.md (*shNadduw): Use n constraint
instead of i.
(*slliuw): Likewise.
(*bexti): Likewise. Also add a check for operands[2] to be less
than the mode bitsize.
---
gcc/config/riscv/bitmanip.md | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
Comments
On Fri, Aug 19, 2022 at 6:08 AM apinski--- via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > From: Andrew Pinski <apinski@marvell.com> > > The constraints should be n instead of i. Also there > needs to a check for out of bounds zero_extract for > *bexti. > > gcc/ChangeLog: > > PR target/106632 > PR target/106588 > * config/riscv/bitmanip.md (*shNadduw): Use n constraint > instead of i. > (*slliuw): Likewise. > (*bexti): Likewise. Also add a check for operands[2] to be less > than the mode bitsize. > --- > gcc/config/riscv/bitmanip.md | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > index 026299d6703..ecf5b51b533 100644 > --- a/gcc/config/riscv/bitmanip.md > +++ b/gcc/config/riscv/bitmanip.md > @@ -44,7 +44,7 @@ (define_insn "*shNadduw" > (plus:DI > (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") > (match_operand:QI 2 "imm123_operand" "Ds3")) > - (match_operand 3 "immediate_operand" "")) > + (match_operand 3 "immediate_operand" "n")) > (match_operand:DI 4 "register_operand" "r")))] > "TARGET_64BIT && TARGET_ZBA > && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" > @@ -110,7 +110,7 @@ (define_insn "*slliuw" > [(set (match_operand:DI 0 "register_operand" "=r") > (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") > (match_operand:QI 2 "immediate_operand" "I")) > - (match_operand 3 "immediate_operand" "")))] > + (match_operand 3 "immediate_operand" "n")))] > "TARGET_64BIT && TARGET_ZBA > && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" > "slli.uw\t%0,%1,%2" > @@ -354,6 +354,7 @@ (define_insn "*bexti" > (zero_extract:X (match_operand:X 1 "register_operand" "r") > (const_int 1) > (match_operand 2 "immediate_operand" "i")))] Seems something wrong during generating this patch, this line should be removed. > - "TARGET_ZBS" > + (match_operand 2 "immediate_operand" "n")))] > + "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" > "bexti\t%0,%1,%2" > [(set_attr "type" "bitmanip")]) > -- > 2.27.0 >
On Thu, 18 Aug 2022 15:03:53 PDT (-0700), gcc-patches@gcc.gnu.org wrote: > From: Andrew Pinski <apinski@marvell.com> > > The constraints should be n instead of i. Also there > needs to a check for out of bounds zero_extract for > *bexti. > > gcc/ChangeLog: > > PR target/106632 > PR target/106588 > * config/riscv/bitmanip.md (*shNadduw): Use n constraint > instead of i. > (*slliuw): Likewise. > (*bexti): Likewise. Also add a check for operands[2] to be less > than the mode bitsize. > --- > gcc/config/riscv/bitmanip.md | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > index 026299d6703..ecf5b51b533 100644 > --- a/gcc/config/riscv/bitmanip.md > +++ b/gcc/config/riscv/bitmanip.md > @@ -44,7 +44,7 @@ (define_insn "*shNadduw" > (plus:DI > (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") > (match_operand:QI 2 "imm123_operand" "Ds3")) > - (match_operand 3 "immediate_operand" "")) > + (match_operand 3 "immediate_operand" "n")) > (match_operand:DI 4 "register_operand" "r")))] > "TARGET_64BIT && TARGET_ZBA > && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" > @@ -110,7 +110,7 @@ (define_insn "*slliuw" > [(set (match_operand:DI 0 "register_operand" "=r") > (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") > (match_operand:QI 2 "immediate_operand" "I")) > - (match_operand 3 "immediate_operand" "")))] > + (match_operand 3 "immediate_operand" "n")))] > "TARGET_64BIT && TARGET_ZBA > && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" > "slli.uw\t%0,%1,%2" > @@ -354,6 +354,7 @@ (define_insn "*bexti" > (zero_extract:X (match_operand:X 1 "register_operand" "r") > (const_int 1) > (match_operand 2 "immediate_operand" "i")))] > - "TARGET_ZBS" > + (match_operand 2 "immediate_operand" "n")))] > + "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" > "bexti\t%0,%1,%2" > [(set_attr "type" "bitmanip")]) I think something went off the rails on that last chunk and it should look more like @@ -353,7 +353,7 @@ [(set (match_operand:X 0 "register_operand" "=r") (zero_extract:X (match_operand:X 1 "register_operand" "r") (const_int 1) - (match_operand 2 "immediate_operand" "i")))] - "TARGET_ZBS" + (match_operand 2 "immediate_operand" "n")))] + "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" "bexti\t%0,%1,%2" [(set_attr "type" "bitmanip")]) with that I get no new failures on trunk with all of these (though I'm still only testing the Linux multilibs for now).
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 026299d6703..ecf5b51b533 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -44,7 +44,7 @@ (define_insn "*shNadduw" (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "imm123_operand" "Ds3")) - (match_operand 3 "immediate_operand" "")) + (match_operand 3 "immediate_operand" "n")) (match_operand:DI 4 "register_operand" "r")))] "TARGET_64BIT && TARGET_ZBA && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" @@ -110,7 +110,7 @@ (define_insn "*slliuw" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "immediate_operand" "I")) - (match_operand 3 "immediate_operand" "")))] + (match_operand 3 "immediate_operand" "n")))] "TARGET_64BIT && TARGET_ZBA && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" "slli.uw\t%0,%1,%2" @@ -354,6 +354,7 @@ (define_insn "*bexti" (zero_extract:X (match_operand:X 1 "register_operand" "r") (const_int 1) (match_operand 2 "immediate_operand" "i")))] - "TARGET_ZBS" + (match_operand 2 "immediate_operand" "n")))] + "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" "bexti\t%0,%1,%2" [(set_attr "type" "bitmanip")])