diff mbox series

[PATCH-5,rs6000] Replace explicit CC bit reverse with common format

Message ID 01bf20ab-2ba0-4c31-8717-568682d4d321@linux.ibm.com
State New
Headers
Series [PATCH-5,rs6000] Replace explicit CC bit reverse with common format |

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Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm fail Patch failed to apply

Commit Message

HAO CHEN GUI May 6, 2024, 6:05 a.m. UTC 
  Hi,
  It's the fifth patch of a series of patches optimizing CC modes on
rs6000.

  There are some explicit CR6 bit reverse (mfcr/xor) expand in vector.md.
As the forth patch optimized CC bit reverse implement, the patch changes
the explicit format to the common format (testing if the bit is not set).
With the common format, it can matches different implement on different
sub-targets. On Power10, it should be setbcr. On Power9, it's isel. On
Power8 and below, it's mfcr/xor.

  Bootstrapped and tested on powerpc64-linux BE and LE with no
regressions. Is it OK for the trunk?

Thanks
Gui Haochen

ChangeLog
rs6000: Replace explicit CC bit reverse with common format

This patch replaces explicit CC bit reverse (mfcr/xor) with the common format
so that it can match setbcr on Power 10, isel on Power 9 and mfcr/xor on
other sub-targets.

gcc/
	* config/rs6000/vector.md (vector_ae_<mode>_p): Replace explicit CC
	bit reverse with common format.
	(vector_ae_v2di_p): Likewise.
	(vector_ae_v1ti_p): Likewise.
	(vector_ae_<mode>_p): Likewise.
	(cr6_test_for_zero): Likewise.
	(cr6_test_for_lt): Likewise.

gcc/testsuite/
	* gcc.target/powerpc/vsu/vec-any-eq-10.c: Replace rlwinm with isel.
	* gcc.target/powerpc/vsu/vec-any-eq-14.c: Replace rlwinm with isel.
	* gcc.target/powerpc/vsu/vec-any-eq-7.c: Replace rlwinm with isel.
	* gcc.target/powerpc/vsu/vec-any-eq-8.c: Replace rlwinm with isel.
	* gcc.target/powerpc/vsu/vec-any-eq-9.c: Replace rlwinm with isel.

patch.diff
diff mbox series

Patch

diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index f86c1f2990e..b1bbf9bac2d 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -942,11 +942,8 @@  (define_expand "vector_ae_<mode>_p"
 	  (ne:VI (match_dup 1)
 		 (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CCLTEQ CR6_REGNO)
-	       (const_int 0)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
+	(ge:SI (reg:CCLTEQ CR6_REGNO)
+	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
   operands[3] = gen_reg_rtx (<MODE>mode);
@@ -1027,11 +1024,8 @@  (define_expand "vector_ae_v2di_p"
 	  (eq:V2DI (match_dup 1)
 		   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CCLTEQ CR6_REGNO)
-	       (const_int 0)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
+	(ne:SI (reg:CCLTEQ CR6_REGNO)
+	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
   operands[3] = gen_reg_rtx (V2DImode);
@@ -1048,11 +1042,8 @@  (define_expand "vector_ae_v1ti_p"
 	  (eq:V1TI (match_dup 1)
 		   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CCLTEQ CR6_REGNO)
-	       (const_int 0)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
+	(ne:SI (reg:CCLTEQ CR6_REGNO)
+	       (const_int 0)))]
   "TARGET_POWER10"
 {
   operands[3] = gen_reg_rtx (V1TImode);
@@ -1095,11 +1086,8 @@  (define_expand "vector_ae_<mode>_p"
 	  (eq:VEC_F (match_dup 1)
 		    (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CCLTEQ CR6_REGNO)
-	       (const_int 0)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
+	(ne:SI (reg:CCLTEQ CR6_REGNO)
+	       (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
   operands[3] = gen_reg_rtx (<MODE>mode);
@@ -1172,11 +1160,8 @@  (define_expand "cr6_test_for_zero"
 ;; integer constant first argument equals one (aka __CR6_EQ_REV in altivec.h).
 (define_expand "cr6_test_for_zero_reverse"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(eq:SI (reg:CCLTEQ CR6_REGNO)
-	       (const_int 0)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
+	(ne:SI (reg:CCLTEQ CR6_REGNO)
+	       (const_int 0)))]
   "TARGET_ALTIVEC || TARGET_VSX"
   "")

@@ -1198,11 +1183,8 @@  (define_expand "cr6_test_for_lt"
 ;; (aka __CR6_LT_REV in altivec.h).
 (define_expand "cr6_test_for_lt_reverse"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(lt:SI (reg:CCLTEQ CR6_REGNO)
-	       (const_int 0)))
-   (set (match_dup 0)
-	(xor:SI (match_dup 0)
-		(const_int 1)))]
+	(ge:SI (reg:CCLTEQ CR6_REGNO)
+	       (const_int 0)))]
   "TARGET_ALTIVEC || TARGET_VSX"
   "")

diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c
index 30dfc83a97b..9743a496fb5 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-10.c
@@ -15,4 +15,4 @@  test_any_equal (vector unsigned long long *arg1_p,
 }

 /* { dg-final { scan-assembler "vcmpequd." } } */
-/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */
+/* { dg-final { scan-assembler "isel r?\[0-9\]+,0,r?\[0-9\]+,26" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c
index 4375bfe21cc..06779924a65 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-14.c
@@ -14,4 +14,4 @@  test_any_equal (vector bool long long *arg1_p, vector bool long long *arg2_p)
 }

 /* { dg-final { scan-assembler "vcmpequd." } } */
-/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */
+/* { dg-final { scan-assembler "isel r?\[0-9\]+,0,r?\[0-9\]+,26" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c
index 254a1161580..1c69216c8ea 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-7.c
@@ -14,4 +14,4 @@  test_any_equal (vector float *arg1_p, vector float *arg2_p)
 }

 /* { dg-final { scan-assembler "xvcmpeqsp." } } */
-/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */
+/* { dg-final { scan-assembler "isel r?\[0-9\]+,0,r?\[0-9\]+,26" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c
index d94ef89f3d0..ef959b4b01c 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-8.c
@@ -14,4 +14,4 @@  test_any_equal (vector double *arg1_p, vector double *arg2_p)
 }

 /* { dg-final { scan-assembler "xvcmpeqdp." } } */
-/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */
+/* { dg-final { scan-assembler "isel r?\[0-9\]+,0,r?\[0-9\]+,26" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c
index efe83cf2ee7..a1a81f68b08 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-any-eq-9.c
@@ -14,4 +14,4 @@  test_any_equal (vector long long *arg1_p, vector long long *arg2_p)
 }

 /* { dg-final { scan-assembler "vcmpequd." } } */
-/* { dg-final { scan-assembler "rlwinm r?\[0-9\]+,r?\[0-9\]+,27,1" } } */
+/* { dg-final { scan-assembler "isel r?\[0-9\]+,0,r?\[0-9\]+,26" } } */