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Tue, 16 Jan 2024 09:14:05 -0800 (PST) Received: from troughton.lym.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id o21-20020a05600c4fd500b0040e34ca648bsm20045876wmq.0.2024.01.16.09.14.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jan 2024 09:14:04 -0800 (PST) From: Mary Bennett <mary.bennett@embecosm.com> To: gcc-patches@gcc.gnu.org Cc: mary.bennett@embecosm.com Subject: [PATCH v3 0/2] RISC-V: Support CORE-V XCVSIMD extension Date: Tue, 16 Jan 2024 17:13:49 +0000 Message-Id: <20240116171351.913881-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240116163529.623568-1-mary.bennett@embecosm.com> References: <20240116163529.623568-1-mary.bennett@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org |
Series |
RISC-V: Support CORE-V XCVSIMD extension
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Message
Mary Bennett
Jan. 16, 2024, 5:13 p.m. UTC
v2 -> v3: * Removed duplicate ftype. This patch series presents the comprehensive implementation of the SIMD extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V builtins are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md [2] github.com/openhwgroup/corev-gcc Contributors: Mary Bennett <mary.bennett@embecosm.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> RISC-V: Add support for XCVsimd extension in CV32E40P RISC-V: Fix XCValu test gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/constraints.md | 30 + gcc/config/riscv/corev.def | 156 ++ gcc/config/riscv/corev.md | 1908 +++++++++++++++++ gcc/config/riscv/predicates.md | 20 + gcc/config/riscv/riscv-builtins.cc | 1 + gcc/config/riscv/riscv-ftypes.def | 8 + gcc/config/riscv/riscv.cc | 8 + gcc/config/riscv/riscv.opt | 2 + gcc/doc/extend.texi | 886 ++++++++ gcc/doc/sourcebuild.texi | 3 + .../gcc.target/riscv/cv-alu-fail-compile.c | 40 +- .../riscv/cv-simd-abs-b-compile-1.c | 11 + .../riscv/cv-simd-abs-h-compile-1.c | 11 + .../riscv/cv-simd-add-b-compile-1.c | 11 + .../riscv/cv-simd-add-div2-compile-1.c | 11 + .../riscv/cv-simd-add-div4-compile-1.c | 11 + .../riscv/cv-simd-add-div8-compile-1.c | 11 + .../riscv/cv-simd-add-h-compile-1.c | 11 + .../riscv/cv-simd-add-sc-b-compile-1.c | 30 + .../riscv/cv-simd-add-sc-h-compile-1.c | 30 + .../riscv/cv-simd-and-b-compile-1.c | 11 + .../riscv/cv-simd-and-h-compile-1.c | 11 + .../riscv/cv-simd-and-sc-b-compile-1.c | 30 + .../riscv/cv-simd-and-sc-h-compile-1.c | 30 + .../riscv/cv-simd-avg-b-compile-1.c | 11 + .../riscv/cv-simd-avg-h-compile-1.c | 11 + .../riscv/cv-simd-avg-sc-b-compile-1.c | 30 + .../riscv/cv-simd-avg-sc-h-compile-1.c | 30 + .../riscv/cv-simd-avgu-b-compile-1.c | 11 + .../riscv/cv-simd-avgu-h-compile-1.c | 11 + .../riscv/cv-simd-avgu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-avgu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpeq-b-compile-1.c | 11 + .../riscv/cv-simd-cmpeq-h-compile-1.c | 11 + .../riscv/cv-simd-cmpeq-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpeq-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpge-b-compile-1.c | 11 + .../riscv/cv-simd-cmpge-h-compile-1.c | 11 + .../riscv/cv-simd-cmpge-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpge-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpgeu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgeu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgeu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpgeu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpgt-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgt-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgt-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpgt-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpgtu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpgtu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpgtu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpgtu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmple-b-compile-1.c | 11 + .../riscv/cv-simd-cmple-h-compile-1.c | 11 + .../riscv/cv-simd-cmple-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmple-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpleu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpleu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpleu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpleu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmplt-b-compile-1.c | 11 + .../riscv/cv-simd-cmplt-h-compile-1.c | 11 + .../riscv/cv-simd-cmplt-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmplt-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cmpltu-b-compile-1.c | 11 + .../riscv/cv-simd-cmpltu-h-compile-1.c | 11 + .../riscv/cv-simd-cmpltu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-cmpltu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-cmpne-b-compile-1.c | 11 + .../riscv/cv-simd-cmpne-h-compile-1.c | 11 + .../riscv/cv-simd-cmpne-sc-b-compile-1.c | 30 + .../riscv/cv-simd-cmpne-sc-h-compile-1.c | 30 + .../riscv/cv-simd-cplxconj-compile-1.c | 11 + .../riscv/cv-simd-cplxmul-i-compile-1.c | 11 + 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.../riscv/cv-simd-extract-h-compile-1.c | 23 + .../riscv/cv-simd-extractu-b-compile-1.c | 23 + .../riscv/cv-simd-extractu-h-compile-1.c | 23 + .../riscv/cv-simd-insert-b-compile-1.c | 23 + .../riscv/cv-simd-insert-h-compile-1.c | 23 + .../riscv/cv-simd-march-compile-1.c | 1765 +++++++++++++++ .../riscv/cv-simd-max-b-compile-1.c | 11 + .../riscv/cv-simd-max-h-compile-1.c | 11 + .../riscv/cv-simd-max-sc-b-compile-1.c | 30 + .../riscv/cv-simd-max-sc-h-compile-1.c | 30 + .../riscv/cv-simd-maxu-b-compile-1.c | 11 + .../riscv/cv-simd-maxu-h-compile-1.c | 11 + .../riscv/cv-simd-maxu-sc-b-compile-1.c | 24 + .../riscv/cv-simd-maxu-sc-h-compile-1.c | 24 + .../riscv/cv-simd-min-b-compile-1.c | 11 + .../riscv/cv-simd-min-h-compile-1.c | 11 + .../riscv/cv-simd-min-sc-b-compile-1.c | 30 + .../riscv/cv-simd-min-sc-h-compile-1.c | 30 + .../riscv/cv-simd-minu-b-compile-1.c | 11 + .../riscv/cv-simd-minu-h-compile-1.c | 11 + .../riscv/cv-simd-minu-sc-b-compile-1.c | 24 + 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Comments
It's stage 4, so I think it would be great to not disturb code base too much, and adding intrinsic without adding VLS modes should be better way to go, and here is not really something serious coding style issue, just few minor indentation issue, so I gonna run regression to make not break anything else and then commit to trunk :)
pushed :) On Thu, Jan 25, 2024 at 9:53 PM Kito Cheng <kito.cheng@gmail.com> wrote: > > It's stage 4, so I think it would be great to not disturb code base > too much, and adding intrinsic without adding VLS modes should be > better way to go, and here is not really something serious coding > style issue, just few minor indentation issue, so I gonna run > regression to make not break anything else and then commit to trunk :)