mbox series

[v2,0/3] RISC-V: vectorised memory operations

Message ID 20231219095348.356551-1-slewis@rivosinc.com
Headers
Series RISC-V: vectorised memory operations |

Message

Sergei Lewis Dec. 19, 2023, 9:53 a.m. UTC 
  This patchset permits generation of inlined vectorised code for movmem, 
setmem and cmpmem, if and only if the operation size is 
at least one and at most eight vector registers' worth of data.

Further vectorisation rapidly becomes debatable due to code size concerns;
however, for these simple cases we do have an unambiguous performance win 
without sacrificing too much code size compared to a libc call.

Changes in v2:

* run clang-format over the code in addition to the 
  contrib/check_GNU_style.sh that was used for v1

* remove string.h include and refer to __builtin_* memory functions 
  in multilib tests

* respect stringop_strategy (don't vectorise if it doesn't include VECTOR)

* use an integer constraint for movmem length parameter

* use TARGET_MAX_LMUL unless riscv-autovec-lmul=dynamic 
  to ensure we respect the user's wishes if they request specific lmul

* add new unit tests to check that riscv-autovec-lmul is respected

* PR target/112109 added to changelog for patch 1/3 as requested

Sergei Lewis (3):
  RISC-V: movmem for RISCV with V extension
  RISC-V: setmem for RISCV with V extension
  RISC-V: cmpmem for RISCV with V extension

 gcc/config/riscv/riscv-protos.h               |   2 +
 gcc/config/riscv/riscv-string.cc              | 190 ++++++++++++++++++
 gcc/config/riscv/riscv.md                     |  51 +++++
 .../gcc.target/riscv/rvv/base/cmpmem-1.c      |  88 ++++++++
 .../gcc.target/riscv/rvv/base/cmpmem-2.c      |  74 +++++++
 .../gcc.target/riscv/rvv/base/cmpmem-3.c      |  45 +++++
 .../gcc.target/riscv/rvv/base/cmpmem-4.c      |  62 ++++++
 .../gcc.target/riscv/rvv/base/movmem-1.c      |  60 ++++++
 .../gcc.target/riscv/rvv/base/setmem-1.c      | 103 ++++++++++
 .../gcc.target/riscv/rvv/base/setmem-2.c      |  51 +++++
 .../gcc.target/riscv/rvv/base/setmem-3.c      |  69 +++++++
 11 files changed, 795 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/setmem-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/setmem-3.c