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[0/3] RISC-V: vectorised memory operations

Message ID 20231211094728.1623032-1-slewis@rivosinc.com
Headers
Series RISC-V: vectorised memory operations |

Message

Sergei Lewis Dec. 11, 2023, 9:47 a.m. UTC 
  This patchset permits generation of inlined vectorised code for movmem, 
setmem and cmpmem, if and only if the operation size is 
at least one and at most eight vector registers' worth of data.

Further vectorisation rapidly becomes debatable due to code size concerns;
however, for these simple cases we do have an unambiguous performance win 
without sacrificing too much code size compared to a libc call.

Signed-off-by: Sergei Lewis <slewis@rivosinc.com>

---

Sergei Lewis (3):
  RISC-V: movmem for RISCV with V extension
  RISC-V: setmem for RISCV with V extension
  RISC-V: cmpmem for RISCV with V extension

 gcc/config/riscv/riscv-protos.h               |   2 +
 gcc/config/riscv/riscv-string.cc              | 193 ++++++++++++++++++
 gcc/config/riscv/riscv.md                     |  51 +++++
 .../gcc.target/riscv/rvv/base/cmpmem-1.c      |  85 ++++++++
 .../gcc.target/riscv/rvv/base/cmpmem-2.c      |  69 +++++++
 .../gcc.target/riscv/rvv/base/movmem-1.c      |  59 ++++++
 .../gcc.target/riscv/rvv/base/setmem-1.c      |  99 +++++++++
 7 files changed, 558 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/cmpmem-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/movmem-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/setmem-1.c