[3/4] RISC-V: Lx/Sx macro insn tests

Message ID f730d726-3667-bb23-9e6f-fda9a8a6ee13@suse.com
State New
Headers
Series RISC-V: load/store macro insn handling adjustments |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Testing passed

Commit Message

Jan Beulich Oct. 30, 2023, 2:47 p.m. UTC
  Make sure these (continue to) work as intended.
  

Patch

--- /dev/null
+++ b/gas/testsuite/gas/riscv/l-s-macro.d
@@ -0,0 +1,56 @@ 
+#as: -march=rv64i
+#name: Lx/Sx macro insns
+#objdump: -dwr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+ <L>:
+[ 	]+[0-9a-f]+:[ 	]+00000517[ 	]+auipc[ 	]+a0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+bval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00050503[ 	]+lb[ 	]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_I[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00000517[ 	]+auipc[ 	]+a0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+bval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00054503[ 	]+lbu[ 	]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_I[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00000517[ 	]+auipc[ 	]+a0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+hval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00051503[ 	]+lh[ 	]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_I[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00000517[ 	]+auipc[ 	]+a0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+hval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00055503[ 	]+lhu[ 	]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_I[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00000517[ 	]+auipc[ 	]+a0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+wval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00052503[ 	]+lw[ 	]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_I[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00000517[ 	]+auipc[ 	]+a0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+wval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00056503[ 	]+lwu[ 	]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_I[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00000517[ 	]+auipc[ 	]+a0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+dval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00053503[ 	]+ld[ 	]+a0,0\(a0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_I[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+
+[0-9a-f]+ <S>:
+[ 	]+[0-9a-f]+:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+bval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00a28023[ 	]+sb[ 	]+a0,0\(t0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_S[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+hval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00a29023[ 	]+sh[ 	]+a0,0\(t0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_S[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+wval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00a2a023[ 	]+sw[ 	]+a0,0\(t0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_S[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00000297[ 	]+auipc[ 	]+t0,0x0[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_HI20[ 	]+dval
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
+[ 	]+[0-9a-f]+:[ 	]+00a2b023[ 	]+sd[ 	]+a0,0\(t0\) # [0-9a-f]+( <.*>)?[ 	]+[0-9a-f]+:[ 	]+R_RISCV_PCREL_LO12_S[ 	]+.*
+[ 	]+[0-9a-f]+:[ 	]+R_RISCV_RELAX.*
--- /dev/null
+++ b/gas/testsuite/gas/riscv/l-s-macro.s
@@ -0,0 +1,14 @@ 
+L:
+	lb	a0, bval
+	lbu	a0, bval
+	lh	a0, hval
+	lhu	a0, hval
+	lw	a0, wval
+	lwu	a0, wval
+	ld	a0, dval
+
+S:
+	sb	a0, bval, t0
+	sh	a0, hval, t0
+	sw	a0, wval, t0
+	sd	a0, dval, t0