diff mbox series

[REVIEW,ONLY,1/1] RISC-V: Add stub support for the 'Svadu' extension

Message ID ce94a866b132a0f233d405ff3e01c93b726cafdd.1693710769.git.research_trasio@irq.a4lg.com
State New
Headers
Series RISC-V: Add stub support for the 'Svadu' extension |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Testing passed

Commit Message

Tsukasa OI Sept. 3, 2023, 3:13 a.m. UTC 
  From: Tsukasa OI <research_trasio@irq.a4lg.com>

This commit implements support for 'Svadu' extension.  Because it does not
add any instructions or CSRs (but adds bits to existing CSRs), this commit
only adds extension name support and implication to the 'Zicsr' extension.

This is based on the "Hardware Updating of PTE A/D Bits (Svadu)"
specification, version 1.0-rc1 (Frozen):
<https://github.com/riscv/riscv-svadu/releases/tag/v1.0-rc1>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implication from
	'Svadu' to 'Zicsr'.  (riscv_supported_std_s_ext) Add 'Svadu'.
---
 bfd/elfxx-riscv.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index cb65024beaff..9189b7da8374 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1189,6 +1189,7 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"sscofpmf", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
+  {"svadu", "zicsr",		check_implicit_always},
   {NULL, NULL, NULL}
 };
 
@@ -1334,6 +1335,7 @@  static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"svadu",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svinval",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svnapot",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svpbmt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },