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[committed,1/2] MIPS/opcodes: Update INSN_CHIP_MASK for INSN_ALLEGREX

Message ID alpine.DEB.2.21.2406131313390.9248@angie.orcam.me.uk
State New
Headers
Series MIPS/opcodes: INSN_* flag clean-ups |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply

Commit Message

Maciej W. Rozycki June 13, 2024, 1:03 p.m. UTC 
  From: Maciej W. Rozycki <macro@redhat.com>

An update has been missed with commit df18f71b565c ("Add MIPS Allegrex 
CPU as a MIPS2-based CPU") for INSN_CHIP_MASK to include INSN_ALLEGREX.
Fix it.
---
 include/opcode/mips.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

binutils-mips-opcodes-chip-mask-allegrex.diff
diff mbox series

Patch

Index: binutils-gdb/include/opcode/mips.h
===================================================================
--- binutils-gdb.orig/include/opcode/mips.h
+++ binutils-gdb/include/opcode/mips.h
@@ -1225,7 +1225,7 @@  static const unsigned int mips_isa_table
 #undef ISAF
 
 /* Masks used for Chip specific instructions.  */
-#define INSN_CHIP_MASK		  0xc7ff4f60
+#define INSN_CHIP_MASK		  0xcfff4f60
 
 /* Cavium Networks Octeon instructions.  */
 #define INSN_OCTEON		  0x00000800