diff mbox series

[1/3] aarch64: Add support for GCS extension.

Message ID a1878c0d-87c3-a1f7-390a-d38ea089800b@arm.com
State Committed
Headers
Series [1/3] aarch64: Add support for GCS extension. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_check--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 fail Patch failed to apply

Commit Message

Srinath Parvathaneni Oct. 31, 2023, 5:49 p.m. UTC 
  Hi,

This patch adds for Guarded Control Stack Extension (GCS) extension. GCS 
feature is
optional from Armv9.4-A architecture and enabled by passing +gcs option 
to -march
(eg: -march=armv9.4-a+gcs) or using ".arch_extension gcs" directive in 
the assembly file.

Also this patch adds support for GCS instructions gcspushx, gcspopcx, 
gcspopx,
gcsss1, gcsss2, gcspushm, gcspopm, gcsstr and gcssttr.

For this feature in gas/doc/c-aarch64.texi: column 2 is marked N/A, as 
this column
"minimum architecture" is not relevant any more and will be removed in 
the later patches.

Regression tested for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.

Comments

Nick Clifton Nov. 2, 2023, 11:44 a.m. UTC | #1 
Hi Srinath,
> This patch adds for Guarded Control Stack Extension (GCS) extension. GCS feature is
> optional from Armv9.4-A architecture and enabled by passing +gcs option to -march
> (eg: -march=armv9.4-a+gcs) or using ".arch_extension gcs" directive in the assembly file.
> 
> Also this patch adds support for GCS instructions gcspushx, gcspopcx, gcspopx,
> gcsss1, gcsss2, gcspushm, gcspopm, gcsstr and gcssttr.
> 
> For this feature in gas/doc/c-aarch64.texi: column 2 is marked N/A, as this column
> "minimum architecture" is not relevant any more and will be removed in the later patches.
> 
> Regression tested for aarch64-none-elf target and found no regressions.
> 
> Ok for binutils-master?

Approved - please apply.

Cheers
   Nick
diff mbox series

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 896ea2d7eb24cd7295f953ce0c619b0a778024f0..60f616c10735b929980f7181e95b6d1159ab967b 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@ 
 -*- text -*-
 
+* Add support for Guarded Control Stack (GCS) for AArch64.
+
 * Add support for AArch64 Check Feature Status Extension (CHK).
 
 * Add support for 'armv8.9-a' and 'armv9.4-a' for -march in AArch64 GAS.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f5b7b427dd6b5a0bc899cc3c79f05c02005b6c5b..6d2040037c3ff2c4c5d1ff967ad3c7222d878c93 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10325,6 +10325,7 @@  static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"hbc",		AARCH64_FEATURE (HBC), AARCH64_NO_FEATURES},
   {"cssc",		AARCH64_FEATURE (CSSC), AARCH64_NO_FEATURES},
   {"chk",		AARCH64_FEATURE (CHK), AARCH64_NO_FEATURES},
+  {"gcs",		AARCH64_FEATURE (GCS), AARCH64_NO_FEATURES},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index f10a44eae9347d5432ad6f7d5a07da4946e53ae2..7e053185d30b378ca3a6da74dd4b925dba9b5422 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -261,6 +261,8 @@  automatically cause those extensions to be disabled.
  @tab Enable Transactional Memory Extensions.
 @item @code{chk} @tab ARMv8-A @tab No
  @tab Enable Check Feature Status Extension.
+@item @code{gcs} @tab N/A @tab No
+ @tab Enable Guarded Control Stack Extension.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/gcs-1-bad.d b/gas/testsuite/gas/aarch64/gcs-1-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..7c3a7ae50a8dc7bf411a6deb419f723d50ff3812
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/gcs-1-bad.d
@@ -0,0 +1,3 @@ 
+#as: -march=armv9.2-a
+#source: gcs-1.s
+#error_output: gcs-1-bad.l
diff --git a/gas/testsuite/gas/aarch64/gcs-1-bad.l b/gas/testsuite/gas/aarch64/gcs-1-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..ca8d17ab8fc5123f2444a6c54193ab2354be1e6e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/gcs-1-bad.l
@@ -0,0 +1,45 @@ 
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushx'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopcx'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopx'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm x15'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 x15'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 x15'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x15'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,sp'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,x1'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,x16'
+[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,sp'
diff --git a/gas/testsuite/gas/aarch64/gcs-1.d b/gas/testsuite/gas/aarch64/gcs-1.d
new file mode 100644
index 0000000000000000000000000000000000000000..51f9dd6afc5cca1e69ad408849d71a6c7e3f09cf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/gcs-1.d
@@ -0,0 +1,54 @@ 
+#name: Test of Guarded Control Stack Instructions.
+#as: -march=armv9.3-a+gcs
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	d508779f 	gcspushx
+.*:	d50877bf 	gcspopcx
+.*:	d50877df 	gcspopx
+.*:	d52b773f 	gcspopm
+.*:	d50b7700 	gcspushm	x0
+.*:	d50b770f 	gcspushm	x15
+.*:	d50b771e 	gcspushm	x30
+.*:	d50b771f 	gcspushm	xzr
+.*:	d50b7740 	gcsss1	x0
+.*:	d50b774f 	gcsss1	x15
+.*:	d50b775e 	gcsss1	x30
+.*:	d50b775f 	gcsss1	xzr
+.*:	d52b7760 	gcsss2	x0
+.*:	d52b776f 	gcsss2	x15
+.*:	d52b777e 	gcsss2	x30
+.*:	d52b777f 	gcsss2	xzr
+.*:	d52b7720 	gcspopm	x0
+.*:	d52b772f 	gcspopm	x15
+.*:	d52b773e 	gcspopm	x30
+.*:	d52b773f 	gcspopm
+.*:	d91f0c20 	gcsstr	x0, x1
+.*:	d91f0e00 	gcsstr	x0, x16
+.*:	d91f0fe0 	gcsstr	x0, sp
+.*:	d91f0c2f 	gcsstr	x15, x1
+.*:	d91f0e0f 	gcsstr	x15, x16
+.*:	d91f0fef 	gcsstr	x15, sp
+.*:	d91f0c3e 	gcsstr	x30, x1
+.*:	d91f0e1e 	gcsstr	x30, x16
+.*:	d91f0ffe 	gcsstr	x30, sp
+.*:	d91f0c3f 	gcsstr	xzr, x1
+.*:	d91f0e1f 	gcsstr	xzr, x16
+.*:	d91f0fff 	gcsstr	xzr, sp
+.*:	d91f1c20 	gcssttr	x0, x1
+.*:	d91f1e00 	gcssttr	x0, x16
+.*:	d91f1fe0 	gcssttr	x0, sp
+.*:	d91f1c2f 	gcssttr	x15, x1
+.*:	d91f1e0f 	gcssttr	x15, x16
+.*:	d91f1fef 	gcssttr	x15, sp
+.*:	d91f1c3e 	gcssttr	x30, x1
+.*:	d91f1e1e 	gcssttr	x30, x16
+.*:	d91f1ffe 	gcssttr	x30, sp
+.*:	d91f1c3f 	gcssttr	xzr, x1
+.*:	d91f1e1f 	gcssttr	xzr, x16
+.*:	d91f1fff 	gcssttr	xzr, sp
diff --git a/gas/testsuite/gas/aarch64/gcs-1.s b/gas/testsuite/gas/aarch64/gcs-1.s
new file mode 100644
index 0000000000000000000000000000000000000000..9706587878d51d0c9874fdf1325d1052dd55ff57
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/gcs-1.s
@@ -0,0 +1,19 @@ 
+	.text
+	gcspushx
+	gcspopcx
+	gcspopx
+	gcspopm
+
+	.irp op gcspushm, gcsss1, gcsss2, gcspopm
+        .irp reg1 x0, x15, x30, xzr
+	\op \reg1
+	.endr
+	.endr
+
+	.irp op gcsstr, gcssttr
+        .irp reg1 x0, x15, x30, xzr
+	.irp reg2 x1, x16, sp
+	\op \reg1, \reg2
+	.endr
+	.endr
+	.endr
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 004df9ec1eb59bb60c821a96ce8f2960b76a9a7c..fc6a01aefd6f957ceb4f1578d09977321ff270b6 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -161,6 +161,8 @@  enum aarch64_feature_bit {
   AARCH64_FEATURE_V8_9A,
   /* Check Feature Status Extension.  */
   AARCH64_FEATURE_CHK,
+  /* Guarded Control Stack.  */
+  AARCH64_FEATURE_GCS,
   /* SME2.  */
   AARCH64_FEATURE_SME2,
   DUMMY1,
@@ -897,6 +899,7 @@  enum aarch64_insn_class
   dotproduct,
   bfloat16,
   cssc,
+  gcs,
 };
 
 /* Opcode enumerators.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 8f4bfc3f2d8a2cc64a72320cb4882d35c66b208e..f281fd55070da59f3ce598115b9ab701fd754deb 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2574,6 +2574,8 @@  static const aarch64_feature_set aarch64_feature_cssc =
   AARCH64_FEATURE (CSSC);
 static const aarch64_feature_set aarch64_feature_chk =
   AARCH64_FEATURE (CHK);
+static const aarch64_feature_set aarch64_feature_gcs =
+  AARCH64_FEATURE (GCS);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -2633,6 +2635,7 @@  static const aarch64_feature_set aarch64_feature_chk =
 #define HBC	  &aarch64_feature_hbc
 #define CSSC	  &aarch64_feature_cssc
 #define CHK	  &aarch64_feature_chk
+#define GCS	  &aarch64_feature_gcs
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2782,6 +2785,8 @@  static const aarch64_feature_set aarch64_feature_chk =
   { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define CHK_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \
   { NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \
+  { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL }
 
 #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
   MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -4141,6 +4146,16 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0),
   CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
   SB_INSN ("sb", 0xd50330ff, 0xffffffff, ic_system, OP0 (), {}, 0),
+  GCS_INSN ("gcspushx", 0xd508779f, 0xffffffff, OP0 (), {}, 0),
+  GCS_INSN ("gcspopx", 0xd50877df, 0xffffffff, OP0 (), {}, 0),
+  GCS_INSN ("gcspopcx", 0xd50877bf, 0xffffffff, OP0 (), {}, 0),
+  GCS_INSN ("gcsss1", 0xd50b7740, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
+  GCS_INSN ("gcspushm", 0xd50b7700, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
+  GCS_INSN ("gcsss2", 0xd52b7760, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
+  GCS_INSN ("gcspopm", 0xd52b773f, 0xffffffff, OP0 (), {}, 0),
+  GCS_INSN ("gcspopm", 0xd52b7720, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
+  GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
+  GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
   CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)),
   CORE_INSN ("at",  0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS),
   CORE_INSN ("dc",  0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),