diff mbox series

Add AMD znver5 processor support

Message ID DM6PR12MB479500B6E1D54C8C60A7B454E394A@DM6PR12MB4795.namprd12.prod.outlook.com
State New
Headers
Series Add AMD znver5 processor support |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Joshi, Tejas Sanjay Dec. 22, 2023, 7:12 a.m. UTC 
  [Public]

Hello,

PFA the patch for AMD znver5 processor enablement. The patch adds the following changes:

        * New AMD znver5 processor support:
           In addition to znver4 features, the architecture adds the following features:
                * AVX_VNNI, MOVDIRI, MOVDIR64B, AVX512_VP2INTERSECT, PREFETCHI
        * New test files added:
                * arch-15.s: New ISAs supported under the arch.
                * x86-64-arch-5.s: x86-64 version of the test.

Make check passes on x86-64. Good to submit in trunk?

ChangeLog:

    2023-11-29  Tejas Joshi <TejasSanjay.Joshi@amd.com>

    gas/

            * config/tc-i386.c (cpu_arch): Add znver5 ARCH.
            * doc/c-i386.texi: Add znver5.
            * testsuite/gas/i386/arch-15.d: New.
            * testsuite/gas/i386/arch-15.s: Likewise.
            * testsuite/gas/i386/arch-15-znver5.d: Likewise.
            * testsuite/gas/i386/i386.exp: Add new znver5 test cases.
            * testsuite/gas/i386/x86-64.exp: Likewise.
            * testsuite/gas/i386/x86-64-arch-5.d: Likewise.
            * testsuite/gas/i386/x86-64-arch-5.s: Likewise.
            * testsuite/gas/i386/x86-64-arch-5-znver5.d: Likewise.

    opcodes/

            * i386-gen.c (isa_dependencies): Add ZNVER5 dependencies.
            * i386-init.h: Re-generated.

--
--
2.34.1

Comments

Jan Beulich Dec. 22, 2023, 11:15 a.m. UTC | #1 
On 22.12.2023 08:12, Joshi, Tejas Sanjay wrote:
> PFA the patch for AMD znver5 processor enablement. The patch adds the following changes:
> 
>         * New AMD znver5 processor support:
>            In addition to znver4 features, the architecture adds the following features:
>                 * AVX_VNNI, MOVDIRI, MOVDIR64B, AVX512_VP2INTERSECT, PREFETCHI
>         * New test files added:
>                 * arch-15.s: New ISAs supported under the arch.
>                 * x86-64-arch-5.s: x86-64 version of the test.
> 
> Make check passes on x86-64. Good to submit in trunk?

Looks okay, so yes.

Jan
Joshi, Tejas Sanjay Dec. 26, 2023, 3:29 a.m. UTC | #2 
[Public]

Hello,

> Looks okay, so yes.

Thanks for the review! Can you please commit on my behalf?

Regards,
Tejas
Jan Beulich Jan. 4, 2024, 8:19 a.m. UTC | #3 
On 26.12.2023 04:29, Joshi, Tejas Sanjay wrote:
> Thanks for the review! Can you please commit on my behalf?

Sure, but then please re-base over recent changes and submit a v2.

Jan
Joshi, Tejas Sanjay Jan. 4, 2024, 9:30 a.m. UTC | #4 
[Public]

Hello,

> Sure, but then please re-base over recent changes and submit a v2.

Please find the patch attached here, rebased on top of recent changes, no conflicts.

Thanks and Regards,
Tejas
Jan Beulich Jan. 5, 2024, 8:29 a.m. UTC | #5 
On 04.01.2024 10:30, Joshi, Tejas Sanjay wrote:
> [Public]
> 
> Hello,
> 
>> Sure, but then please re-base over recent changes and submit a v2.
> 
> Please find the patch attached here, rebased on top of recent changes, no conflicts.

Pushed.

Jan
Nick Clifton Jan. 5, 2024, 9:35 a.m. UTC | #6 
Hi Jan, Hi Joshi,

   Two new failures in the gas testsuite for PE based x86_64
   toolchains has just appeared:

FAIL: x86-64 arch 5
FAIL: x86-64 arch 5 (znver5)

   It looks like a simple regexp problem:

regexp_diff match failure
regexp "^[ 	]*[a-f0-9]+:[ 	]*0f 18 3d 78 56 34 12[ 	]*prefetchit0 0x12345678\(%rip\)        # 0x[0-9a-f]+$"
line   "  15:	0f 18 3d 78 56 34 12 	prefetchit0 0x12345678(%rip)        # 12345694 <.text+0x12345694>"

   Could you take a look please ?

Cheers
   Nick

PS.  Seen with toolchains configured as x86_64-pc-cygwin,
   x86_64-pc-mingw64 and x86_64-w64-mingw32
Jan Beulich Jan. 5, 2024, 11:11 a.m. UTC | #7 
On 05.01.2024 10:35, Nick Clifton wrote:
> Hi Jan, Hi Joshi,
> 
>    Two new failures in the gas testsuite for PE based x86_64
>    toolchains has just appeared:
> 
> FAIL: x86-64 arch 5
> FAIL: x86-64 arch 5 (znver5)
> 
>    It looks like a simple regexp problem:
> 
> regexp_diff match failure
> regexp "^[ 	]*[a-f0-9]+:[ 	]*0f 18 3d 78 56 34 12[ 	]*prefetchit0 0x12345678\(%rip\)        # 0x[0-9a-f]+$"
> line   "  15:	0f 18 3d 78 56 34 12 	prefetchit0 0x12345678(%rip)        # 12345694 <.text+0x12345694>"
> 
>    Could you take a look please ?

Correction pushed. I'm puzzled though that this test isn't run when
building a 64-bit capable assembler for 32-bit Cygwin (I first meant
to reply: Cannot reproduce), despite --help output mentioning the
necessary --64 command line option. That looks to be something in
need of (further) improvement.

Jan
diff mbox series

Patch

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index c84374a08d1..7053655281a 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1007,6 +1007,7 @@  static const arch_entry cpu_arch[] =
   ARCH (znver2, ZNVER, ZNVER2, false),
   ARCH (znver3, ZNVER, ZNVER3, false),
   ARCH (znver4, ZNVER, ZNVER4, false),
+  ARCH (znver5, ZNVER, ZNVER5, false),
   ARCH (btver1, BT, BTVER1, false),
   ARCH (btver2, BT, BTVER2, false),

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 03ee980bef7..cb378a89994 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -125,6 +125,7 @@  processor names are recognized:
 @code{znver2},
 @code{znver3},
 @code{znver4},
+@code{znver5},
 @code{btver1},
 @code{btver2},
 @code{generic32} and
@@ -1627,7 +1628,8 @@  supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
-@item @samp{znver4} @tab @samp{btver1} @tab @samp{btver2} @tab @samp{generic32}
+@item @samp{znver4} @tab @samp{znver5} @tab @samp{btver1} @tab @samp{btver2}
+@item @samp{generic32}
 @item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
diff --git a/gas/testsuite/gas/i386/arch-15-znver5.d b/gas/testsuite/gas/i386/arch-15-znver5.d
new file mode 100644
index 00000000000..378daa655dd
--- /dev/null
+++ b/gas/testsuite/gas/i386/arch-15-znver5.d
@@ -0,0 +1,5 @@ 
+#source: arch-15.s
+#as: -march=znver5
+#objdump: -dw
+#name: i386 arch 15 (znver5)
+#dump: arch-15.d
diff --git a/gas/testsuite/gas/i386/arch-15.d b/gas/testsuite/gas/i386/arch-15.d
new file mode 100644
index 00000000000..33de12a5dff
--- /dev/null
+++ b/gas/testsuite/gas/i386/arch-15.d
@@ -0,0 +1,13 @@ 
+#objdump: -dw
+#name: i386 arch 15
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[      ]*[a-f0-9]+:[   ]*c4 e2 59 50 d2[       ]*\{vex\} vpdpbusd %xmm2,%xmm4,%xmm2
+[      ]*[a-f0-9]+:[   ]*0f 38 f9 01[  ]*movdiri %eax,\(%ecx\)
+[      ]*[a-f0-9]+:[   ]*66 0f 38 f8 01[       ]*movdir64b \(%ecx\),%eax
+[      ]*[a-f0-9]+:[   ]*62 f2 6f 48 68 d9[    ]*vp2intersectd %zmm1,%zmm2,%k3
+#pass
diff --git a/gas/testsuite/gas/i386/arch-15.s b/gas/testsuite/gas/i386/arch-15.s
new file mode 100644
index 00000000000..e3b70e5743b
--- /dev/null
+++ b/gas/testsuite/gas/i386/arch-15.s
@@ -0,0 +1,7 @@ 
+# Test -march=
+       .text
+
+    {vex} vpdpbusd %xmm2, %xmm4, %xmm2    #AVX_VNNI
+    movdiri %eax, (%ecx)            #MOVDIRI
+    movdir64b (%ecx), %eax          #MOVDIR64B
+    vp2intersectd %zmm1, %zmm2, %k3 #AVX512_VP2INTERSECT
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3917be6be70..3aba45ef8f0 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -204,6 +204,7 @@  if [gas_32_check] then {
     run_dump_test "arch-13-znver2"
     run_dump_test "arch-14-znver3"
     run_dump_test "arch-14-znver4"
+    run_dump_test "arch-15-znver5"
     run_dump_test "arch-10-btver1"
     run_dump_test "arch-10-btver2"
     run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al"
@@ -217,6 +218,7 @@  if [gas_32_check] then {
     run_dump_test "arch-13"
     run_dump_test "arch-14"
     run_dump_test "arch-14-1"
+    run_dump_test "arch-15"
     run_list_test "arch-dflt" "-march=generic32 -al"
     run_list_test "arch-stk" "-march=generic32 -al"
     run_dump_test "8087"
diff --git a/gas/testsuite/gas/i386/x86-64-arch-5-znver5.d b/gas/testsuite/gas/i386/x86-64-arch-5-znver5.d
new file mode 100644
index 00000000000..f7d6342fb7e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-arch-5-znver5.d
@@ -0,0 +1,5 @@ 
+#source: x86-64-arch-5.s
+#as: -march=znver5
+#objdump: -dw
+#name: x86-64 arch 5 (znver5)
+#dump: x86-64-arch-5.d
diff --git a/gas/testsuite/gas/i386/x86-64-arch-5.d b/gas/testsuite/gas/i386/x86-64-arch-5.d
new file mode 100644
index 00000000000..dfcdc857cce
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-arch-5.d
@@ -0,0 +1,14 @@ 
+#objdump: -dw
+#name: x86-64 arch 5
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[      ]*[a-f0-9]+:[   ]*c4 c2 59 50 d4[       ]*\{vex\} vpdpbusd %xmm12,%xmm4,%xmm2
+[      ]*[a-f0-9]+:[   ]*48 0f 38 f9 01[       ]*movdiri %rax,\(%rcx\)
+[      ]*[a-f0-9]+:[   ]*66 0f 38 f8 01[       ]*movdir64b \(%rcx\),%rax
+[      ]*[a-f0-9]+:[   ]*62 f2 6f 48 68 d9[    ]*vp2intersectd %zmm1,%zmm2,%k3
+[      ]*[a-f0-9]+:[   ]*0f 18 3d 78 56 34 12[         ]*prefetchit0 0x12345678\(%rip\)        # 0x[0-9a-f]+
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-arch-5.s b/gas/testsuite/gas/i386/x86-64-arch-5.s
new file mode 100644
index 00000000000..f359f4ed27b
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-arch-5.s
@@ -0,0 +1,8 @@ 
+# Test -march=
+       .text
+
+    {vex} vpdpbusd %xmm12, %xmm4, %xmm2     #AVX_VNNI
+    movdiri %rax, (%rcx)                    #MOVDIRI
+    movdir64b (%rcx), %rax                  #MOVDIR64B
+    vp2intersectd %zmm1, %zmm2, %k3         #AVX512_VP2INTERSECT
+    prefetchit0 0x12345678(%rip)            #prefetchi
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index a7f5547017f..614e2c7601a 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -174,6 +174,7 @@  run_dump_test "x86-64-arch-3"
 run_dump_test "x86-64-arch-4"
 run_dump_test "x86-64-arch-4-1"
 run_dump_test "rmpquery"
+run_dump_test "x86-64-arch-5"
 run_dump_test "x86-64-arch-2-lzcnt"
 run_dump_test "x86-64-arch-2-prefetchw"
 run_dump_test "x86-64-arch-2-bdver1"
@@ -184,6 +185,7 @@  run_dump_test "x86-64-arch-3-znver1"
 run_dump_test "x86-64-arch-3-znver2"
 run_dump_test "x86-64-arch-4-znver3"
 run_dump_test "x86-64-arch-4-znver4"
+run_dump_test "x86-64-arch-5-znver5"
 run_dump_test "x86-64-arch-2-btver1"
 run_dump_test "x86-64-arch-2-btver2"
 run_list_test "x86-64-arch-2-1" "-march=generic64 -I${srcdir}/$subdir -al"
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 110a8371bd0..3b0b435bac2 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -94,6 +94,8 @@  static const dependency isa_dependencies[] =
     "ZNVER2|INVLPGB|TLBSYNC|VAES|VPCLMULQDQ|INVPCID|SNP|OSPKE" },
   { "ZNVER4",
     "ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" },
+  { "ZNVER5",
+    "ZNVER4|AVX_VNNI|MOVDIRI|MOVDIR64B|AVX512_VP2INTERSECT|PREFETCHI" },
   { "BTVER1",
     "GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
   { "BTVER2",