diff mbox series

[REVIEW,ONLY,v2] UNRATIFIED RISC-V: Add support for the 'Zimop' extension

Message ID CAP9EGj7a_DCDgKVqqg7jLzGZ-+NgS2nyYTedxv24N-k3covxCw@mail.gmail.com
State New
Headers
Series [REVIEW,ONLY,v2] UNRATIFIED RISC-V: Add support for the 'Zimop' extension |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Lyut Nersisyan Dec. 7, 2023, 3:02 p.m. UTC 
  [DO NOT MERGE]
Until this extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream. This commit uses
unratified version 0.1 as in the documentation file name (instead of
possible 1.0 after ratification).

The 'Zimop' extension provides may be operations instructions. This commit
adds instruction and extension support for this extension.

This is based on the draft specification:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>

bfd/ChangeLog:

        * elfxx-riscv.c
        (riscv_supported_std_z_ext): Add 'Zimop' to the supported list.
        (riscv_multi_subset_supports, riscv_multi_subset_supports_ext): Add
handling for new instruction class.

gas/ChangeLog:

        * testsuite/gas/riscv/zimop.s: New test.
        * testsuite/gas/riscv/zimop-32.d: Likewise.
        * testsuite/gas/riscv/zimop-64.d: Likewise.

include/ChangeLog:

        * opcode/riscv-opc.h (MATCH_MOP_R_[0...31], MASK_MOP_R,
MATCH_MOP_RR_[0...7], MASK_MOP_RR): New.
        * opcode/riscv.h (enum riscv_insn_class): Add new instruction class
INSN_CLASS_ZIMOP.

opcodes/ChangeLog:

        * riscv-opc.c (riscv_opcodes): Add instructions from the 'Zimop'
extension.
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 567631e7d96..46417dd91c9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1268,6 +1268,7 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zimop",		ISA_SPEC_CLASS_DRAFT,		0, 1,  0 },
   {"zfa",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2430,6 +2431,8 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "a");
     case INSN_CLASS_ZAWRS:
       return riscv_subset_supports (rps, "zawrs");
+    case INSN_CLASS_ZIMOP:
+      return riscv_subset_supports (rps, "zimop");
     case INSN_CLASS_F:
       return riscv_subset_supports (rps, "f");
     case INSN_CLASS_D:
@@ -2648,6 +2651,8 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "a";
     case INSN_CLASS_ZAWRS:
       return "zawrs";
+    case INSN_CLASS_ZIMOP:
+      return "zimop";
     case INSN_CLASS_F:
       return "f";
     case INSN_CLASS_D:
diff --git a/gas/testsuite/gas/riscv/zimop-32.d b/gas/testsuite/gas/riscv/zimop-32.d
new file mode 100644
index 00000000000..9420a4f1f38
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zimop-32.d
@@ -0,0 +1,12 @@ 
+#as: -march=rv32gc_zimop
+#source: zimop.s
+#objdump: -d
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[	 ]+0:[	 ]+81c5c573[	 ]+mop.r.0[	 ]+a0,a1
+[	 ]+4:[	 ]+ced64573[	 ]+mop.rr.7[	 ]+a0,a2,a3
diff --git a/gas/testsuite/gas/riscv/zimop-64.d b/gas/testsuite/gas/riscv/zimop-64.d
new file mode 100644
index 00000000000..1d6d6f9f8f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zimop-64.d
@@ -0,0 +1,12 @@ 
+#as: -march=rv64gc_zimop
+#source: zimop.s
+#objdump: -d
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[	 ]+0:[	 ]+81c5c573[	 ]+mop.r.0[	 ]+a0,a1
+[	 ]+4:[	 ]+ced64573[	 ]+mop.rr.7[	 ]+a0,a2,a3
diff --git a/gas/testsuite/gas/riscv/zimop.s b/gas/testsuite/gas/riscv/zimop.s
new file mode 100644
index 00000000000..2333a56715c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zimop.s
@@ -0,0 +1,3 @@ 
+target:
+       mop.r.0         a0, a1
+       mop.rr.7        a0, a2, a3
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1e417217b7d..cfe9fc7ca85 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2320,6 +2320,49 @@ 
 #define MASK_WRS_NTO 0xffffffff
 #define MATCH_WRS_STO 0x01d00073
 #define MASK_WRS_STO 0xffffffff
+/* Zimop instructions. */
+#define MATCH_MOP_R_0 0x81c04073
+#define MATCH_MOP_R_1 0x81d04073
+#define MATCH_MOP_R_2 0x81e04073
+#define MATCH_MOP_R_3 0x81f04073
+#define MATCH_MOP_R_4 0x85c04073
+#define MATCH_MOP_R_5 0x85d04073
+#define MATCH_MOP_R_6 0x85e04073
+#define MATCH_MOP_R_7 0x85f04073
+#define MATCH_MOP_R_8 0x89c04073
+#define MATCH_MOP_R_9 0x89d04073
+#define MATCH_MOP_R_10 0x89e04073
+#define MATCH_MOP_R_11 0x89f04073
+#define MATCH_MOP_R_12 0x8dc04073
+#define MATCH_MOP_R_13 0x8dd04073
+#define MATCH_MOP_R_14 0x8de04073
+#define MATCH_MOP_R_15 0x8df04073
+#define MATCH_MOP_R_16 0xc1c04073
+#define MATCH_MOP_R_17 0xc1d04073
+#define MATCH_MOP_R_18 0xc1e04073
+#define MATCH_MOP_R_19 0xc1f04073
+#define MATCH_MOP_R_20 0xc5c04073
+#define MATCH_MOP_R_21 0xc5d04073
+#define MATCH_MOP_R_22 0xc5e04073
+#define MATCH_MOP_R_23 0xc5f04073
+#define MATCH_MOP_R_24 0xc9c04073
+#define MATCH_MOP_R_25 0xc9d04073
+#define MATCH_MOP_R_26 0xc9e04073
+#define MATCH_MOP_R_27 0xc9f04073
+#define MATCH_MOP_R_28 0xcdc04073
+#define MATCH_MOP_R_29 0xcdd04073
+#define MATCH_MOP_R_30 0xcde04073
+#define MATCH_MOP_R_31 0xcdf04073
+#define MASK_MOP_R 0xfff0707f
+#define MATCH_MOP_RR_0 0x82004073
+#define MATCH_MOP_RR_1 0x86004073
+#define MATCH_MOP_RR_2 0x8a004073
+#define MATCH_MOP_RR_3 0x8e004073
+#define MATCH_MOP_RR_4 0xc2004073
+#define MATCH_MOP_RR_5 0xc6004073
+#define MATCH_MOP_RR_6 0xca004073
+#define MATCH_MOP_RR_7 0xce004073
+#define MASK_MOP_RR 0xfe00707f
 /* Vendor-specific (CORE-V) Xcvmac instructions.  */
 #define MATCH_CV_MAC       0x9000302b
 #define MASK_CV_MAC        0xfe00707f
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 25486869606..991f8097a45 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -407,6 +407,7 @@  enum riscv_insn_class
   INSN_CLASS_ZIHINTPAUSE,
   INSN_CLASS_ZMMUL,
   INSN_CLASS_ZAWRS,
+  INSN_CLASS_ZIMOP,
   INSN_CLASS_F_INX,
   INSN_CLASS_D_INX,
   INSN_CLASS_Q_INX,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index bf19978e025..041fff03202 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -988,6 +988,48 @@  const struct riscv_opcode riscv_opcodes[] =
 {"wrs.nto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 },
 {"wrs.sto",    0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 },
 
+/* Zimop instructions.  */
+{"mop.r.0",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.1",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.2",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_2, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.3",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_3, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.4",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_4, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.5",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_5, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.6",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_6, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.7",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_7, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.8",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_8, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.9",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_9, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.10",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_10, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.11",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_11, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.12",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_12, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.13",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_13, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.14",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_14, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.15",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_15, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.16",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_16, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.17",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_17, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.18",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_18, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.19",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_19, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.20",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_20, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.21",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_21, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.22",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_22, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.23",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_23, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.24",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_24, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.25",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_25, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.26",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_26, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.27",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_27, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.28",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_28, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.29",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_29, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.30",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_30, MASK_MOP_R, match_opcode, 0 },
+{"mop.r.31",    0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_31, MASK_MOP_R, match_opcode, 0 },
+{"mop.rr.0",    0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_0, MASK_MOP_RR, match_opcode, 0 },
+{"mop.rr.1",    0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_1, MASK_MOP_RR, match_opcode, 0 },
+{"mop.rr.2",    0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_2, MASK_MOP_RR, match_opcode, 0 },
+{"mop.rr.3",    0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_3, MASK_MOP_RR, match_opcode, 0 },
+{"mop.rr.4",    0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_4, MASK_MOP_RR, match_opcode, 0 },
+{"mop.rr.5",    0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_5, MASK_MOP_RR, match_opcode, 0 },
+{"mop.rr.6",    0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_6, MASK_MOP_RR, match_opcode, 0 },
+{"mop.rr.7",    0, INSN_CLASS_ZIMOP, "d,s,t", MATCH_MOP_RR_7, MASK_MOP_RR, match_opcode, 0 },
+
 /* Zfa instructions.  */
 {"fli.s",       0, INSN_CLASS_ZFA,         "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 },
 {"fli.d",       0, INSN_CLASS_D_AND_ZFA,   "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 },