diff mbox series

[2/5] aarch64: Add features to the Statistical Profiling Extension.

Message ID 8dcf129a-88c8-198a-adbb-4da2e6403063@arm.com
State Committed
Headers
Series [1/5] aarch64: Add SLC target for PRFM instruction. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply

Commit Message

Srinath Parvathaneni Nov. 16, 2023, 11:28 a.m. UTC 
  Hi,

This patch adds features to the Statistical Profiling Extension,
identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which
are enabled by default from Armv9.4-A.

Also adds support for system register "pmsdsfr_el1".

Regression tested for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.

Comments

Richard Earnshaw Nov. 16, 2023, 11:58 a.m. UTC | #1 
On 16/11/2023 11:28, Srinath Parvathaneni wrote:
> Hi,
> 
> This patch adds features to the Statistical Profiling Extension,
> identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which
> are enabled by default from Armv9.4-A.
> 
> Also adds support for system register "pmsdsfr_el1".
> 
> Regression tested for aarch64-none-elf target and found no regressions.
> 
> Ok for binutils-master?
> 
> Regards,
> Srinath.

OK.
diff mbox series

Patch

diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..2471b6b52c31183b0aef6f089fcc3ce22089ee98
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.d
@@ -0,0 +1,3 @@ 
+#as: -march=armv8.8-a
+#source: armv8_9-a-sysregs.s
+#error_output: armv8_9-a-sysregs-bad.l
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..48c55680aa07618cd1f0c165435533fe4dd31e41
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
@@ -0,0 +1,3 @@ 
+.*: Assembler messages:
+.*: Error: selected processor does not support system register name 'pmsdsfr_el1'
+.*: Error: selected processor does not support system register name 'pmsdsfr_el1'
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
new file mode 100644
index 0000000000000000000000000000000000000000..d4cb769fdf63aaa89ac4c410982cd20ac12bbd4d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
@@ -0,0 +1,10 @@ 
+#as: -march=armv8.9-a
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d53c9a83 	mrs	x3, pmsdsfr_el1
+.*:	d51c9a83 	msr	pmsdsfr_el1, x3
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
new file mode 100644
index 0000000000000000000000000000000000000000..4200d7ce60ed21822731a836214bb44aeeea57ac
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
@@ -0,0 +1,2 @@ 
+	mrs x3, PMSDSFR_EL1
+	msr PMSDSFR_EL1, x3
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6be2885c78fbd5213220d22ce3218c39bb03916f..881a4211eabfad2cc4442efc78eb37c06d26973d 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -163,6 +163,12 @@  enum aarch64_feature_bit {
   AARCH64_FEATURE_CHK,
   /* Guarded Control Stack.  */
   AARCH64_FEATURE_GCS,
+  /* SPE Call Return branch records.  */
+  AARCH64_FEATURE_SPE_CRR,
+  /* SPE Filter by data source.  */
+  AARCH64_FEATURE_SPE_FDS,
+  /* Additional SPE events.  */
+  AARCH64_FEATURE_SPEv1p4,
   /* SME2.  */
   AARCH64_FEATURE_SME2,
   /* Translation Hardening Extension.  */
@@ -224,7 +230,10 @@  enum aarch64_feature_bit {
 #define AARCH64_ARCH_V8_8A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_8A)	\
 					 | AARCH64_FEATBIT (X, MOPS)	\
 					 | AARCH64_FEATBIT (X, HBC))
-#define AARCH64_ARCH_V8_9A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_9A))
+#define AARCH64_ARCH_V8_9A_FEATURES(X)	(AARCH64_FEATBIT (X, V8_9A)	\
+					 | AARCH64_FEATBIT (X, SPEv1p4) \
+					 | AARCH64_FEATBIT (X, SPE_CRR)	\
+					 | AARCH64_FEATBIT (X, SPE_FDS))
 
 #define AARCH64_ARCH_V9A_FEATURES(X)	(AARCH64_FEATBIT (X, V9A)	\
 					 | AARCH64_FEATBIT (X, F16)	\
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 96bdadb0b0fe56f25ec2c210264900d6936db06b..aab2c7264cab0b4ca34ab8135194abd0126b7430 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -676,6 +676,7 @@ 
   SYSREG ("pmscr_el1",		CPENC (3,0,9,9,0),	F_ARCHEXT,		AARCH64_FEATURE (PROFILE))
   SYSREG ("pmscr_el12",		CPENC (3,5,9,9,0),	F_ARCHEXT,		AARCH64_FEATURE (PROFILE))
   SYSREG ("pmscr_el2",		CPENC (3,4,9,9,0),	F_ARCHEXT,		AARCH64_FEATURE (PROFILE))
+  SYSREG ("pmsdsfr_el1",	CPENC (3,4,9,10,4),	F_ARCHEXT,		AARCH64_FEATURE (SPE_FDS))
   SYSREG ("pmselr_el0",		CPENC (3,3,9,12,5),	0,			AARCH64_NO_FEATURES)
   SYSREG ("pmsevfr_el1",	CPENC (3,0,9,9,5),	F_ARCHEXT,		AARCH64_FEATURE (PROFILE))
   SYSREG ("pmsfcr_el1",		CPENC (3,0,9,9,4),	F_ARCHEXT,		AARCH64_FEATURE (PROFILE))