diff mbox series

[1/2] opcodes/riscv: add styling support to print_reg_list

Message ID 7d81dac4693d176577d59a23b2348ebadcde8e3c.1717589992.git.aburgess@redhat.com
State New
Headers
Series RISC-V styled disassembler output fixes |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Andrew Burgess June 5, 2024, 12:21 p.m. UTC 
  I noticed that some unstyled output had crept into the risc-v
disassembler in this commit:

  commit 9132c8152b899a1683bc886f8ba76bedadb48aa1
  Date:   Tue Feb 27 11:48:11 2024 +0800

      RISC-V: Support Zcmp push/pop instructions.

this commit adds styling support.  The risc-v disassembler is now once
again, fully styled.
---
 opcodes/riscv-dis.c | 51 ++++++++++++++++++++++++++++++++-------------
 1 file changed, 37 insertions(+), 14 deletions(-)
diff mbox series

Patch

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index e6596c47423..d0d74c0a05a 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -223,26 +223,49 @@  print_reg_list (disassemble_info *info, insn_t l)
   bool numeric = riscv_gpr_names == riscv_gpr_names_numeric;
   unsigned reg_list = (int)EXTRACT_OPERAND (REG_LIST, l);
   unsigned r_start = numeric ? X_S2 : X_S0;
-  info->fprintf_func (info->stream, "%s", riscv_gpr_names[X_RA]);
+  info->fprintf_styled_func (info->stream, dis_style_register,
+			     "%s", riscv_gpr_names[X_RA]);
 
   if (reg_list == 5)
-    info->fprintf_func (info->stream, ",%s",
-			riscv_gpr_names[X_S0]);
+    {
+      info->fprintf_styled_func (info->stream, dis_style_text, ",");
+      info->fprintf_styled_func (info->stream, dis_style_register,
+				 "%s", riscv_gpr_names[X_S0]);
+    }
   else if (reg_list == 6 || (numeric && reg_list > 6))
-    info->fprintf_func (info->stream, ",%s-%s",
-			riscv_gpr_names[X_S0],
-			riscv_gpr_names[X_S1]);
+    {
+      info->fprintf_styled_func (info->stream, dis_style_text, ",");
+      info->fprintf_styled_func (info->stream, dis_style_register,
+				 "%s", riscv_gpr_names[X_S0]);
+      info->fprintf_styled_func (info->stream, dis_style_text, "-");
+      info->fprintf_styled_func (info->stream, dis_style_register,
+				 "%s", riscv_gpr_names[X_S1]);
+    }
+
   if (reg_list == 15)
-    info->fprintf_func (info->stream, ",%s-%s",
-			riscv_gpr_names[r_start],
-			riscv_gpr_names[X_S11]);
+    {
+      info->fprintf_styled_func (info->stream, dis_style_text, ",");
+      info->fprintf_styled_func (info->stream, dis_style_register,
+				 "%s", riscv_gpr_names[r_start]);
+      info->fprintf_styled_func (info->stream, dis_style_text, "-");
+      info->fprintf_styled_func (info->stream, dis_style_register,
+				 "%s", riscv_gpr_names[X_S11]);
+    }
   else if (reg_list == 7 && numeric)
-    info->fprintf_func (info->stream, ",%s",
-			riscv_gpr_names[X_S2]);
+    {
+      info->fprintf_styled_func (info->stream, dis_style_text, ",");
+      info->fprintf_styled_func (info->stream, dis_style_register,
+				 "%s", riscv_gpr_names[X_S2]);
+    }
   else if (reg_list > 6)
-    info->fprintf_func (info->stream, ",%s-%s",
-			riscv_gpr_names[r_start],
-			riscv_gpr_names[reg_list + 11]);
+    {
+      info->fprintf_styled_func (info->stream, dis_style_text, ",");
+      info->fprintf_styled_func (info->stream, dis_style_register,
+				 "%s", riscv_gpr_names[r_start]);
+      info->fprintf_styled_func (info->stream, dis_style_text, "-");
+      info->fprintf_styled_func (info->stream, dis_style_register,
+				 "%s", riscv_gpr_names[reg_list + 11]);
+    }
 }
 
 /* Get Zcmp sp adjustment immediate.  */