@@ -6805,10 +6805,14 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zn_5_INDEX:
case AARCH64_OPND_SME_Zm_INDEX1:
case AARCH64_OPND_SME_Zm_INDEX2:
+ case AARCH64_OPND_SME_Zm_INDEX2_3:
case AARCH64_OPND_SME_Zm_INDEX3_1:
case AARCH64_OPND_SME_Zm_INDEX3_2:
+ case AARCH64_OPND_SME_Zm_INDEX3_3:
case AARCH64_OPND_SME_Zm_INDEX3_10:
case AARCH64_OPND_SME_Zm_INDEX4_1:
+ case AARCH64_OPND_SME_Zm_INDEX4_2:
+ case AARCH64_OPND_SME_Zm_INDEX4_3:
case AARCH64_OPND_SME_Zm_INDEX4_10:
case AARCH64_OPND_SME_Zn_INDEX1_16:
case AARCH64_OPND_SME_Zn_INDEX2_15:
@@ -8019,6 +8023,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
break;
+ case AARCH64_OPND_SME_ZAda_1b:
case AARCH64_OPND_SME_ZAda_2b:
case AARCH64_OPND_SME_ZAda_3b:
reg = parse_reg_with_qual (&str, REG_TYPE_ZAT, &qualifier, 0);
@@ -10568,6 +10573,10 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (SSVE_FP8FMA)},
{"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2),
AARCH64_FEATURE (SSVE_FP8DOT4)},
+ {"sme-f8f32", AARCH64_FEATURE (SME_F8F32),
+ AARCH64_FEATURES (2, FP8, SME2)},
+ {"sme-f8f16", AARCH64_FEATURE (SME_F8F16),
+ AARCH64_FEATURE (SME_F8F32)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@@ -263,6 +263,10 @@ automatically cause those extensions to be disabled.
@tab Enable the SM3 and SM4 cryptographic extensions.
@item @code{sme} @tab @code{sve2}, @code{bf16}
@tab Enable the Scalable Matrix Extension.
+@item @code{sme-f8f16} @tab @code{sme-f8f32}
+ @tab Enable the SME F8F16 Extension.
+@item @code{sme-f8f32} @tab @code{sme2}, @code{fp8}
+ @tab Enable the SME F8F32 Extension.
@item @code{sme-f64f64} @tab @code{sme}
@tab Enable SME F64F64 Extension.
@item @code{sme-i16i64} @tab @code{sme}
new file mode 100644
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f16
+#error_output: fp8-sme-dot-illegal.l
new file mode 100644
@@ -0,0 +1,87 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:2: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:3: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:4: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]'
+[^:]*:5: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:6: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:7: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:9: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]'
+[^:]*:10: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^:]*:11: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:12: Error: register element index out of range 0 to 3 at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[4\]'
+[^:]*:13: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:14: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:15: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:17: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b'
+[^:]*:18: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:21: Error: expected a list of 4 registers at operand 2 -- `fdot za\.s\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b'
+[^:]*:23: Error: z0-z15 expected at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},z16\.b'
+[^:]*:24: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},z0\.b'
+[^:]*:25: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:26: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:27: Error: expected a list of 2 registers at operand 2 -- `fdot za\.s\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:29: Error: expected a list of 2 registers at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
+[^:]*:30: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
+[^:]*:31: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
+[^:]*:32: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:33: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:35: Error: expected a list of 4 registers at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
+[^:]*:36: Error: start register out of range at operand 3 -- `fdot za\.s\[w8,0\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
+[^:]*:37: Error: start register out of range at operand 2 -- `fdot za\.s\[w8,0\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
+[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.s\[w7,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:39: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.s\[w8,8\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:41: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:42: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:43: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:44: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[8\]'
+[^:]*:45: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:46: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:49: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z16\.b\[0\]'
+[^:]*:50: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^:]*:51: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:52: Error: register element index out of range 0 to 7 at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b\[8\]'
+[^:]*:53: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:54: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:55: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:57: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b'
+[^:]*:58: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b'
+[^:]*:59: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:60: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:61: Error: expected a list of 4 registers at operand 2 -- `fdot za\.h\[w8,0,VGx4\],{z0\.b-z1\.b},z0\.b'
+[^:]*:63: Error: z0-z15 expected at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},z16\.b'
+[^:]*:64: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},z0\.b'
+[^:]*:65: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:66: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:67: Error: expected a list of 2 registers at operand 2 -- `fdot za\.h\[w8,0,VGx2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:69: Error: expected a list of 2 registers at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
+[^:]*:70: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
+[^:]*:71: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
+[^:]*:72: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:73: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:75: Error: expected a list of 4 registers at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
+[^:]*:76: Error: start register out of range at operand 3 -- `fdot za\.h\[w8,0\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
+[^:]*:77: Error: start register out of range at operand 2 -- `fdot za\.h\[w8,0\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
+[^:]*:78: Error: expected a selection register in the range w8-w11 at operand 1 -- `fdot za\.h\[w7,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:79: Error: immediate offset out of range 0 to 7 at operand 1 -- `fdot za\.h\[w8,8\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:81: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.h\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:82: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.h\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:83: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdot za\.h\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:84: Error: start register out of range at operand 2 -- `fvdot za\.h\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:85: Error: z0-z15 expected at operand 3 -- `fvdot za\.h\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:86: Error: register element index out of range 0 to 7 at operand 3 -- `fvdot za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[8\]'
+[^:]*:88: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:89: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdotb za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:90: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdotb za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:91: Error: start register out of range at operand 2 -- `fvdotb za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:92: Error: z0-z15 expected at operand 3 -- `fvdotb za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:93: Error: register element index out of range 0 to 3 at operand 3 -- `fvdotb za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]'
+[^:]*:95: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w7,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:96: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdott za\.s\[w12,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:97: Error: immediate offset out of range 0 to 7 at operand 1 -- `fvdott za\.s\[w8,8\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:98: Error: start register out of range at operand 2 -- `fvdott za\.s\[w8,0\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:99: Error: z0-z15 expected at operand 3 -- `fvdott za\.s\[w8,0\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:100: Error: register element index out of range 0 to 3 at operand 3 -- `fvdott za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[4\]'
new file mode 100644
@@ -0,0 +1,100 @@
+fdot za.s[w8, 0], { z0.b-z1.b }, z16.b[0]
+fdot za.s[w8, 0], { z1.b-z2.b }, z0.b[0]
+fdot za.s[w8, 0, VGx2], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w8, 0], { z0.b-z1.b }, z0.b[4]
+fdot za.s[w8, 8], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w7, 0], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w12, 0], { z0.b-z1.b }, z0.b[0]
+
+fdot za.s[w8, 0], { z0.b-z3.b }, z16.b[0]
+fdot za.s[w8, 0], { z2.b-z5.b }, z0.b[0]
+fdot za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w8, 0], { z0.b-z3.b }, z0.b[4]
+fdot za.s[w8, 8], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w7, 0], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w12, 0], { z0.b-z3.b }, z0.b[0]
+
+fdot za.s[w8, 0], { z0.b-z1.b }, z16.b
+fdot za.s[w8, 8], { z0.b-z1.b }, z0.b
+fdot za.s[w7, 0], { z0.b-z1.b }, z0.b
+fdot za.s[w12, 0], { z0.b-z1.b }, z0.b
+fdot za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b
+
+fdot za.s[w8, 0], { z0.b-z3.b }, z16.b
+fdot za.s[w8, 8], { z0.b-z3.b }, z0.b
+fdot za.s[w7, 0], { z0.b-z3.b }, z0.b
+fdot za.s[w12, 0], { z0.b-z3.b }, z0.b
+fdot za.s[w8, 0, VGx2], { z0.b-z3.b }, z0.b
+
+fdot za.s[w8, 0], { z0.b-z1.b }, { z0.b-z3.b}
+fdot za.s[w8, 0], { z0.b-z1.b }, { z1.b-z2.b}
+fdot za.s[w8, 0], { z1.b-z2.b }, { z0.b-z1.b}
+fdot za.s[w7, 0], { z0.b-z1.b }, { z0.b-z1.b}
+fdot za.s[w8, 8], { z0.b-z1.b }, { z0.b-z1.b}
+
+fdot za.s[w8, 0], { z0.b-z3.b }, { z0.b-z1.b}
+fdot za.s[w8, 0], { z0.b-z3.b }, { z2.b-z5.b}
+fdot za.s[w8, 0], { z2.b-z5.b }, { z0.b-z3.b}
+fdot za.s[w7, 0], { z0.b-z3.b }, { z0.b-z3.b}
+fdot za.s[w8, 8], { z0.b-z3.b }, { z0.b-z3.b}
+
+fdot za.h[w8, 0], { z0.b-z1.b }, z16.b[0]
+fdot za.h[w8, 0], { z1.b-z2.b }, z0.b[0]
+fdot za.h[w8, 0, VGx2], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w8, 0], { z0.b-z1.b }, z0.b[8]
+fdot za.h[w8, 8], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w7, 0], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w12, 0], { z0.b-z1.b }, z0.b[0]
+
+fdot za.h[w8, 0], { z0.b-z3.b }, z16.b[0]
+fdot za.h[w8, 0], { z2.b-z5.b }, z0.b[0]
+fdot za.h[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[8]
+fdot za.h[w8, 8], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w7, 0], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w12, 0], { z0.b-z3.b }, z0.b[0]
+
+fdot za.h[w8, 0], { z0.b-z1.b }, z16.b
+fdot za.h[w8, 8], { z0.b-z1.b }, z0.b
+fdot za.h[w7, 0], { z0.b-z1.b }, z0.b
+fdot za.h[w12, 0], { z0.b-z1.b }, z0.b
+fdot za.h[w8, 0, VGx4], { z0.b-z1.b }, z0.b
+
+fdot za.h[w8, 0], { z0.b-z3.b }, z16.b
+fdot za.h[w8, 8], { z0.b-z3.b }, z0.b
+fdot za.h[w7, 0], { z0.b-z3.b }, z0.b
+fdot za.h[w12, 0], { z0.b-z3.b }, z0.b
+fdot za.h[w8, 0, VGx2], { z0.b-z3.b }, z0.b
+
+fdot za.h[w8, 0], { z0.b-z1.b }, { z0.b-z3.b}
+fdot za.h[w8, 0], { z0.b-z1.b }, { z1.b-z2.b}
+fdot za.h[w8, 0], { z1.b-z2.b }, { z0.b-z1.b}
+fdot za.h[w7, 0], { z0.b-z1.b }, { z0.b-z1.b}
+fdot za.h[w8, 8], { z0.b-z1.b }, { z0.b-z1.b}
+
+fdot za.h[w8, 0], { z0.b-z3.b }, { z0.b-z1.b}
+fdot za.h[w8, 0], { z0.b-z3.b }, { z2.b-z5.b}
+fdot za.h[w8, 0], { z2.b-z5.b }, { z0.b-z3.b}
+fdot za.h[w7, 0], { z0.b-z3.b }, { z0.b-z3.b}
+fdot za.h[w8, 8], { z0.b-z3.b }, { z0.b-z3.b}
+
+fvdot za.h[w7, 0], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w12, 0], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w8, 8], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w8, 0], {z1.b-z2.b}, z0.b[0]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z16.b[0]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[8]
+
+fvdotb za.s[w7, 0], {z0.b-z1.b}, z0.b[0]
+fvdotb za.s[w12, 0], {z0.b-z1.b}, z0.b[0]
+fvdotb za.s[w8, 8], {z0.b-z1.b}, z0.b[0]
+fvdotb za.s[w8, 0], {z1.b-z2.b}, z0.b[0]
+fvdotb za.s[w8, 0], {z0.b-z1.b}, z16.b[0]
+fvdotb za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
+
+fvdott za.s[w7, 0], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w12, 0], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w8, 8], {z0.b-z1.b}, z0.b[0]
+fvdott za.s[w8, 0], {z1.b-z2.b}, z0.b[0]
+fvdott za.s[w8, 0], {z0.b-z1.b}, z16.b[0]
+fvdott za.s[w8, 0], {z0.b-z1.b}, z0.b[4]
new file mode 100644
@@ -0,0 +1,50 @@
+#as: -march=armv8-a+sme-f8f16
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1d00020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1df0020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1d003e0 fdot za\.h\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00820 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[4\]
+ *[0-9a-f]+: c1d00c28 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1d00027 fdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d06020 fdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1109040 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c11f9040 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c11093c0 fdot za\.h\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1109840 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[4\]
+ *[0-9a-f]+: c1109c48 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1109047 fdot za\.h\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c110f040 fdot za\.h\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1201008 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c12f1008 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b
+ *[0-9a-f]+: c12013e8 fdot za\.h\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
+ *[0-9a-f]+: c120100f fdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1207008 fdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1301008 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c13f1008 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b
+ *[0-9a-f]+: c13013e8 fdot za\.h\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
+ *[0-9a-f]+: c130100f fdot za\.h\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1307008 fdot za\.h\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1a01020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1be1020 fdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
+ *[0-9a-f]+: c1a013e0 fdot za\.h\[w8, 0, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a01027 fdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a07020 fdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a11020 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1bd1020 fdot za\.h\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
+ *[0-9a-f]+: c1a113a0 fdot za\.h\[w8, 0, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a11027 fdot za\.h\[w8, 7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a17020 fdot za\.h\[w11, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1d01020 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d07020 fvdot za\.h\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d01027 fvdot za\.h\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d013e0 fvdot za\.h\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1df1020 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1d01428 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\]
+ *[0-9a-f]+: c1d01c28 fvdot za\.h\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\]
new file mode 100644
@@ -0,0 +1,47 @@
+fdot za.h[w8, 0], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w8, 0], { z0.b - z1.b }, z15.b[0]
+fdot za.h[w8, 0], { z30.b-z31.b }, z0.b[0]
+fdot za.h[w8, 0, VGx2 ], { z0.b-z1.b }, z0.b[4]
+fdot za.h[w8, 0, VGx2 ], { z0.b-z1.b }, z0.b[7]
+fdot za.h[w8, 7], { z0.b-z1.b }, z0.b[0]
+fdot za.h[w11, 0], { z0.b-z1.b }, z0.b[0]
+
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w8, 0, VGx4], { z0.b - z3.b }, z15.b[0]
+fdot za.h[w8, 0], { z28.b-z31.b }, z0.b[0]
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[4]
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b[7]
+fdot za.h[w8, 7], { z0.b-z3.b }, z0.b[0]
+fdot za.h[w11, 0], { z0.b-z3.b }, z0.b[0]
+
+fdot za.h[w8, 0], { z0.b-z1.b }, z0.b
+fdot za.h[w8, 0], { z0.b - z1.b }, z15.b
+fdot za.h[w8, 0, VGx2], { z31.b-z0.b }, z0.b
+fdot za.h[w8, 7], { z0.b-z1.b }, z0.b
+fdot za.h[w11, 0], { z0.b-z1.b }, z0.b
+
+fdot za.h[w8, 0], { z0.b-z3.b }, z0.b
+fdot za.h[w8, 0, VGx4], { z0.b - z3.b }, z15.b
+fdot za.h[w8, 0], { z31.b-z2.b }, z0.b
+fdot za.h[w8, 7], { z0.b-z3.b }, z0.b
+fdot za.h[w11, 0], { z0.b-z3.b }, z0.b
+
+fdot za.h[w8, 0], { z0.b-z1.b }, {z0.b-z1.b }
+fdot za.h[w8, 0], { z0.b - z1.b }, {z30.b - z31.b}
+fdot za.h[w8, 0], { z30.b-z31.b }, {z0.b-z1.b}
+fdot za.h[w8, 7], { z0.b-z1.b },{ z0.b-z1.b}
+fdot za.h[w11, 0, VGx2], { z0.b-z1.b }, {z0.b-z1.b}
+
+fdot za.h[w8, 0], { z0.b-z3.b }, {z0.b-z3.b }
+fdot za.h[w8, 0], { z0.b - z3.b }, {z28.b - z31.b}
+fdot za.h[w8, 0], { z28.b-z31.b }, {z0.b-z3.b}
+fdot za.h[w8, 7], { z0.b-z3.b }, {z0.b-z3.b}
+fdot za.h[w11, 0, VGx4], { z0.b-z3.b }, {z0.b-z3.b}
+
+fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w11, 0, VGx2], {z0.b-z1.b}, z0.b[0]
+fvdot za.h[w8, 7], { z0.b-z1.b }, z0.b[0]
+fvdot za.h[w8, 0], {z30.b-z31.b}, z0.b[0]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z15.b[0]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[3]
+fvdot za.h[w8, 0], {z0.b-z1.b}, z0.b[7]
new file mode 100644
@@ -0,0 +1,55 @@
+#as: -march=armv8-a+sme-f8f32
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1500038 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c15f0038 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c15003f8 fdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1500c38 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[3\]
+ *[0-9a-f]+: c150003f fdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1506038 fdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1508008 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c15f8008 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1508388 fdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1508c08 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[3\]
+ *[0-9a-f]+: c150800f fdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c150e008 fdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1201018 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c12f1018 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, z15\.b
+ *[0-9a-f]+: c12013f8 fdot za\.s\[w8, 0, vgx2\], {z31\.b-z0\.b}, z0\.b
+ *[0-9a-f]+: c120101f fdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1207018 fdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1301018 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c13f1018 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, z15\.b
+ *[0-9a-f]+: c13013f8 fdot za\.s\[w8, 0, vgx4\], {z31\.b-z2\.b}, z0\.b
+ *[0-9a-f]+: c130101f fdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1307018 fdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1a01030 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1be1030 fdot za\.s\[w8, 0, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
+ *[0-9a-f]+: c1a013f0 fdot za\.s\[w8, 0, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a01037 fdot za\.s\[w8, 7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a07030 fdot za\.s\[w11, 0, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a11030 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1bd1030 fdot za\.s\[w8, 0, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
+ *[0-9a-f]+: c1a113b0 fdot za\.s\[w8, 0, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a11037 fdot za\.s\[w8, 7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a17030 fdot za\.s\[w11, 0, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1d00800 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d06800 fvdotb za\.s\[w11, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00807 fvdotb za\.s\[w8, 7, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00bc0 fvdotb za\.s\[w8, 0, vgx4\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1df0800 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1d00808 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c1d00c08 fvdotb za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[3\]
+ *[0-9a-f]+: c1d00810 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d06810 fvdott za\.s\[w11, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00817 fvdott za\.s\[w8, 7, vgx4\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1d00bd0 fvdott za\.s\[w8, 0, vgx4\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1df0810 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1d00818 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c1d00c18 fvdott za\.s\[w8, 0, vgx4\], {z0\.b-z1\.b}, z0\.b\[3\]
new file mode 100644
@@ -0,0 +1,53 @@
+fdot za.s[w8, 0], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w8, 0], { z0.b - z1.b }, z15.b[0]
+fdot za.s[w8, 0], { z30.b-z31.b }, z0.b[0]
+fdot za.s[w8, 0, VGx2 ], { z0.b-z1.b }, z0.b[3]
+fdot za.s[w8, 7], { z0.b-z1.b }, z0.b[0]
+fdot za.s[w11, 0], { z0.b-z1.b }, z0.b[0]
+
+fdot za.s[w8, 0], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w8, 0, VGx4], { z0.b - z3.b }, z15.b[0]
+fdot za.s[w8, 0], { z28.b-z31.b }, z0.b[0]
+fdot za.s[w8, 0], { z0.b-z3.b }, z0.b[3]
+fdot za.s[w8, 7], { z0.b-z3.b }, z0.b[0]
+fdot za.s[w11, 0], { z0.b-z3.b }, z0.b[0]
+
+fdot za.s[w8, 0], { z0.b-z1.b }, z0.b
+fdot za.s[w8, 0], { z0.b - z1.b }, z15.b
+fdot za.s[w8, 0, VGx2], { z31.b-z0.b }, z0.b
+fdot za.s[w8, 7], { z0.b-z1.b }, z0.b
+fdot za.s[w11, 0], { z0.b-z1.b }, z0.b
+
+fdot za.s[w8, 0], { z0.b-z3.b }, z0.b
+fdot za.s[w8, 0, VGx4], { z0.b - z3.b }, z15.b
+fdot za.s[w8, 0], { z31.b-z2.b }, z0.b
+fdot za.s[w8, 7], { z0.b-z3.b }, z0.b
+fdot za.s[w11, 0], { z0.b-z3.b }, z0.b
+
+fdot za.s[w8, 0], { z0.b-z1.b }, {z0.b-z1.b }
+fdot za.s[w8, 0], { z0.b - z1.b }, {z30.b - z31.b}
+fdot za.s[w8, 0], { z30.b-z31.b }, {z0.b-z1.b}
+fdot za.s[w8, 7], { z0.b-z1.b },{ z0.b-z1.b}
+fdot za.s[w11, 0, VGx2], { z0.b-z1.b }, {z0.b-z1.b}
+
+fdot za.s[w8, 0], { z0.b-z3.b }, {z0.b-z3.b }
+fdot za.s[w8, 0], { z0.b - z3.b }, {z28.b - z31.b}
+fdot za.s[w8, 0], { z28.b-z31.b }, {z0.b-z3.b}
+fdot za.s[w8, 7], { z0.b-z3.b }, {z0.b-z3.b}
+fdot za.s[w11, 0, VGx4], { z0.b-z3.b }, {z0.b-z3.b}
+
+fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdotb za.s[w11, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdotb za.s[w8, 7, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdotb za.s[w8, 0, VGx4], { z30.b-z31.b }, z0.b[0]
+fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z15.b[0]
+fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[1]
+fvdotb za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[3]
+
+fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdott za.s[w11, 0, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdott za.s[w8, 7, VGx4], { z0.b-z1.b }, z0.b[0]
+fvdott za.s[w8, 0, VGx4], { z30.b-z31.b }, z0.b[0]
+fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z15.b[0]
+fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[1]
+fvdott za.s[w8, 0, VGx4], { z0.b-z1.b }, z0.b[3]
new file mode 100644
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f16
+#error_output: fp8-sme-fmlal-illegal.l
new file mode 100644
@@ -0,0 +1,72 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z16\.b\[0\]'
+[^:]*:2: Error: unexpected vector group size at operand 1 -- `fmlal za\.h\[w8,0:1,VGx2\],z0\.b,z0\.b\[0\]'
+[^:]*:3: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z0\.b\[16\]'
+[^:]*:4: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],z0\.b,z0\.b\[0\]'
+[^:]*:5: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],z0\.b,z0\.b\[0\]'
+[^:]*:6: Error: immediate offset out of range 0 to 14 at operand 1 -- `fmlal za\.h\[w8,16:17\],z0\.b,z0\.b\[0\]'
+[^:]*:7: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],z0\.b,z0\.b\[0\]'
+[^:]*:8: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],z0\.b,z0\.b\[0\]'
+[^:]*:9: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],z0\.b,z0\.b\[0\]'
+[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:12: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z0\.b\[16\]'
+[^:]*:15: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:16: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:17: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:18: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z16\.b\[0\]'
+[^:]*:23: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z0\.b\[16\]'
+[^:]*:26: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:27: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:28: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:29: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:33: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],z0\.b,z16\.b'
+[^:]*:34: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],z0\.b,z0\.b'
+[^:]*:35: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],z0\.b,z0\.b'
+[^:]*:36: Error: immediate offset out of range 0 to 14 at operand 1 -- `fmlal za\.h\[w8,16:17\],z0\.b,z0\.b'
+[^:]*:37: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],z0\.b,z0\.b'
+[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0\],z0\.b,z0\.b'
+[^:]*:39: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0\],z0\.b,z0\.b'
+[^:]*:40: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0,VGx4\],z0\.b,z0\.b'
+[^:]*:42: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},z16\.b'
+[^:]*:43: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:44: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},z0\.b'
+[^:]*:45: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},z0\.b'
+[^:]*:46: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},z0\.b'
+[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},z0\.b'
+[^:]*:48: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},z0\.b'
+[^:]*:49: Error: expected a list of 4 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx4\],{z0\.b-z1\.b},z0\.b'
+[^:]*:51: Error: z0-z15 expected at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},z16\.b'
+[^:]*:52: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:53: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:54: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},z0\.b'
+[^:]*:55: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},z0\.b'
+[^:]*:56: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z3\.b},z0\.b'
+[^:]*:57: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z3\.b},z0\.b'
+[^:]*:58: Error: expected a list of 2 registers at operand 2 -- `fmlal za\.h\[w8,0:1,VGx2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:60: Error: expected a list of 2 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
+[^:]*:61: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
+[^:]*:62: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
+[^:]*:63: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:64: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:65: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:66: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:67: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:68: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:70: Error: expected a list of 4 registers at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
+[^:]*:71: Error: start register out of range at operand 3 -- `fmlal za\.h\[w8,0:1\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
+[^:]*:72: Error: start register out of range at operand 2 -- `fmlal za\.h\[w8,0:1\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
+[^:]*:73: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w7,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:74: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlal za\.h\[w12,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:75: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:76: Error: starting offset is not a multiple of 2 at operand 1 -- `fmlal za\.h\[w8,1:2\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:77: Error: immediate offset out of range 0 to 6 at operand 1 -- `fmlal za\.h\[w8,8:9\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:78: Error: expected a range of two offsets at operand 1 -- `fmlal za\.h\[w8,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
new file mode 100644
@@ -0,0 +1,78 @@
+fmlal za.h[w8, 0:1], z0.b, z16.b[0]
+fmlal za.h[w8, 0:1, VGx2], z0.b, z0.b[0]
+fmlal za.h[w8, 0:1], z0.b, z0.b[16]
+fmlal za.h[w8, 0], z0.b, z0.b[0]
+fmlal za.h[w8, 1:2], z0.b, z0.b[0]
+fmlal za.h[w8, 16:17], z0.b, z0.b[0]
+fmlal za.h[w8, 0:3], z0.b, z0.b[0]
+fmlal za.h[w7, 0:1], z0.b, z0.b[0]
+fmlal za.h[w12, 0:1], z0.b, z0.b[0]
+
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, z16.b[0]
+fmlal za.h[w8, 0:1], { z1.b-z2.b }, z0.b[0]
+fmlal za.h[w8, 0:1, VGx2], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, z0.b[16]
+fmlal za.h[w8, 0], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w8, 1:2], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w8, 8:9], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w8, 0:3], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w7, 0:1], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w12, 0:1], { z0.b-z1.b }, z0.b[0]
+
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, z16.b[0]
+fmlal za.h[w8, 0:1], { z2.b-z5.b }, z0.b[0]
+fmlal za.h[w8, 0:1, VGx4], { z0.b-z1.b }, z0.b[0]
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, z0.b[16]
+fmlal za.h[w8, 0], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w8, 1:2], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w8, 8:9], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w8, 0:3], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w7, 0], { z0.b-z3.b }, z0.b[0]
+fmlal za.h[w12, 0], { z0.b-z3.b }, z0.b[0]
+
+fmlal za.h[w8, 0:1], z0.b, z16.b
+fmlal za.h[w8, 0], z0.b, z0.b
+fmlal za.h[w8, 1:2], z0.b, z0.b
+fmlal za.h[w8, 16:17], z0.b, z0.b
+fmlal za.h[w8, 0:3], z0.b, z0.b
+fmlal za.h[w7, 0], z0.b, z0.b
+fmlal za.h[w12, 0], z0.b, z0.b
+fmlal za.h[w8, 0, VGx4], z0.b, z0.b
+
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, z16.b
+fmlal za.h[w8, 0], { z0.b-z1.b }, z0.b
+fmlal za.h[w8, 1:2], { z0.b-z1.b }, z0.b
+fmlal za.h[w8, 8:9], { z0.b-z1.b }, z0.b
+fmlal za.h[w8, 0:3], { z0.b-z1.b }, z0.b
+fmlal za.h[w7, 0:1], { z0.b-z1.b }, z0.b
+fmlal za.h[w12, 0:1], { z0.b-z1.b }, z0.b
+fmlal za.h[w8, 0:1, VGx4], { z0.b-z1.b }, z0.b
+
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, z16.b
+fmlal za.h[w8, 0], { z0.b-z3.b }, z0.b
+fmlal za.h[w8, 1:2], { z0.b-z3.b }, z0.b
+fmlal za.h[w8, 8:9], { z0.b-z3.b }, z0.b
+fmlal za.h[w8, 0:3], { z0.b-z3.b }, z0.b
+fmlal za.h[w7, 0:1], { z0.b-z3.b }, z0.b
+fmlal za.h[w12, 0:1], { z0.b-z3.b }, z0.b
+fmlal za.h[w8, 0:1, VGx2], { z0.b-z3.b }, z0.b
+
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, { z0.b-z3.b}
+fmlal za.h[w8, 0:1], { z0.b-z1.b }, { z1.b-z2.b}
+fmlal za.h[w8, 0:1], { z1.b-z2.b }, { z0.b-z1.b}
+fmlal za.h[w7, 0:1], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w12, 0:1], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w8, 0], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w8, 1:2], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w8, 8:9], { z0.b-z1.b }, { z0.b-z1.b}
+fmlal za.h[w8, 0:3], { z0.b-z1.b }, { z0.b-z1.b}
+
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, { z0.b-z1.b}
+fmlal za.h[w8, 0:1], { z0.b-z3.b }, { z2.b-z5.b}
+fmlal za.h[w8, 0:1], { z2.b-z5.b }, { z0.b-z3.b}
+fmlal za.h[w7, 0:1], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w12, 0:1], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w8, 0], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w8, 1:2], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w8, 8:9], { z0.b-z3.b }, { z0.b-z3.b}
+fmlal za.h[w8, 0:3], { z0.b-z3.b }, { z0.b-z3.b}
new file mode 100644
@@ -0,0 +1,57 @@
+#as: -march=armv8-a+sme-f8f16
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1c00000 fmlal za\.h\[w8, 0:1], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1c06000 fmlal za\.h\[w11, 0:1], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1c00007 fmlal za\.h\[w8, 14:15], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1c003e0 fmlal za\.h\[w8, 0:1], z31\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1cf0000 fmlal za\.h\[w8, 0:1], z0\.b, z15\.b\[0\]
+ *[0-9a-f]+: c1c00408 fmlal za\.h\[w8, 0:1], z0\.b, z0\.b\[3\]
+ *[0-9a-f]+: c1c08c08 fmlal za\.h\[w8, 0:1], z0\.b, z0\.b\[15\]
+ *[0-9a-f]+: c1901030 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1907030 fmlal za\.h\[w11, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1901033 fmlal za\.h\[w8, 6:7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19013f0 fmlal za\.h\[w8, 0:1, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19f1030 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1901034 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c190143c fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1901c3c fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b\[15\]
+ *[0-9a-f]+: c1909020 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c190f020 fmlal za\.h\[w11, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1909023 fmlal za\.h\[w8, 6:7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19093a0 fmlal za\.h\[w8, 0:1, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19f9020 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1909024 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c190942c fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1909c2c fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b\[15\]
+ *[0-9a-f]+: c1300c00 fmlal za\.h\[w8, 0:1\], z0\.b, z0\.b
+ *[0-9a-f]+: c1306c00 fmlal za\.h\[w11, 0:1\], z0\.b, z0\.b
+ *[0-9a-f]+: c1300c07 fmlal za\.h\[w8, 14:15\], z0\.b, z0\.b
+ *[0-9a-f]+: c1300fe0 fmlal za\.h\[w8, 0:1\], z31\.b, z0\.b
+ *[0-9a-f]+: c13f0c00 fmlal za\.h\[w8, 0:1\], z0\.b, z15\.b
+ *[0-9a-f]+: c1200804 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1206804 fmlal za\.h\[w11, 0:1, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1200807 fmlal za\.h\[w8, 6:7, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1200be4 fmlal za\.h\[w8, 0:1, vgx2\], {z31\.b-z0\.b}, z0\.b
+ *[0-9a-f]+: c12f0804 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, z15\.b
+ *[0-9a-f]+: c1300804 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1306804 fmlal za\.h\[w11, 0:1, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1300807 fmlal za\.h\[w8, 6:7, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1300be4 fmlal za\.h\[w8, 0:1, vgx4\], {z31\.b-z2\.b}, z0\.b
+ *[0-9a-f]+: c13f0804 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, z15\.b
+ *[0-9a-f]+: c1a00820 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a06820 fmlal za\.h\[w11, 0:1, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a00823 fmlal za\.h\[w8, 6:7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a00be0 fmlal za\.h\[w8, 0:1, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1be0820 fmlal za\.h\[w8, 0:1, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
+ *[0-9a-f]+: c1a10820 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a16820 fmlal za\.h\[w11, 0:1, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a10823 fmlal za\.h\[w8, 6:7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a10ba0 fmlal za\.h\[w8, 0:1, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1bd0820 fmlal za\.h\[w8, 0:1, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
new file mode 100644
@@ -0,0 +1,56 @@
+fmlal za.h[w8, 0:1], z0.b, z0.b[0]
+fmlal za.h[w11, 0:1], z0.b, z0.b[0]
+fmlal za.h[w8, 14:15], z0.b, z0.b[0]
+fmlal za.h[w8, 0:1], z31.b, z0.b[0]
+fmlal za.h[w8, 0:1], z0.b, z15.b[0]
+fmlal za.h[w8, 0:1], z0.b, z0.b[3]
+fmlal za.h[w8, 0:1], z0.b, z0.b[15]
+
+fmlal za.h[w8, 0:1], {z0.b-z1.b }, z0.b[0]
+fmlal za.h[w11, 0:1, VGx2], { z0.b-z1.b}, z0.b[0]
+fmlal za.h[w8, 6:7], {z0.b - z1.b}, z0.b[0]
+fmlal za.h[w8, 0:1], { z30.b-z31.b}, z0.b[0]
+fmlal za.h[w8, 0:1], { z0.b - z1.b}, z15.b[0]
+fmlal za.h[w8, 0:1], { z0.b - z1.b }, z0.b[1]
+fmlal za.h[w8, 0:1], { z0.b - z1.b }, z0.b[7]
+fmlal za.h[w8, 0:1], { z0.b - z1.b }, z0.b[15]
+
+fmlal za.h[w8, 0:1], {z0.b-z3.b }, z0.b[0]
+fmlal za.h[w11, 0:1, VGx4], { z0.b-z3.b}, z0.b[0]
+fmlal za.h[w8, 6:7], {z0.b - z3.b}, z0.b[0]
+fmlal za.h[w8, 0:1], { z28.b-z31.b}, z0.b[0]
+fmlal za.h[w8, 0:1], { z0.b - z3.b}, z15.b[0]
+fmlal za.h[w8, 0:1], { z0.b - z3.b }, z0.b[1]
+fmlal za.h[w8, 0:1], { z0.b - z3.b }, z0.b[7]
+fmlal za.h[w8, 0:1], { z0.b - z3.b }, z0.b[15]
+
+fmlal za.h[w8, 0:1], z0.b, z0.b
+fmlal za.h[w11, 0:1], z0.b, z0.b
+fmlal za.h[w8, 14:15], z0.b, z0.b
+fmlal za.h[w8, 0:1], z31.b, z0.b
+fmlal za.h[w8, 0:1], z0.b, z15.b
+
+fmlal za.h[w8, 0:1], {z0.b -z1.b}, z0.b
+fmlal za.h[w11, 0:1], {z0.b-z1.b}, z0.b
+fmlal za.h[w8, 6:7], { z0.b - z1.b }, z0.b
+fmlal za.h[w8, 0:1, VGx2], {z31.b - z0.b}, z0.b
+fmlal za.h[w8, 0:1], {z0.b - z1.b}, z15.b
+
+fmlal za.h[w8, 0:1], {z0.b -z3.b}, z0.b
+fmlal za.h[w11, 0:1], {z0.b-z3.b}, z0.b
+fmlal za.h[w8, 6:7], { z0.b - z3.b }, z0.b
+fmlal za.h[w8, 0:1, VGx4], {z31.b - z2.b}, z0.b
+fmlal za.h[w8, 0:1], {z0.b - z3.b}, z15.b
+
+fmlal za.h[w8, 0:1], {z0.b -z1.b}, {z0.b-z1.b}
+fmlal za.h[w11, 0:1], {z0.b-z1.b}, {z0.b - z1.b}
+fmlal za.h[w8, 6:7], { z0.b - z1.b }, {z0.b -z1.b}
+fmlal za.h[w8, 0:1, VGx2], {z30.b - z31.b}, {z0.b-z1.b}
+fmlal za.h[w8, 0:1], {z0.b - z1.b}, {z30.b -z31.b}
+
+fmlal za.h[w8, 0:1], {z0.b -z3.b}, {z0.b-z3.b}
+fmlal za.h[w11, 0:1], {z0.b-z3.b}, {z0.b - z3.b}
+fmlal za.h[w8, 6:7], { z0.b - z3.b }, {z0.b-z3.b}
+fmlal za.h[w8, 0:1, VGx4], {z28.b - z31.b}, {z0.b-z3.b}
+fmlal za.h[w8, 0:1], {z0.b - z3.b}, {z28.b-z31.b}
+
new file mode 100644
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f32
+#error_output: fp8-sme-fmlall-illegal.l
new file mode 100644
@@ -0,0 +1,72 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z16\.b\[0\]'
+[^:]*:2: Error: unexpected vector group size at operand 1 -- `fmlall za\.s\[w8,0:3,VGx2\],z0\.b,z0\.b\[0\]'
+[^:]*:3: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z0\.b\[16\]'
+[^:]*:4: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],z0\.b,z0\.b\[0\]'
+[^:]*:5: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],z0\.b,z0\.b\[0\]'
+[^:]*:6: Error: immediate offset out of range 0 to 12 at operand 1 -- `fmlall za\.s\[w8,16:19\],z0\.b,z0\.b\[0\]'
+[^:]*:7: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],z0\.b,z0\.b\[0\]'
+[^:]*:8: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],z0\.b,z0\.b\[0\]'
+[^:]*:9: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],z0\.b,z0\.b\[0\]'
+[^:]*:11: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z16\.b\[0\]'
+[^:]*:12: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z1\.b-z2\.b},z0\.b\[0\]'
+[^:]*:13: Error: expected a list of 2 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx2\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z0\.b\[16\]'
+[^:]*:15: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:16: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:17: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:18: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:20: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:22: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z16\.b\[0\]'
+[^:]*:23: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z2\.b-z5\.b},z0\.b\[0\]'
+[^:]*:24: Error: expected a list of 4 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx4\],{z0\.b-z1\.b},z0\.b\[0\]'
+[^:]*:25: Error: register element index out of range 0 to 15 at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z0\.b\[16\]'
+[^:]*:26: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:27: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:28: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:29: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:30: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:31: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0\],{z0\.b-z3\.b},z0\.b\[0\]'
+[^:]*:33: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],z0\.b,z16\.b'
+[^:]*:34: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],z0\.b,z0\.b'
+[^:]*:35: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],z0\.b,z0\.b'
+[^:]*:36: Error: immediate offset out of range 0 to 12 at operand 1 -- `fmlall za\.s\[w8,16:19\],z0\.b,z0\.b'
+[^:]*:37: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],z0\.b,z0\.b'
+[^:]*:38: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0\],z0\.b,z0\.b'
+[^:]*:39: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0\],z0\.b,z0\.b'
+[^:]*:40: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0,VGx4\],z0\.b,z0\.b'
+[^:]*:42: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},z16\.b'
+[^:]*:43: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},z0\.b'
+[^:]*:44: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},z0\.b'
+[^:]*:45: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},z0\.b'
+[^:]*:46: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},z0\.b'
+[^:]*:47: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},z0\.b'
+[^:]*:48: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},z0\.b'
+[^:]*:49: Error: expected a list of 4 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx4\],{z0\.b-z1\.b},z0\.b'
+[^:]*:51: Error: z0-z15 expected at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},z16\.b'
+[^:]*:52: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},z0\.b'
+[^:]*:53: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},z0\.b'
+[^:]*:54: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},z0\.b'
+[^:]*:55: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},z0\.b'
+[^:]*:56: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z3\.b},z0\.b'
+[^:]*:57: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z3\.b},z0\.b'
+[^:]*:58: Error: expected a list of 2 registers at operand 2 -- `fmlall za\.s\[w8,0:3,VGx2\],{z0\.b-z3\.b},z0\.b'
+[^:]*:60: Error: expected a list of 2 registers at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},{z0\.b-z3\.b}'
+[^:]*:61: Error: start register out of range at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z1\.b},{z1\.b-z2\.b}'
+[^:]*:62: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z1\.b-z2\.b},{z0\.b-z1\.b}'
+[^:]*:63: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:64: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:65: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:66: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:67: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:68: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^:]*:70: Error: expected a list of 4 registers at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},{z0\.b-z1\.b}'
+[^:]*:71: Error: start register out of range at operand 3 -- `fmlall za\.s\[w8,0:3\],{z0\.b-z3\.b},{z2\.b-z5\.b}'
+[^:]*:72: Error: start register out of range at operand 2 -- `fmlall za\.s\[w8,0:3\],{z2\.b-z5\.b},{z0\.b-z3\.b}'
+[^:]*:73: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w7,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:74: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmlall za\.s\[w12,0:3\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:75: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:76: Error: starting offset is not a multiple of 4 at operand 1 -- `fmlall za\.s\[w8,2:5\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:77: Error: immediate offset out of range 0 to 4 at operand 1 -- `fmlall za\.s\[w8,8:11\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^:]*:78: Error: expected a range of four offsets at operand 1 -- `fmlall za\.s\[w8,0:1\],{z0\.b-z3\.b},{z0\.b-z3\.b}'
new file mode 100644
@@ -0,0 +1,78 @@
+fmlall za.s[w8, 0:3], z0.b, z16.b[0]
+fmlall za.s[w8, 0:3, VGx2], z0.b, z0.b[0]
+fmlall za.s[w8, 0:3], z0.b, z0.b[16]
+fmlall za.s[w8, 0], z0.b, z0.b[0]
+fmlall za.s[w8, 2:5], z0.b, z0.b[0]
+fmlall za.s[w8, 16:19], z0.b, z0.b[0]
+fmlall za.s[w8, 0:1], z0.b, z0.b[0]
+fmlall za.s[w7, 0:3], z0.b, z0.b[0]
+fmlall za.s[w12, 0:3], z0.b, z0.b[0]
+
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, z16.b[0]
+fmlall za.s[w8, 0:3], { z1.b-z2.b }, z0.b[0]
+fmlall za.s[w8, 0:3, VGx2], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, z0.b[16]
+fmlall za.s[w8, 0], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w8, 2:5], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w8, 8:11], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w8, 0:1], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w7, 0:3], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w12, 0:3], { z0.b-z1.b }, z0.b[0]
+
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, z16.b[0]
+fmlall za.s[w8, 0:3], { z2.b-z5.b }, z0.b[0]
+fmlall za.s[w8, 0:3, VGx4], { z0.b-z1.b }, z0.b[0]
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, z0.b[16]
+fmlall za.s[w8, 0], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w8, 2:5], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w8, 8:11], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w8, 0:1], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w7, 0], { z0.b-z3.b }, z0.b[0]
+fmlall za.s[w12, 0], { z0.b-z3.b }, z0.b[0]
+
+fmlall za.s[w8, 0:3], z0.b, z16.b
+fmlall za.s[w8, 0], z0.b, z0.b
+fmlall za.s[w8, 2:5], z0.b, z0.b
+fmlall za.s[w8, 16:19], z0.b, z0.b
+fmlall za.s[w8, 0:1], z0.b, z0.b
+fmlall za.s[w7, 0], z0.b, z0.b
+fmlall za.s[w12, 0], z0.b, z0.b
+fmlall za.s[w8, 0, VGx4], z0.b, z0.b
+
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, z16.b
+fmlall za.s[w8, 0], { z0.b-z1.b }, z0.b
+fmlall za.s[w8, 2:5], { z0.b-z1.b }, z0.b
+fmlall za.s[w8, 8:11], { z0.b-z1.b }, z0.b
+fmlall za.s[w8, 0:1], { z0.b-z1.b }, z0.b
+fmlall za.s[w7, 0:3], { z0.b-z1.b }, z0.b
+fmlall za.s[w12, 0:3], { z0.b-z1.b }, z0.b
+fmlall za.s[w8, 0:3, VGx4], { z0.b-z1.b }, z0.b
+
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, z16.b
+fmlall za.s[w8, 0], { z0.b-z3.b }, z0.b
+fmlall za.s[w8, 2:5], { z0.b-z3.b }, z0.b
+fmlall za.s[w8, 8:11], { z0.b-z3.b }, z0.b
+fmlall za.s[w8, 0:1], { z0.b-z3.b }, z0.b
+fmlall za.s[w7, 0:3], { z0.b-z3.b }, z0.b
+fmlall za.s[w12, 0:3], { z0.b-z3.b }, z0.b
+fmlall za.s[w8, 0:3, VGx2], { z0.b-z3.b }, z0.b
+
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, { z0.b-z3.b}
+fmlall za.s[w8, 0:3], { z0.b-z1.b }, { z1.b-z2.b}
+fmlall za.s[w8, 0:3], { z1.b-z2.b }, { z0.b-z1.b}
+fmlall za.s[w7, 0:3], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w12, 0:3], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w8, 0], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w8, 2:5], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w8, 8:11], { z0.b-z1.b }, { z0.b-z1.b}
+fmlall za.s[w8, 0:1], { z0.b-z1.b }, { z0.b-z1.b}
+
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, { z0.b-z1.b}
+fmlall za.s[w8, 0:3], { z0.b-z3.b }, { z2.b-z5.b}
+fmlall za.s[w8, 0:3], { z2.b-z5.b }, { z0.b-z3.b}
+fmlall za.s[w7, 0:3], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w12, 0:3], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w8, 0], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w8, 2:5], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w8, 8:11], { z0.b-z3.b }, { z0.b-z3.b}
+fmlall za.s[w8, 0:1], { z0.b-z3.b }, { z0.b-z3.b}
new file mode 100644
@@ -0,0 +1,57 @@
+#as: -march=armv8-a+sme-f8f32
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1400000 fmlall za\.s\[w8, 0:3], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1406000 fmlall za\.s\[w11, 0:3], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c1400003 fmlall za\.s\[w8, 12:15], z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: c14003e0 fmlall za\.s\[w8, 0:3], z31\.b, z0\.b\[0\]
+ *[0-9a-f]+: c14f0000 fmlall za\.s\[w8, 0:3], z0\.b, z15\.b\[0\]
+ *[0-9a-f]+: c1400c00 fmlall za\.s\[w8, 0:3], z0\.b, z0\.b\[3\]
+ *[0-9a-f]+: c1409c00 fmlall za\.s\[w8, 0:3], z0\.b, z0\.b\[15\]
+ *[0-9a-f]+: c1900020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1906020 fmlall za\.s\[w11, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1900021 fmlall za\.s\[w8, 4:7, vgx2\], {z0\.b-z1\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19003e0 fmlall za\.s\[w8, 0:3, vgx2\], {z30\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c19f0020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1900022 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c1900426 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1900c26 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b\[15\]
+ *[0-9a-f]+: c1108040 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c110e040 fmlall za\.s\[w11, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c1108041 fmlall za\.s\[w8, 4:7, vgx4\], {z0\.b-z3\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c11083c0 fmlall za\.s\[w8, 0:3, vgx4\], {z28\.b-z31\.b}, z0\.b\[0\]
+ *[0-9a-f]+: c11f8040 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z15\.b\[0\]
+ *[0-9a-f]+: c1108042 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[1\]
+ *[0-9a-f]+: c1108446 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[7\]
+ *[0-9a-f]+: c1108c46 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b\[15\]
+ *[0-9a-f]+: c1300400 fmlall za\.s\[w8, 0:3\], z0\.b, z0\.b
+ *[0-9a-f]+: c1306400 fmlall za\.s\[w11, 0:3\], z0\.b, z0\.b
+ *[0-9a-f]+: c1300403 fmlall za\.s\[w8, 12:15\], z0\.b, z0\.b
+ *[0-9a-f]+: c13007e0 fmlall za\.s\[w8, 0:3\], z31\.b, z0\.b
+ *[0-9a-f]+: c13f0400 fmlall za\.s\[w8, 0:3\], z0\.b, z15\.b
+ *[0-9a-f]+: c1200002 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1206002 fmlall za\.s\[w11, 0:3, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c1200003 fmlall za\.s\[w8, 4:7, vgx2\], {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+: c12003e2 fmlall za\.s\[w8, 0:3, vgx2\], {z31\.b-z0\.b}, z0\.b
+ *[0-9a-f]+: c12f0002 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, z15\.b
+ *[0-9a-f]+: c1300002 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1306002 fmlall za\.s\[w11, 0:3, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c1300003 fmlall za\.s\[w8, 4:7, vgx4\], {z0\.b-z3\.b}, z0\.b
+ *[0-9a-f]+: c13003e2 fmlall za\.s\[w8, 0:3, vgx4\], {z31\.b-z2\.b}, z0\.b
+ *[0-9a-f]+: c13f0002 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, z15\.b
+ *[0-9a-f]+: c1a00020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a06020 fmlall za\.s\[w11, 0:3, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a00021 fmlall za\.s\[w8, 4:7, vgx2\], {z0\.b-z1\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1a003e0 fmlall za\.s\[w8, 0:3, vgx2\], {z30\.b-z31\.b}, {z0\.b-z1\.b}
+ *[0-9a-f]+: c1be0020 fmlall za\.s\[w8, 0:3, vgx2\], {z0\.b-z1\.b}, {z30\.b-z31\.b}
+ *[0-9a-f]+: c1a10020 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a16020 fmlall za\.s\[w11, 0:3, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a10021 fmlall za\.s\[w8, 4:7, vgx4\], {z0\.b-z3\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1a103a0 fmlall za\.s\[w8, 0:3, vgx4\], {z28\.b-z31\.b}, {z0\.b-z3\.b}
+ *[0-9a-f]+: c1bd0020 fmlall za\.s\[w8, 0:3, vgx4\], {z0\.b-z3\.b}, {z28\.b-z31\.b}
new file mode 100644
@@ -0,0 +1,56 @@
+fmlall za.s[w8, 0:3], z0.b, z0.b[0]
+fmlall za.s[w11, 0:3], z0.b, z0.b[0]
+fmlall za.s[w8, 12:15], z0.b, z0.b[0]
+fmlall za.s[w8, 0:3], z31.b, z0.b[0]
+fmlall za.s[w8, 0:3], z0.b, z15.b[0]
+fmlall za.s[w8, 0:3], z0.b, z0.b[3]
+fmlall za.s[w8, 0:3], z0.b, z0.b[15]
+
+fmlall za.s[w8, 0:3], {z0.b-z1.b }, z0.b[0]
+fmlall za.s[w11, 0:3, VGx2], { z0.b-z1.b}, z0.b[0]
+fmlall za.s[w8, 4:7], {z0.b - z1.b}, z0.b[0]
+fmlall za.s[w8, 0:3], { z30.b-z31.b}, z0.b[0]
+fmlall za.s[w8, 0:3], { z0.b - z1.b}, z15.b[0]
+fmlall za.s[w8, 0:3], { z0.b - z1.b }, z0.b[1]
+fmlall za.s[w8, 0:3], { z0.b - z1.b }, z0.b[7]
+fmlall za.s[w8, 0:3], { z0.b - z1.b }, z0.b[15]
+
+fmlall za.s[w8, 0:3], {z0.b-z3.b }, z0.b[0]
+fmlall za.s[w11, 0:3, VGx4], { z0.b-z3.b}, z0.b[0]
+fmlall za.s[w8, 4:7], {z0.b - z3.b}, z0.b[0]
+fmlall za.s[w8, 0:3], { z28.b-z31.b}, z0.b[0]
+fmlall za.s[w8, 0:3], { z0.b - z3.b}, z15.b[0]
+fmlall za.s[w8, 0:3], { z0.b - z3.b }, z0.b[1]
+fmlall za.s[w8, 0:3], { z0.b - z3.b }, z0.b[7]
+fmlall za.s[w8, 0:3], { z0.b - z3.b }, z0.b[15]
+
+fmlall za.s[w8, 0:3], z0.b, z0.b
+fmlall za.s[w11, 0:3], z0.b, z0.b
+fmlall za.s[w8, 12:15], z0.b, z0.b
+fmlall za.s[w8, 0:3], z31.b, z0.b
+fmlall za.s[w8, 0:3], z0.b, z15.b
+
+fmlall za.s[w8, 0:3], {z0.b -z1.b}, z0.b
+fmlall za.s[w11, 0:3], {z0.b-z1.b}, z0.b
+fmlall za.s[w8, 4:7], { z0.b - z1.b }, z0.b
+fmlall za.s[w8, 0:3, VGx2], {z31.b - z0.b}, z0.b
+fmlall za.s[w8, 0:3], {z0.b - z1.b}, z15.b
+
+fmlall za.s[w8, 0:3], {z0.b -z3.b}, z0.b
+fmlall za.s[w11, 0:3], {z0.b-z3.b}, z0.b
+fmlall za.s[w8, 4:7], { z0.b - z3.b }, z0.b
+fmlall za.s[w8, 0:3, VGx4], {z31.b - z2.b}, z0.b
+fmlall za.s[w8, 0:3], {z0.b - z3.b}, z15.b
+
+fmlall za.s[w8, 0:3], {z0.b -z1.b}, {z0.b-z1.b}
+fmlall za.s[w11, 0:3], {z0.b-z1.b}, {z0.b - z1.b}
+fmlall za.s[w8, 4:7], { z0.b - z1.b }, {z0.b -z1.b}
+fmlall za.s[w8, 0:3, VGx2], {z30.b - z31.b}, {z0.b-z1.b}
+fmlall za.s[w8, 0:3], {z0.b - z1.b}, {z30.b -z31.b}
+
+fmlall za.s[w8, 0:3], {z0.b -z3.b}, {z0.b-z3.b}
+fmlall za.s[w11, 0:3], {z0.b-z3.b}, {z0.b - z3.b}
+fmlall za.s[w8, 4:7], { z0.b - z3.b }, {z0.b-z3.b}
+fmlall za.s[w8, 0:3, VGx4], {z28.b - z31.b}, {z0.b-z3.b}
+fmlall za.s[w8, 0:3], {z0.b - z3.b}, {z28.b-z31.b}
+
new file mode 100644
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f16
+#error_output: fp8-sme-mopa-illegal.l
new file mode 100644
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: ZA tile number out of range at operand 1 -- `fmopa za2\.h,p0/m,p0/m,z0\.b,z0\.b'
+[^:]*:2: Error: p0-p7 expected at operand 2 -- `fmopa za0\.h,p8/m,p0/m,z0\.b,z0\.b'
+[^:]*:3: Error: p0-p7 expected at operand 3 -- `fmopa za0\.h,p0/m,p8/m,z0\.b,z0\.b'
+[^:]*:5: Error: ZA tile number out of range at operand 1 -- `fmopa za4\.s,p0/m,p0/m,z0\.b,z0\.b'
+[^:]*:6: Error: p0-p7 expected at operand 2 -- `fmopa za0\.s,p8/m,p0/m,z0\.b,z0\.b'
+[^:]*:7: Error: p0-p7 expected at operand 3 -- `fmopa za0\.s,p0/m,p8/m,z0\.b,z0\.b'
new file mode 100644
@@ -0,0 +1,7 @@
+fmopa za2.h, p0/m, p0/m, z0.b, z0.b
+fmopa za0.h, p8/m, p0/m, z0.b, z0.b
+fmopa za0.h, p0/m, p8/m, z0.b, z0.b
+
+fmopa za4.s, p0/m, p0/m, z0.b, z0.b
+fmopa za0.s, p8/m, p0/m, z0.b, z0.b
+fmopa za0.s, p0/m, p8/m, z0.b, z0.b
new file mode 100644
@@ -0,0 +1,15 @@
+#as: -march=armv8-a+sme-f8f16
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 80a00008 fmopa za0\.h, p0/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a00009 fmopa za1\.h, p0/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a01c08 fmopa za0\.h, p7/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a0e008 fmopa za0\.h, p0/m, p7/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a003e8 fmopa za0\.h, p0/m, p0/m, z31\.b, z0\.b
+ *[0-9a-f]+: 80bf0008 fmopa za0\.h, p0/m, p0/m, z0\.b, z31\.b
new file mode 100644
@@ -0,0 +1,6 @@
+fmopa za0.h, p0/m, p0/m, z0.b, z0.b
+fmopa za1.h, p0/m, p0/m, z0.b, z0.b
+fmopa za0.h, p7/m, p0/m, z0.b, z0.b
+fmopa za0.h, p0/m, p7/m, z0.b, z0.b
+fmopa za0.h, p0/m, p0/m, z31.b, z0.b
+fmopa za0.h, p0/m, p0/m, z0.b, z31.b
new file mode 100644
@@ -0,0 +1,15 @@
+#as: -march=armv8-a+sme-f8f32
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 80a00000 fmopa za0\.s, p0/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a00003 fmopa za3\.s, p0/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a01c00 fmopa za0\.s, p7/m, p0/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a0e000 fmopa za0\.s, p0/m, p7/m, z0\.b, z0\.b
+ *[0-9a-f]+: 80a003e0 fmopa za0\.s, p0/m, p0/m, z31\.b, z0\.b
+ *[0-9a-f]+: 80bf0000 fmopa za0\.s, p0/m, p0/m, z0\.b, z31\.b
new file mode 100644
@@ -0,0 +1,6 @@
+fmopa za0.s, p0/m, p0/m, z0.b, z0.b
+fmopa za3.s, p0/m, p0/m, z0.b, z0.b
+fmopa za0.s, p7/m, p0/m, z0.b, z0.b
+fmopa za0.s, p0/m, p7/m, z0.b, z0.b
+fmopa za0.s, p0/m, p0/m, z31.b, z0.b
+fmopa za0.s, p0/m, p0/m, z0.b, z31.b
new file mode 100644
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sme-f8f16
+#error_output: sme-fp16-addsub-illegal.l
new file mode 100644
@@ -0,0 +1,19 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w7,0\],{z0\.h-z1\.h}'
+[^:]*:2: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w12,0\],{z0\.h-z1\.h}'
+[^:]*:3: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.h\[w8,8\],{z0\.h-z1\.h}'
+[^:]*:4: Error: start register out of range at operand 2 -- `fadd za\.h\[w8,0\],{z1\.h-z2\.h}'
+[^:]*:6: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w7,0\],{z0\.h-z3\.h}'
+[^:]*:7: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.h\[w12,0\],{z0\.h-z3\.h}'
+[^:]*:8: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.h\[w8,8\],{z0\.h-z3\.h}'
+[^:]*:9: Error: start register out of range at operand 2 -- `fadd za\.h\[w8,0\],{z2\.h-z5\.h}'
+[^:]*:11: Error: missing braces at operand 2 -- `fadd za\.h\[w0,0\],z0\.h'
+[^:]*:13: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w7,0\],{z0\.h-z1\.h}'
+[^:]*:14: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w12,0\],{z0\.h-z1\.h}'
+[^:]*:15: Error: immediate offset out of range 0 to 7 at operand 1 -- `fsub za\.h\[w8,8\],{z0\.h-z1\.h}'
+[^:]*:16: Error: start register out of range at operand 2 -- `fsub za\.h\[w8,0\],{z1\.h-z2\.h}'
+[^:]*:18: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w7,0\],{z0\.h-z3\.h}'
+[^:]*:19: Error: expected a selection register in the range w8-w11 at operand 1 -- `fsub za\.h\[w12,0\],{z0\.h-z3\.h}'
+[^:]*:20: Error: immediate offset out of range 0 to 7 at operand 1 -- `fsub za\.h\[w8,8\],{z0\.h-z3\.h}'
+[^:]*:21: Error: start register out of range at operand 2 -- `fsub za\.h\[w8,0\],{z2\.h-z5\.h}'
+[^:]*:23: Error: missing braces at operand 2 -- `fsub za\.h\[w0,0\],z0\.h'
new file mode 100644
@@ -0,0 +1,24 @@
+fadd za.h[w7, 0], {z0.h-z1.h}
+fadd za.h[w12, 0], {z0.h-z1.h}
+fadd za.h[w8, 8], {z0.h-z1.h}
+fadd za.h[w8, 0], {z1.h-z2.h}
+
+fadd za.h[w7, 0], {z0.h-z3.h}
+fadd za.h[w12, 0], {z0.h-z3.h}
+fadd za.h[w8, 8], {z0.h-z3.h}
+fadd za.h[w8, 0], {z2.h-z5.h}
+
+fadd za.h[w0, 0], z0.h
+
+fsub za.h[w7, 0], {z0.h-z1.h}
+fsub za.h[w12, 0], {z0.h-z1.h}
+fsub za.h[w8, 8], {z0.h-z1.h}
+fsub za.h[w8, 0], {z1.h-z2.h}
+
+fsub za.h[w7, 0], {z0.h-z3.h}
+fsub za.h[w12, 0], {z0.h-z3.h}
+fsub za.h[w8, 8], {z0.h-z3.h}
+fsub za.h[w8, 0], {z2.h-z5.h}
+
+fsub za.h[w0, 0], z0.h
+
new file mode 100644
@@ -0,0 +1,25 @@
+#as: -march=armv8-a+sme-f8f16
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c1a41c00 fadd za\.h\[w8, 0, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a47c00 fadd za\.h\[w11, 0, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a41c07 fadd za\.h\[w8, 7, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a41fc0 fadd za\.h\[w8, 0, vgx2\], {z30\.h-z31\.h}
+ *[0-9a-f]+: c1a51c00 fadd za\.h\[w8, 0, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a57c00 fadd za\.h\[w11, 0, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a51c07 fadd za\.h\[w8, 7, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a51f80 fadd za\.h\[w8, 0, vgx4\], {z28\.h-z31\.h}
+ *[0-9a-f]+: c1a41c08 fsub za\.h\[w8, 0, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a47c08 fsub za\.h\[w11, 0, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a41c0f fsub za\.h\[w8, 7, vgx2\], {z0\.h-z1\.h}
+ *[0-9a-f]+: c1a41fc8 fsub za\.h\[w8, 0, vgx2\], {z30\.h-z31\.h}
+ *[0-9a-f]+: c1a51c08 fsub za\.h\[w8, 0, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a57c08 fsub za\.h\[w11, 0, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a51c0f fsub za\.h\[w8, 7, vgx4\], {z0\.h-z3\.h}
+ *[0-9a-f]+: c1a51f88 fsub za\.h\[w8, 0, vgx4\], {z28\.h-z31\.h}
new file mode 100644
@@ -0,0 +1,19 @@
+fadd za.h[w8, 0], {z0.h-z1.h}
+fadd za.h[w11, 0], {z0.h-z1.h}
+fadd za.h[w8, 7], {z0.h-z1.h}
+fadd za.h[w8, 0], {z30.h-z31.h}
+
+fadd za.h[w8, 0], {z0.h-z3.h}
+fadd za.h[w11, 0], {z0.h-z3.h}
+fadd za.h[w8, 7], {z0.h-z3.h}
+fadd za.h[w8, 0], {z28.h-z31.h}
+
+fsub za.h[w8, 0], {z0.h-z1.h}
+fsub za.h[w11, 0], {z0.h-z1.h}
+fsub za.h[w8, 7], {z0.h-z1.h}
+fsub za.h[w8, 0], {z30.h-z31.h}
+
+fsub za.h[w8, 0], {z0.h-z3.h}
+fsub za.h[w11, 0], {z0.h-z3.h}
+fsub za.h[w8, 7], {z0.h-z3.h}
+fsub za.h[w8, 0], {z28.h-z31.h}
@@ -6,7 +6,7 @@
[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `fvdot za\.h\[w8,0\],{z0\.h-z1\.h},z0\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fvdot za\.s\[w8,0\],{z0\.b-z1\.h},z0\.b\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: fvdot za\.s\[w8, 0\], {z0\.h-z1\.h}, z0\.h\[0\]
+[^ :]+:[0-9]+: Info: fvdot za\.h\[w8, 0\], {z0\.b-z1\.b}, z0\.b\[0\]
[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fvdot za\.s\[w8,0:1\],{z0\.h-z1\.h},z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand 1 must have a vector group size of 2 -- `fvdot za\.s\[w8,0,vgx4\],{z0\.h-z1\.h},z0\.h\[0\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fvdot za\.s\[w7,0\],{z0\.h-z1\.h},z0\.h\[0\]'
@@ -172,8 +172,4 @@
[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s}
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d}
-[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.h\[w8,0\],{z0\.h-z1\.h}'
-[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s}
-[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.h\[w8,0\],{z0\.h-z1\.h}'
@@ -250,6 +250,10 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SSVE_FP8DOT4,
/* SSVE FP8DOT2 instructions. */
AARCH64_FEATURE_SSVE_FP8DOT2,
+ /* SME F8F32 instructions. */
+ AARCH64_FEATURE_SME_F8F32,
+ /* SME F8F16 instructions. */
+ AARCH64_FEATURE_SME_F8F16,
AARCH64_NUM_FEATURES
};
@@ -777,6 +781,7 @@ enum aarch64_opnd
AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */
AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */
+ AARCH64_OPND_SME_ZAda_1b, /* SME <ZAda>.H, 1-bits. */
AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */
AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */
AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */
@@ -807,10 +812,14 @@ enum aarch64_opnd
AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */
AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */
AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */
+ AARCH64_OPND_SME_Zm_INDEX2_3, /* Zn.T[index], bits [19:16,10,3]. */
AARCH64_OPND_SME_Zm_INDEX3_1, /* Zn.T[index], bits [19:16,10,2:1]. */
AARCH64_OPND_SME_Zm_INDEX3_2, /* Zn.T[index], bits [19:16,11:10,2]. */
+ AARCH64_OPND_SME_Zm_INDEX3_3, /* Zn.T[index], bits [19:16,11:10,3]. */
AARCH64_OPND_SME_Zm_INDEX3_10, /* Zn.T[index], bits [19:16,15,11:10]. */
AARCH64_OPND_SME_Zm_INDEX4_1, /* Zn.T[index], bits [19:16,11:10,2:1]. */
+ AARCH64_OPND_SME_Zm_INDEX4_2, /* Zn.T[index], bits [19:16,11:10,3:2]. */
+ AARCH64_OPND_SME_Zm_INDEX4_3, /* Zn.T[index], bits [19:16,15,11,10,3]. */
AARCH64_OPND_SME_Zm_INDEX4_10, /* Zn.T[index], bits [19:16,15,12:10]. */
AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */
AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */
@@ -680,16 +680,17 @@ aarch64_insert_operand (const aarch64_operand *self,
case 245:
case 252:
case 253:
- case 260:
+ case 254:
case 261:
case 262:
case 263:
+ case 264:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 295:
- case 297:
+ case 300:
+ case 302:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -704,7 +705,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 299:
+ case 304:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -712,9 +713,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 226:
case 227:
case 230:
- case 264:
case 265:
- case 280:
+ case 266:
case 281:
case 282:
case 283:
@@ -727,6 +727,11 @@ aarch64_insert_operand (const aarch64_operand *self,
case 290:
case 291:
case 292:
+ case 293:
+ case 294:
+ case 295:
+ case 296:
+ case 297:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -774,13 +779,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 206:
case 207:
case 208:
- case 266:
- case 293:
- case 294:
- case 296:
+ case 267:
case 298:
+ case 299:
+ case 301:
case 303:
- case 304:
+ case 308:
+ case 309:
return aarch64_ins_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -928,7 +933,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 198:
case 199:
case 200:
- case 279:
+ case 280:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 213:
case 214:
@@ -955,10 +960,10 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 240:
case 242:
- case 259:
- case 305:
- case 306:
- case 307:
+ case 260:
+ case 310:
+ case 311:
+ case 312:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 243:
case 244:
@@ -966,44 +971,44 @@ aarch64_insert_operand (const aarch64_operand *self,
case 247:
case 248:
case 249:
- case 258:
+ case 259:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 250:
case 251:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
- case 254:
- case 256:
- case 267:
- return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 255:
case 257:
- return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 268:
+ return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 256:
+ case 258:
+ return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 269:
case 270:
case 271:
case 272:
case 273:
case 274:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 275:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 276:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 277:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 278:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 279:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 300:
- case 301:
- case 302:
+ case 305:
+ case 306:
+ case 307:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 308:
- case 309:
- case 310:
- case 311:
+ case 313:
+ case 314:
+ case 315:
+ case 316:
return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
- case 312:
+ case 317:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
@@ -1116,21 +1116,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x00000101xxxxxxxxxxxxxxxx0xxxx
- sumopa. */
- return 2423;
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000000101xxxxxxxxxxxxxxxx00xxx
+ fmopa. */
+ return 3458;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000000101xxxxxxxxxxxxxxxx01xxx
+ fmopa. */
+ return 3457;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1x00000101xxxxxxxxxxxxxxxx0xxxx
- st1w. */
- return 2452;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100000101xxxxxxxxxxxxxxxx0xxxx
+ sumopa. */
+ return 2423;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100000101xxxxxxxxxxxxxxxx0xxxx
+ st1w. */
+ return 2452;
+ }
}
}
else
@@ -1394,13 +1416,13 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 3) & 0x1) == 0)
+ if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 2) & 0x1) == 0)
{
- if (((word >> 2) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -1412,54 +1434,109 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010000xxxxxxxxxxxxxxx001xx
- usmlall. */
- return 2931;
+ xx0000010000xxxxxxxxxxxxxxx010xx
+ smlsll. */
+ return 2742;
}
}
else
{
- if (((word >> 5) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010000xxxxxxxxxxxxxxx0x1xx
+ usmlall. */
+ return 2931;
+ }
+ }
+ else
+ {
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx000xxx
- smlall. */
- return 2727;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx000xxx
+ smlall. */
+ return 2727;
+ }
+ else
+ {
+ if (((word >> 6) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxx0000xxx
+ smlall. */
+ return 2728;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxx1000xxx
+ fmlall. */
+ return 3451;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx000xxx
- smlall. */
- return 2728;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx001xxx
+ smlsll. */
+ return 2743;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx001xxx
+ smlsll. */
+ return 2744;
+ }
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx100xxx
- usmlall. */
- return 2932;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx100xxx
- usmlall. */
- return 2933;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxxxxx1xxxxxx00xxxx
+ fdot. */
+ return 3436;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xxxxxxxxx10xxxx
+ usmlall. */
+ return 2932;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xxxxxxxxx10xxxx
+ usmlall. */
+ return 2933;
}
}
}
- else
+ }
+ else
+ {
+ if (((word >> 3) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
{
@@ -1522,39 +1599,6 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
}
}
- }
- else
- {
- if (((word >> 4) & 0x1) == 0)
- {
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010000xxxxxxxxxxxxxxx01xxx
- smlsll. */
- return 2742;
- }
- else
- {
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxxx01xxx
- smlsll. */
- return 2743;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxxx01xxx
- smlsll. */
- return 2744;
- }
- }
- }
else
{
if (((word >> 20) & 0x1) == 0)
@@ -1785,23 +1829,23 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 3) & 0x1) == 0)
+ if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 30) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0000001100xxxxxxxxxxxxxxxx00xxx
- bfmopa. */
- return 2410;
- }
- else
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001100xxxxxxxxxxxxxxxx0xxxx
+ bfmopa. */
+ return 2410;
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
{
@@ -1813,21 +1857,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 5) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011001xxxx0xx0xxxxxxx00xxx
- smlall. */
- return 2964;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx0xx0xxxxxx000xxx
+ smlall. */
+ return 2964;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx1xx0xxxxxx000xxx
+ smlall. */
+ return 2965;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011001xxxx1xx0xxxxxxx00xxx
- smlall. */
- return 2965;
+ x10000011001xxxxxxx0xxxxxx100xxx
+ fmlall. */
+ return 3450;
}
}
}
@@ -1837,9 +1892,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011000xxxxxxx1xxxxxxx00xxx
- fmlal. */
- return 2567;
+ x10000011000xxxxxxx0xxxxxxx01xxx
+ smlsll. */
+ return 2966;
}
else
{
@@ -1847,23 +1902,100 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011001xxxx0xx1xxxxxxx00xxx
- fmlal. */
- return 2568;
+ x10000011001xxxx0xx0xxxxxxx01xxx
+ smlsll. */
+ return 2967;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011001xxxx1xx1xxxxxxx00xxx
- fmlal. */
- return 2569;
+ x10000011001xxxx1xx0xxxxxxx01xxx
+ smlsll. */
+ return 2968;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011000xxxxxxx1xxxxxxx00xxx
+ fmlal. */
+ return 2567;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011000xxxxxxx1xxxxxxx01xxx
+ fmlsl. */
+ return 2581;
+ }
+ }
+ else
+ {
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx0xx1xxxxxx000xxx
+ fmlal. */
+ return 2568;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx1xx1xxxxxx000xxx
+ fmlal. */
+ return 2569;
+ }
}
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx0xx1xxxxxx001xxx
+ fmlsl. */
+ return 2582;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx1xx1xxxxxx001xxx
+ fmlsl. */
+ return 2583;
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxxxxx1xxxxxx10xxxx
+ fmlal. */
+ return 3443;
}
}
}
}
- else
+ }
+ else
+ {
+ if (((word >> 3) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -1871,22 +2003,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
usmopa. */
return 2431;
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001100xxxxxxxxxxxxxxxx01xxx
+ umopa. */
+ return 2913;
+ }
}
- else
+ }
+ else
+ {
+ if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 30) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0000001100xxxxxxxxxxxxxxxx10xxx
- bfmops. */
- return 2411;
- }
- else
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001100xxxxxxxxxxxxxxxx1xxxx
+ bfmops. */
+ return 2411;
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
{
@@ -1922,9 +2065,9 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011000xxxxxxx1xxxxxxx10xxx
- bfmlal. */
- return 2509;
+ x10000011000xxxxxxx0xxxxxxx11xxx
+ umlsll. */
+ return 2975;
}
else
{
@@ -1932,121 +2075,157 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011001xxxx0xx1xxxxxxx10xxx
- bfmlal. */
- return 2510;
+ x10000011001xxxx0xx0xxxxxxx11xxx
+ umlsll. */
+ return 2976;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011001xxxx1xx1xxxxxxx10xxx
- bfmlal. */
- return 2511;
+ x10000011001xxxx1xx0xxxxxxx11xxx
+ umlsll. */
+ return 2977;
}
}
}
}
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100001100xxxxxxxxxxxxxxxx10xxx
- usmops. */
- return 2433;
- }
- }
- }
- else
- {
- if (((word >> 4) & 0x1) == 0)
- {
- if (((word >> 29) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
+ else
{
if (((word >> 20) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011000xxxxxxx0xxxxxxx01xxx
- smlsll. */
- return 2966;
- }
- else
- {
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000011001xxxx0xx0xxxxxxx01xxx
- smlsll. */
- return 2967;
+ x10000011000xxxxxxx1xxxxxxx10xxx
+ bfmlal. */
+ return 2509;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000011001xxxx1xx0xxxxxxx01xxx
- smlsll. */
- return 2968;
+ x10000011000xxxxxxx1xxxxxxx11xxx
+ bfmlsl. */
+ return 2517;
}
}
- }
- else
- {
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011000xxxxxxx1xxxxxxx01xxx
- fmlsl. */
- return 2581;
- }
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 5) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011001xxxx0xx1xxxxxxx01xxx
- fmlsl. */
- return 2582;
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx0xx1xxxxxx010xxx
+ bfmlal. */
+ return 2510;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx1xx1xxxxxx010xxx
+ bfmlal. */
+ return 2511;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx0xx1xxxxxx011xxx
+ bfmlsl. */
+ return 2518;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011001xxxx1xx1xxxxxx011xxx
+ bfmlsl. */
+ return 2519;
+ }
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000011001xxxx1xx1xxxxxxx01xxx
- fmlsl. */
- return 2583;
+ x10000011001xxxxxxx1xxxxxx11xxxx
+ fmlal. */
+ return 3442;
}
}
}
}
+ }
+ else
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001100xxxxxxxxxxxxxxxx10xxx
+ usmops. */
+ return 2433;
+ }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx100001100xxxxxxxxxxxxxxxx01xxx
- umopa. */
- return 2913;
+ xx100001100xxxxxxxxxxxxxxxx11xxx
+ umops. */
+ return 2914;
}
}
- else
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
{
if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010100xxxxxxxxxxxxxxxx0xxx
+ fmlall. */
+ return 3449;
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011000xxxxxxx0xxxxxxx11xxx
- umlsll. */
- return 2975;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx1000010100xxxx000xxxxxxxxx0xxx
+ ld1b. */
+ return 2602;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx1000010100xxxx100xxxxxxxxx0xxx
+ ld1b. */
+ return 2603;
+ }
}
else
{
@@ -2054,29 +2233,40 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000011001xxxx0xx0xxxxxxx11xxx
- umlsll. */
- return 2976;
+ xx1000010100xxxx010xxxxxxxxx0xxx
+ ld1w. */
+ return 2626;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000011001xxxx1xx0xxxxxxx11xxx
- umlsll. */
- return 2977;
+ xx1000010100xxxx110xxxxxxxxx0xxx
+ ld1w. */
+ return 2627;
}
}
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011000xxxxxxx1xxxxxxx11xxx
- bfmlsl. */
- return 2517;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx1000010100xxxx001xxxxxxxxx0xxx
+ ld1h. */
+ return 2618;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx1000010100xxxx101xxxxxxxxx0xxx
+ ld1h. */
+ return 2619;
+ }
}
else
{
@@ -2084,89 +2274,31 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000011001xxxx0xx1xxxxxxx11xxx
- bfmlsl. */
- return 2518;
+ xx1000010100xxxx011xxxxxxxxx0xxx
+ ld1d. */
+ return 2610;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000011001xxxx1xx1xxxxxxx11xxx
- bfmlsl. */
- return 2519;
+ xx1000010100xxxx111xxxxxxxxx0xxx
+ ld1d. */
+ return 2611;
}
}
}
}
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100001100xxxxxxxxxxxxxxxx11xxx
- umops. */
- return 2914;
- }
}
- }
- }
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
- {
- if (((word >> 3) & 0x1) == 0)
- {
- if (((word >> 15) & 0x1) == 0)
+ else
{
- if (((word >> 20) & 0x1) == 0)
- {
- if (((word >> 13) & 0x1) == 0)
- {
- if (((word >> 14) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010100xxxx000xxxxxxxxx0xxx
- ld1b. */
- return 2602;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010100xxxx010xxxxxxxxx0xxx
- ld1w. */
- return 2626;
- }
- }
- else
- {
- if (((word >> 14) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010100xxxx001xxxxxxxxx0xxx
- ld1h. */
- return 2618;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010100xxxx011xxxxxxxxx0xxx
- ld1d. */
- return 2610;
- }
- }
- }
- else
+ if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 5) & 0x1) == 0)
{
- if (((word >> 5) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -2178,190 +2310,146 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx0xx1xxxxxx000xxx
- sdot. */
- return 2696;
+ xxx000010101xxxx1xx0xxxxxx000xxx
+ fmla. */
+ return 2562;
}
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx0xx0xxxxxx100xxx
- svdot. */
- return 2855;
+ xxx000010101xxxx0xx1xxxxxx000xxx
+ sdot. */
+ return 2696;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx0xx1xxxxxx100xxx
+ xxx000010101xxxx1xx1xxxxxx000xxx
sdot. */
- return 2702;
+ return 2697;
}
}
}
else
{
- if (((word >> 5) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx0xx0xxxxxx010xxx
- fmls. */
- return 2575;
+ xxx000010101xxxx0xx0xxxxxx100xxx
+ svdot. */
+ return 2855;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx0xx1xxxxxx010xxx
- udot. */
- return 2861;
+ xxx000010101xxxx1xx0xxxxxx100xxx
+ svdot. */
+ return 2856;
}
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx0xx0xxxxxx110xxx
- uvdot. */
- return 2942;
+ xxx000010101xxxx0xx1xxxxxx100xxx
+ sdot. */
+ return 2702;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx0xx1xxxxxx110xxx
- udot. */
- return 2867;
+ xxx000010101xxxx1xx1xxxxxx100xxx
+ sdot. */
+ return 2703;
}
}
}
}
- }
- else
- {
- if (((word >> 20) & 0x1) == 0)
- {
- if (((word >> 13) & 0x1) == 0)
- {
- if (((word >> 14) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010100xxxx100xxxxxxxxx0xxx
- ld1b. */
- return 2603;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010100xxxx110xxxxxxxxx0xxx
- ld1w. */
- return 2627;
- }
- }
- else
- {
- if (((word >> 14) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010100xxxx101xxxxxxxxx0xxx
- ld1h. */
- return 2619;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010100xxxx111xxxxxxxxx0xxx
- ld1d. */
- return 2611;
- }
- }
- }
else
{
- if (((word >> 4) & 0x1) == 0)
+ if (((word >> 5) & 0x1) == 0)
{
- if (((word >> 5) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx1xx0xxxxxx000xxx
- fmla. */
- return 2562;
+ xxx000010101xxxx0xx0xxxxxx010xxx
+ fmls. */
+ return 2575;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx1xx1xxxxxx000xxx
- sdot. */
- return 2697;
+ xxx000010101xxxx1xx0xxxxxx010xxx
+ fmls. */
+ return 2576;
}
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx1xx0xxxxxx100xxx
- svdot. */
- return 2856;
+ xxx000010101xxxx0xx1xxxxxx010xxx
+ udot. */
+ return 2861;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx1xx1xxxxxx100xxx
- sdot. */
- return 2703;
+ xxx000010101xxxx1xx1xxxxxx010xxx
+ udot. */
+ return 2862;
}
}
}
else
{
- if (((word >> 5) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx1xx0xxxxxx010xxx
- fmls. */
- return 2576;
+ xxx000010101xxxx0xx0xxxxxx110xxx
+ uvdot. */
+ return 2942;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx1xx1xxxxxx010xxx
- udot. */
- return 2862;
+ xxx000010101xxxx1xx0xxxxxx110xxx
+ uvdot. */
+ return 2943;
}
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000010101xxxx1xx0xxxxxx110xxx
- uvdot. */
- return 2943;
+ xxx000010101xxxx0xx1xxxxxx110xxx
+ udot. */
+ return 2867;
}
else
{
@@ -2476,11 +2564,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010101xxxx0xxxxxxxxx111xxx
- sudot. */
- return 2843;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010101xxxx0xx0xxxxxx111xxx
+ fdot. */
+ return 3429;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010101xxxx0xx1xxxxxx111xxx
+ sudot. */
+ return 2843;
+ }
}
}
}
@@ -2534,11 +2633,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 5) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000010101xxxx1xxxxxxxxx001xxx
- fdot. */
- return 2540;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010101xxxx1xx0xxxxxx001xxx
+ fdot. */
+ return 3430;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxx000010101xxxx1xx1xxxxxx001xxx
+ fdot. */
+ return 2540;
+ }
}
else
{
@@ -2600,93 +2710,104 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 3) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx000001110xxxxx0xx0xxxxxxx00xxx
- fmla. */
- return 2979;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx000001110xxxxx1xx0xxxxxxx00xxx
- fmla. */
- return 2980;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011100xxxxxxx0xxxxxxx0xxxx
+ fmlal. */
+ return 3441;
}
else
{
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011100xxxxxxx1xxxxxxx00xxx
- smlal. */
- return 2718;
- }
- else
+ if (((word >> 5) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011101xxxx0xx1xxxxxxx00xxx
- smlal. */
- return 2719;
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx0xx00xxxxx000xxx
+ fmla. */
+ return 2979;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx1xx00xxxxx000xxx
+ fmla. */
+ return 2980;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx0xx00xxxxx001xxx
+ sdot. */
+ return 2961;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx1xx00xxxxx001xxx
+ sdot. */
+ return 2962;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011101xxxx1xx1xxxxxxx00xxx
- smlal. */
- return 2720;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx0xx01xxxxx00xxxx
+ fvdotb. */
+ return 3460;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx1xx01xxxxx00xxxx
+ svdot. */
+ return 2969;
+ }
}
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxxxxx0xxxxxx10xxxx
+ fdot. */
+ return 3435;
+ }
}
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 11) & 0x1) == 0)
- {
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx000001110xxxxx0xx00xxxxxx01xxx
- sdot. */
- return 2961;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx000001110xxxxx1xx00xxxxxx01xxx
- sdot. */
- return 2962;
- }
- }
- else
+ if (((word >> 3) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx000001110xxxxxxxx01xxxxxx01xxx
- svdot. */
- return 2969;
+ xx0000011100xxxxxxx1xxxxxxx00xxx
+ smlal. */
+ return 2718;
}
- }
- else
- {
- if (((word >> 20) & 0x1) == 0)
+ else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -2694,25 +2815,58 @@ aarch64_opcode_lookup_1 (uint32_t word)
smlsl. */
return 2734;
}
- else
+ }
+ else
+ {
+ if (((word >> 5) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011101xxxx0xx1xxxxxxx01xxx
- smlsl. */
- return 2735;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx0xx1xxxxxx000xxx
+ smlal. */
+ return 2719;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx1xx1xxxxxx000xxx
+ smlal. */
+ return 2720;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000011101xxxx1xx1xxxxxxx01xxx
- smlsl. */
- return 2736;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx0xx1xxxxxx001xxx
+ smlsl. */
+ return 2735;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx1xx1xxxxxx001xxx
+ smlsl. */
+ return 2736;
+ }
}
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxxxxx1xxxxxx10xxxx
+ fvdot. */
+ return 3459;
+ }
}
}
}
@@ -2738,30 +2892,74 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 3) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 29) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001110xxxxx0xx00xxxxxx10xxx
+ fmls. */
+ return 2981;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001110xxxxx1xx00xxxxxx10xxx
+ fmls. */
+ return 2982;
+ }
+ }
+ else
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001110xxxxx0xx00xxxxxx11xxx
+ udot. */
+ return 2970;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx000001110xxxxx1xx00xxxxxx11xxx
+ udot. */
+ return 2971;
+ }
+ }
+ }
+ else
{
if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx000001110xxxxx0xx0xxxxxxx10xxx
- fmls. */
- return 2981;
+ xx000001110xxxxx0xx01xxxxxx1xxxx
+ fvdott. */
+ return 3461;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx000001110xxxxx1xx0xxxxxxx10xxx
- fmls. */
- return 2982;
+ xx000001110xxxxx1xx01xxxxxx1xxxx
+ uvdot. */
+ return 2978;
}
}
- else
+ }
+ else
+ {
+ if (((word >> 3) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
{
@@ -2791,79 +2989,46 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
}
}
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx100001110xxxxxxxxxxxxxxxx10xxx
- usmops. */
- return 2434;
- }
- }
- else
- {
- if (((word >> 12) & 0x1) == 0)
- {
- if (((word >> 11) & 0x1) == 0)
- {
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001110xxxxx0xx00xxxxxx11xxx
- udot. */
- return 2970;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001110xxxxx1xx00xxxxxx11xxx
- udot. */
- return 2971;
- }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001110xxxxxxxx01xxxxxx11xxx
- uvdot. */
- return 2978;
- }
- }
- else
- {
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000011100xxxxxxx1xxxxxxx11xxx
- umlsl. */
- return 2897;
- }
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xxx000011101xxxx0xx1xxxxxxx11xxx
+ xx0000011100xxxxxxx1xxxxxxx11xxx
umlsl. */
- return 2898;
+ return 2897;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx000011101xxxx1xx1xxxxxxx11xxx
- umlsl. */
- return 2899;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx0xx1xxxxxxx11xxx
+ umlsl. */
+ return 2898;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000011101xxxx1xx1xxxxxxx11xxx
+ umlsl. */
+ return 2899;
+ }
}
}
}
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001110xxxxxxxxxxxxxxxx1xxxx
+ usmops. */
+ return 2434;
+ }
}
}
}
@@ -2905,86 +3070,130 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 2) & 0x1) == 0)
+ if (((word >> 1) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 2) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x10xxxx0xx000xxxxx000xx
- smlall. */
- return 2730;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xx000xxxxx0000x
+ smlall. */
+ return 2730;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xx000xxxxx0000x
+ smlall. */
+ return 2731;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x11xxxx0xx000xxxxx000xx
- smlall. */
- return 2731;
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx000xxxx00000x
+ smlall. */
+ return 2732;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx000xxxx00000x
+ smlall. */
+ return 2733;
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx000xxxx10000x
+ fmlall. */
+ return 3455;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx000xxxx10000x
+ fmlall. */
+ return 3456;
+ }
+ }
}
}
else
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx00xx000xxxxx000xx
- smlall. */
- return 2732;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xx000xxxxx0010x
+ usmlall. */
+ return 2935;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xx000xxxxx0010x
+ usmlall. */
+ return 2936;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx000xxxxx000xx
- smlall. */
- return 2733;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx000xxxxx0010x
+ usmlall. */
+ return 2937;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx000xxxxx0010x
+ usmlall. */
+ return 2938;
+ }
}
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x10xxxx0xx000xxxxx001xx
- usmlall. */
- return 2935;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x11xxxx0xx000xxxxx001xx
- usmlall. */
- return 2936;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx10xxxx0xx000xxxxx00x1x
+ fmlall. */
+ return 3453;
}
else
{
- if (((word >> 16) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx00xx000xxxxx001xx
- usmlall. */
- return 2937;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx000xxxxx001xx
- usmlall. */
- return 2938;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx000xxxxx00x1x
+ fmlall. */
+ return 3454;
}
}
}
@@ -3011,48 +3220,23 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 16) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx00xx100xxxxx00xxx
- fdot. */
- return 2543;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxxx00xxx
- fdot. */
- return 2544;
- }
- }
- }
- }
- else
- {
- if (((word >> 12) & 0x1) == 0)
- {
- if (((word >> 22) & 0x1) == 0)
- {
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 5) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 16) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000010010xxxx0xx010xxxxx00xxx
- fmlal. */
- return 2571;
+ x10000011x1xxxx00xx100xxxx000xxx
+ fdot. */
+ return 2543;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000010011xxxx0xx010xxxxx00xxx
- fmlal. */
- return 2572;
+ x10000011x1xxxx10xx100xxxx000xxx
+ fdot. */
+ return 2544;
}
}
else
@@ -3061,61 +3245,152 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001101xxxx00xx010xxxxx00xxx
- fmlal. */
- return 2573;
+ x10000011x1xxxx00xx100xxxx100xxx
+ fdot. */
+ return 3439;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001101xxxx10xx010xxxxx00xxx
- fmlal. */
- return 2574;
+ x10000011x1xxxx10xx100xxxx100xxx
+ fdot. */
+ return 3440;
}
}
}
- else
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 2) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010110xxxx0xx010xxxxx00xxx
- smlal. */
- return 2722;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010010xxxx0xx010xxxxx000xx
+ fmlal. */
+ return 2571;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010011xxxx0xx010xxxxx000xx
+ fmlal. */
+ return 2572;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010111xxxx0xx010xxxxx00xxx
- smlal. */
- return 2723;
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx00xx010xxxx0000xx
+ fmlal. */
+ return 2573;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx10xx010xxxx0000xx
+ fmlal. */
+ return 2574;
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx00xx010xxxx1000xx
+ fmlal. */
+ return 3447;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001101xxxx10xx010xxxx1000xx
+ fmlal. */
+ return 3448;
+ }
+ }
}
}
else
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001111xxxx00xx010xxxxx00xxx
- smlal. */
- return 2724;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010110xxxx0xx010xxxxx000xx
+ smlal. */
+ return 2722;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010111xxxx0xx010xxxxx000xx
+ smlal. */
+ return 2723;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001111xxxx10xx010xxxxx00xxx
- smlal. */
- return 2725;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001111xxxx00xx010xxxxx000xx
+ smlal. */
+ return 2724;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001111xxxx10xx010xxxxx000xx
+ smlal. */
+ return 2725;
+ }
}
}
}
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx10xxxx0xx010xxxxx001xx
+ fmlal. */
+ return 3445;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx010xxxxx001xx
+ fmlal. */
+ return 3446;
+ }
+ }
}
else
{
@@ -3168,11 +3443,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 2) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx0xx001xxxxx000xx
- smlall. */
- return 2729;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx10xxxx0xx001xxxxx000xx
+ smlall. */
+ return 2729;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx001xxxxx000xx
+ fmlall. */
+ return 3452;
+ }
}
else
{
@@ -3229,40 +3515,73 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001x01xxxxx0xx011xxxxx00xxx
- fmlal. */
- return 2570;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x010xxxx0xx011xxxxx00xxx
+ fmlal. */
+ return 2570;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001x110xxxx0xx011xxxxx00xxx
+ smlal. */
+ return 2721;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001x11xxxxx0xx011xxxxx00xxx
- smlal. */
- return 2721;
+ x1000001xx11xxxx0xx011xxxxx00xxx
+ fmlal. */
+ return 3444;
}
}
else
{
if (((word >> 16) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxx00xx111xxxxx00xxx
- fadd. */
- return 2529;
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx0x00xx111xxxxx00xxx
+ fadd. */
+ return 2529;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx1x00xx111xxxxx00xxx
+ fadd. */
+ return 3393;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxx10xx111xxxxx00xxx
- fadd. */
- return 2530;
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx0x10xx111xxxxx00xxx
+ fadd. */
+ return 2530;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx1x10xx111xxxxx00xxx
+ fadd. */
+ return 3394;
+ }
}
}
}
@@ -3360,21 +3679,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 5) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx00xx100xxxxx10xxx
- bfdot. */
- return 2507;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx100xxxx010xxx
+ bfdot. */
+ return 2507;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxx010xxx
+ bfdot. */
+ return 2508;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000011x1xxxx10xx100xxxxx10xxx
- bfdot. */
- return 2508;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx100xxxx110xxx
+ fdot. */
+ return 3433;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxx110xxx
+ fdot. */
+ return 3434;
+ }
}
}
}
@@ -3615,42 +3956,64 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x10xxxx0xxx00xxxxx01xxx
- smlsll. */
- return 2746;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xx000xxxxx01xxx
+ smlsll. */
+ return 2746;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xx000xxxxx01xxx
+ smlsll. */
+ return 2747;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x11xxxx0xxx00xxxxx01xxx
- smlsll. */
- return 2747;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx000xxxxx01xxx
+ smlsll. */
+ return 2748;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx000xxxxx01xxx
+ smlsll. */
+ return 2749;
+ }
}
}
else
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx00xxx00xxxxx01xxx
- smlsll. */
- return 2748;
+ x1000001xx10xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3437;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx10xxx00xxxxx01xxx
- smlsll. */
- return 2749;
+ x1000001xx11xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3438;
}
}
}
@@ -3907,19 +4270,41 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 16) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxx00xx111xxxxx01xxx
- fsub. */
- return 2597;
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx0x00xx111xxxxx01xxx
+ fsub. */
+ return 2597;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx1x00xx111xxxxx01xxx
+ fsub. */
+ return 3395;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxx10xx111xxxxx01xxx
- fsub. */
- return 2598;
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx0x10xx111xxxxx01xxx
+ fsub. */
+ return 2598;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xx1x10xx111xxxxx01xxx
+ fsub. */
+ return 3396;
+ }
}
}
}
@@ -3931,42 +4316,64 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x10xxxx0xxx00xxxxx11xxx
- umlsll. */
- return 2909;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xx000xxxxx11xxx
+ umlsll. */
+ return 2909;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xx000xxxxx11xxx
+ umlsll. */
+ return 2910;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10000010x11xxxx0xxx00xxxxx11xxx
- umlsll. */
- return 2910;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx000xxxxx11xxx
+ umlsll. */
+ return 2911;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx000xxxxx11xxx
+ umlsll. */
+ return 2912;
+ }
}
}
else
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx00xxx00xxxxx11xxx
- umlsll. */
- return 2911;
+ x1000001xx10xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3431;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10000011x1xxxx10xxx00xxxxx11xxx
- umlsll. */
- return 2912;
+ x1000001xx11xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3432;
}
}
}
@@ -17268,7 +17675,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3412;
+ return 3416;
}
}
else
@@ -17277,7 +17684,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3414;
+ return 3418;
}
}
else
@@ -17318,7 +17725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3424;
+ return 3428;
}
}
else
@@ -17351,7 +17758,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3410;
+ return 3414;
}
}
else
@@ -17422,7 +17829,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3415;
+ return 3419;
}
}
else
@@ -17431,7 +17838,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3411;
+ return 3415;
}
}
else
@@ -17440,7 +17847,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3416;
+ return 3420;
}
}
else
@@ -17449,7 +17856,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3417;
+ return 3421;
}
}
else
@@ -17476,7 +17883,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3413;
+ return 3417;
}
}
else
@@ -17494,7 +17901,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3420;
+ return 3424;
}
}
else
@@ -17503,7 +17910,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3423;
+ return 3427;
}
}
else
@@ -17536,7 +17943,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3409;
+ return 3413;
}
}
else
@@ -17545,7 +17952,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3418;
+ return 3422;
}
}
else
@@ -17577,7 +17984,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3422;
+ return 3426;
}
}
else
@@ -17891,7 +18298,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3419;
+ return 3423;
}
else
{
@@ -17899,7 +18306,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3421;
+ return 3425;
}
}
else
@@ -26159,7 +26566,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x00xxxxxx10001xxxxxxxxxx
fmlallbb. */
- return 3401;
+ return 3405;
}
else
{
@@ -26167,7 +26574,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x00xxxxxx10001xxxxxxxxxx
fmlalltb. */
- return 3403;
+ return 3407;
}
}
else
@@ -26178,7 +26585,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110x10xxxxxx10001xxxxxxxxxx
fmlallbt. */
- return 3402;
+ return 3406;
}
else
{
@@ -26186,7 +26593,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110x10xxxxxx10001xxxxxxxxxx
fmlalltt. */
- return 3404;
+ return 3408;
}
}
}
@@ -26434,7 +26841,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110x00xxxxxx11111xxxxxxxxxx
fdot. */
- return 3393;
+ return 3397;
}
else
{
@@ -26444,7 +26851,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x001110010xxxxxx11111xxxxxxxxxx
fdot. */
- return 3395;
+ return 3399;
}
else
{
@@ -26454,7 +26861,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00001110110xxxxxx11111xxxxxxxxxx
fmlalb. */
- return 3397;
+ return 3401;
}
else
{
@@ -26462,7 +26869,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01001110110xxxxxx11111xxxxxxxxxx
fmlalt. */
- return 3398;
+ return 3402;
}
}
}
@@ -31911,7 +32318,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111100xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3394;
+ return 3398;
}
else
{
@@ -31941,7 +32348,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx00111101xxxxxx0000x0xxxxxxxxxx
fdot. */
- return 3396;
+ return 3400;
}
else
{
@@ -31951,7 +32358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x000111111xxxxxx0000x0xxxxxxxxxx
fmlalb. */
- return 3399;
+ return 3403;
}
else
{
@@ -31959,7 +32366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100111111xxxxxx0000x0xxxxxxxxxx
fmlalt. */
- return 3400;
+ return 3404;
}
}
}
@@ -32501,7 +32908,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x010111100xxxxxx1000x0xxxxxxxxxx
fmlallbb. */
- return 3405;
+ return 3409;
}
else
{
@@ -32509,7 +32916,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x110111100xxxxxx1000x0xxxxxxxxxx
fmlalltb. */
- return 3407;
+ return 3411;
}
}
else
@@ -32540,7 +32947,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0101111x1xxxxxx1000x0xxxxxxxxxx
fmlallbt. */
- return 3406;
+ return 3410;
}
else
{
@@ -32548,7 +32955,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1101111x1xxxxxx1000x0xxxxxxxxxx
fmlalltt. */
- return 3408;
+ return 3412;
}
}
}
@@ -34029,16 +34436,17 @@ aarch64_extract_operand (const aarch64_operand *self,
case 245:
case 252:
case 253:
- case 260:
+ case 254:
case 261:
case 262:
case 263:
+ case 264:
return aarch64_ext_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 295:
- case 297:
+ case 300:
+ case 302:
return aarch64_ext_none (self, info, code, inst, errors);
case 11:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -34058,7 +34466,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 299:
+ case 304:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -34066,9 +34474,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 226:
case 227:
case 230:
- case 264:
case 265:
- case 280:
+ case 266:
case 281:
case 282:
case 283:
@@ -34081,6 +34488,11 @@ aarch64_extract_operand (const aarch64_operand *self,
case 290:
case 291:
case 292:
+ case 293:
+ case 294:
+ case 295:
+ case 296:
+ case 297:
return aarch64_ext_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -34129,13 +34541,13 @@ aarch64_extract_operand (const aarch64_operand *self,
case 206:
case 207:
case 208:
- case 266:
- case 293:
- case 294:
- case 296:
+ case 267:
case 298:
+ case 299:
+ case 301:
case 303:
- case 304:
+ case 308:
+ case 309:
return aarch64_ext_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -34285,7 +34697,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 198:
case 199:
case 200:
- case 279:
+ case 280:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
case 213:
case 214:
@@ -34312,7 +34724,7 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sve_index (self, info, code, inst, errors);
case 240:
case 242:
- case 259:
+ case 260:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
case 243:
case 244:
@@ -34320,48 +34732,48 @@ aarch64_extract_operand (const aarch64_operand *self,
case 247:
case 248:
case 249:
- case 258:
+ case 259:
return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
case 250:
case 251:
return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
- case 254:
- case 256:
- case 267:
- return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
case 255:
case 257:
- return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 268:
+ return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 256:
+ case 258:
+ return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 269:
case 270:
case 271:
case 272:
case 273:
case 274:
- return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 275:
- return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 276:
- return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 277:
- return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
case 278:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 279:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
- case 300:
- case 301:
- case 302:
- return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
case 305:
case 306:
case 307:
- return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
- case 308:
- case 309:
+ return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
case 310:
case 311:
- return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 312:
+ return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
+ case 313:
+ case 314:
+ case 315:
+ case 316:
+ return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 317:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
@@ -276,6 +276,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_1b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_1b}, "an SME ZA tile ZA0-ZA1"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
@@ -306,10 +307,14 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5b}, "a shift-right immediate operand"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10, FLD_imm1_3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10, FLD_imm2_1}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm1_2}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm1_3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm2_1}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10, FLD_imm2_2}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10, FLD_imm1_3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_15, FLD_imm3_10}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"},
@@ -60,6 +60,7 @@ enum aarch64_field_kind
FLD_SME_V,
FLD_SME_VL_10,
FLD_SME_VL_13,
+ FLD_SME_ZAda_1b,
FLD_SME_ZAda_2b,
FLD_SME_ZAda_3b,
FLD_SME_Zdn2,
@@ -150,6 +151,7 @@ enum aarch64_field_kind
FLD_hw,
FLD_imm1_0,
FLD_imm1_2,
+ FLD_imm1_3,
FLD_imm1_8,
FLD_imm1_10,
FLD_imm1_14,
@@ -157,6 +159,7 @@ enum aarch64_field_kind
FLD_imm1_16,
FLD_imm2_0,
FLD_imm2_1,
+ FLD_imm2_2,
FLD_imm2_8,
FLD_imm2_10,
FLD_imm2_12,
@@ -250,6 +250,7 @@ const aarch64_field fields[] =
{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
{ 10, 1 }, /* SME_VL_10: VLx2 or VLx4, bit [10]. */
{ 13, 1 }, /* SME_VL_13: VLx2 or VLx4, bit [13]. */
+ { 0, 1 }, /* SME_ZAda_1b: tile ZA0-ZA1. */
{ 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
{ 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */
@@ -340,6 +341,7 @@ const aarch64_field fields[] =
{ 21, 2 }, /* hw: in move wide constant instructions. */
{ 0, 1 }, /* imm1_0: general immediate in bits [0]. */
{ 2, 1 }, /* imm1_2: general immediate in bits [2]. */
+ { 3, 1 }, /* imm1_3: general immediate in bits [3]. */
{ 8, 1 }, /* imm1_8: general immediate in bits [8]. */
{ 10, 1 }, /* imm1_10: general immediate in bits [10]. */
{ 14, 1 }, /* imm1_14: general immediate in bits [14]. */
@@ -347,6 +349,7 @@ const aarch64_field fields[] =
{ 16, 1 }, /* imm1_16: general immediate in bits [16]. */
{ 0, 2 }, /* imm2_0: general immediate in bits [1:0]. */
{ 1, 2 }, /* imm2_1: general immediate in bits [2:1]. */
+ { 2, 2 }, /* imm2_2: general immediate in bits [3:2]. */
{ 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */
{ 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */
{ 12, 2 }, /* imm2_12: 2-bit immediate, bits [13:12] */
@@ -1875,10 +1878,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SME_Zm_INDEX1:
case AARCH64_OPND_SME_Zm_INDEX2:
+ case AARCH64_OPND_SME_Zm_INDEX2_3:
case AARCH64_OPND_SME_Zm_INDEX3_1:
case AARCH64_OPND_SME_Zm_INDEX3_2:
+ case AARCH64_OPND_SME_Zm_INDEX3_3:
case AARCH64_OPND_SME_Zm_INDEX3_10:
case AARCH64_OPND_SME_Zm_INDEX4_1:
+ case AARCH64_OPND_SME_Zm_INDEX4_2:
+ case AARCH64_OPND_SME_Zm_INDEX4_3:
case AARCH64_OPND_SME_Zm_INDEX4_10:
size = get_operand_fields_width (get_operand_from_code (type)) - 4;
if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15,
@@ -4237,11 +4244,15 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_Zn_INDEX:
case AARCH64_OPND_SME_Zm_INDEX1:
case AARCH64_OPND_SME_Zm_INDEX2:
+ case AARCH64_OPND_SME_Zm_INDEX2_3:
case AARCH64_OPND_SME_Zm_INDEX3_1:
case AARCH64_OPND_SME_Zm_INDEX3_2:
+ case AARCH64_OPND_SME_Zm_INDEX3_3:
case AARCH64_OPND_SME_Zm_INDEX3_10:
case AARCH64_OPND_SVE_Zn_5_INDEX:
case AARCH64_OPND_SME_Zm_INDEX4_1:
+ case AARCH64_OPND_SME_Zm_INDEX4_2:
+ case AARCH64_OPND_SME_Zm_INDEX4_3:
case AARCH64_OPND_SME_Zm_INDEX4_10:
case AARCH64_OPND_SME_Zn_INDEX1_16:
case AARCH64_OPND_SME_Zn_INDEX2_15:
@@ -4258,6 +4269,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
style_imm (styler, "%" PRIi64, opnd->reglane.index));
break;
+ case AARCH64_OPND_SME_ZAda_1b:
case AARCH64_OPND_SME_ZAda_2b:
case AARCH64_OPND_SME_ZAda_3b:
snprintf (buf, size, "%s",
@@ -1698,6 +1698,10 @@
{ \
QLF3(S_H,P_M,S_D), \
}
+#define OP_SVE_HMMBB \
+{ \
+ QLF5(S_H,P_M,P_M,S_B,S_B) \
+}
#define OP_SVE_HMS \
{ \
QLF3(S_H,P_M,S_S), \
@@ -2737,6 +2741,10 @@ FEATURE_SET_OR_2(fp8dot4_sve, AARCH64_FEATURES (2, FP8DOT4, SVE2),
AARCH64_FEATURE (SSVE_FP8DOT4))
FEATURE_SET_OR_2(fp8dot2_sve, AARCH64_FEATURES (2, FP8DOT2, SVE2),
AARCH64_FEATURE (SSVE_FP8DOT2))
+FEATURE_SET_OR_1(sme_f8f32, AARCH64_FEATURES (2, SME_F8F32, SME2))
+FEATURE_SET_OR_1(sme_f8f16, AARCH64_FEATURES (2, SME_F8F16, SME2))
+//TODO: Update to include SME_F16F16 once this feature is added to Binutils:
+FEATURE_SET_OR_1(sme_f16f16_f8f16, AARCH64_FEATURES (2, SME_F8F16, SME2))
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2819,6 +2827,9 @@ FEATURE_SET_OR_2(fp8dot2_sve, AARCH64_FEATURES (2, FP8DOT2, SVE2),
#define FP8FMA_SVE &aarch64_feature_fp8fma_sve
#define FP8DOT4_SVE &aarch64_feature_fp8dot4_sve
#define FP8DOT2_SVE &aarch64_feature_fp8dot2_sve
+#define SME_F8F32 &aarch64_feature_sme_f8f32
+#define SME_F8F16 &aarch64_feature_sme_f8f16
+#define SME_F16F16_F8F16 &aarch64_feature_sme_f16f16_f8f16
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -3029,6 +3040,12 @@ FEATURE_SET_OR_2(fp8dot2_sve, AARCH64_FEATURES (2, FP8DOT2, SVE2),
{ NAME, OPCODE, MASK, CLASS, 0, FP8DOT4_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
#define FP8DOT2_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, FP8DOT2_SVE, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
+#define SME_F8F32_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SME_F8F32, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL }
+#define SME_F8F16_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SME_F8F16, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL }
+#define SME_F16F16_F8F16_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS) \
+ { NAME, OPCODE, MASK, CLASS, 0, SME_F16F16_F8F16, OPS, QUALS, F_STRICT | FLAGS, CONSTRAINTS, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -6614,6 +6631,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
LUT_SVE2_INSN ("luti4", 0x4520b400, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(2), 0),
LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0),
+ SME_F16F16_F8F16_INSNC("fadd", 0xc1a41c00, 0xffff9c38, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD (2), 0),
+ SME_F16F16_F8F16_INSNC("fadd", 0xc1a51c00, 0xffff9c78, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_HH, F_OD (4), 0),
+ SME_F16F16_F8F16_INSNC("fsub", 0xc1a41c08, 0xffff9c38, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD (2), 0),
+ SME_F16F16_F8F16_INSNC("fsub", 0xc1a51c08, 0xffff9c78, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_HH, F_OD (4), 0),
+
FP8DOT4_INSN("fdot", 0x0e00fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
FP8DOT4_INSN("fdot", 0x0f000000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
FP8DOT2_INSN("fdot", 0x0e40fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOTH, F_SIZEQ),
@@ -6648,6 +6670,40 @@ const struct aarch64_opcode aarch64_opcode_table[] =
FP8FMA_SVE_INSNC("fmlalt", 0x64a09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
FP8FMA_SVE_INSNC("fmlalt", 0x64a05000, 0xffe0f000, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_10_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ SME_F8F32_INSNC("fdot", 0xc1500038, 0xfff09038, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_VVV_S_B, F_OD (2), 0),
+ SME_F8F32_INSNC("fdot", 0xc1508008, 0xfff09078, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_VVV_S_B, F_OD (4), 0),
+ SME_F8F32_INSNC("fdot", 0xc1201018, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_S_B, F_OD (2), 0),
+ SME_F8F32_INSNC("fdot", 0xc1301018, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_S_B, F_OD (4), 0),
+ SME_F8F32_INSNC("fdot", 0xc1a01030, 0xffe19c38, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_S_B, F_OD (2), 0),
+ SME_F8F32_INSNC("fdot", 0xc1a11030, 0xffe39c78, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_S_B, F_OD (4), 0),
+ SME_F8F16_INSNC("fdot", 0xc1d00020, 0xfff09030, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_VVV_H_B, F_OD (2), 0),
+ SME_F8F16_INSNC("fdot", 0xc1109040, 0xfff09070, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX3_3), OP_SVE_VVV_H_B, F_OD (4), 0),
+ SME_F8F16_INSNC("fdot", 0xc1201008, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_H_B, F_OD (2), 0),
+ SME_F8F16_INSNC("fdot", 0xc1301008, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_H_B, F_OD (4), 0),
+ SME_F8F16_INSNC("fdot", 0xc1a01020, 0xffe19c38, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_H_B, F_OD (2), 0),
+ SME_F8F16_INSNC("fdot", 0xc1a11020, 0xffe39c78, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_H_B, F_OD (4), 0),
+ SME_F8F16_INSNC("fmlal", 0xc1c00000, 0xfff01010, sme_misc, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm_INDEX4_3), OP_SVE_VVV_H_B, 0, 0),
+ SME_F8F16_INSNC("fmlal", 0xc1901030, 0xfff09030, sme_misc, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zm_INDEX4_2), OP_SVE_VVV_H_B, F_OD (2), 0),
+ SME_F8F16_INSNC("fmlal", 0xc1909020, 0xfff09070, sme_misc, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zm_INDEX4_2), OP_SVE_VVV_H_B, F_OD (4), 0),
+ SME_F8F16_INSNC("fmlal", 0xc1300c00, 0xfff09c18, sme_misc, OP3 (SME_ZA_array_off3x2, SVE_Zn, SME_Zm), OP_SVE_VVV_H_B, 0, 0),
+ SME_F8F16_INSNC("fmlal", 0xc1200804, 0xfff09c1c, sme_misc, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_VVV_H_B, F_OD (2), 0),
+ SME_F8F16_INSNC("fmlal", 0xc1300804, 0xfff09c1c, sme_misc, OP3 (SME_ZA_array_off2x2, SVE_ZnxN, SME_Zm), OP_SVE_VVV_H_B, F_OD (4), 0),
+ SME_F8F16_INSNC("fmlal", 0xc1a00820, 0xffe19c3c, sme_misc, OP3 (SME_ZA_array_off2x2, SME_Znx2, SME_Zmx2), OP_SVE_VVV_H_B, F_OD (2), 0),
+ SME_F8F16_INSNC("fmlal", 0xc1a10820, 0xffe39c7c, sme_misc, OP3 (SME_ZA_array_off2x2, SME_Znx4, SME_Zmx4), OP_SVE_VVV_H_B, F_OD (4), 0),
+ SME_F8F32_INSNC("fmlall", 0xc1400000, 0xfff0001c, sme_misc, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm_INDEX4_10), OP_SVE_VVV_S_B, 0, 0),
+ SME_F8F32_INSNC("fmlall", 0xc1900020, 0xfff09038, sme_misc, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zm_INDEX4_1), OP_SVE_VVV_S_B, F_OD (2), 0),
+ SME_F8F32_INSNC("fmlall", 0xc1108040, 0xfff09078, sme_misc, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_VVV_S_B, F_OD (4), 0),
+ SME_F8F32_INSNC("fmlall", 0xc1300400, 0xfff09c1c, sme_misc, OP3 (SME_ZA_array_off2x4, SVE_Zn, SME_Zm), OP_SVE_VVV_S_B, 0, 0),
+ SME_F8F32_INSNC("fmlall", 0xc1200002, 0xfff09c1e, sme_misc, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_S_B, F_OD (2), 0),
+ SME_F8F32_INSNC("fmlall", 0xc1300002, 0xfff09c1e, sme_misc, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_VVV_S_B, F_OD (4), 0),
+ SME_F8F32_INSNC("fmlall", 0xc1a00020, 0xffe19c3e, sme_misc, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zmx2), OP_SVE_VVV_S_B, F_OD (2), 0),
+ SME_F8F32_INSNC("fmlall", 0xc1a10020, 0xffe39c7e, sme_misc, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_S_B, F_OD (4), 0),
+ SME_F8F16_INSNC("fmopa", 0x80a00008, 0xffe0001e, sme_misc, OP5 (SME_ZAda_1b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_HMMBB, 0, 0),
+ SME_F8F32_INSNC("fmopa", 0x80a00000, 0xffe0001c, sme_misc, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
+ SME_F8F16_INSNC("fvdot", 0xc1d01020, 0xfff09030, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX3_3), OP_SVE_VVV_H_B, F_OD (2), 0),
+ SME_F8F32_INSNC("fvdotb", 0xc1d00800, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4), 0),
+ SME_F8F32_INSNC("fvdott", 0xc1d00810, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4), 0),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
@@ -7189,6 +7245,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx4_STRIDED", \
4 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt2), \
"a list of SVE vector registers") \
+ Y(SVE_REG, regno, "SME_ZAda_1b", 0, F(FLD_SME_ZAda_1b), \
+ "an SME ZA tile ZA0-ZA1") \
Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \
"an SME ZA tile ZA0-ZA3") \
Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \
@@ -7257,18 +7315,30 @@ const struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_SME_Zm, FLD_imm1_10), "an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \
F(FLD_SME_Zm, FLD_imm2_10), "an indexed SVE vector register") \
+ Y(SVE_REG, simple_index, "SME_Zm_INDEX2_3", 0, \
+ F(FLD_SME_Zm, FLD_imm1_10, FLD_imm1_3), \
+ "an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zm_INDEX3_1", 0, \
F(FLD_SME_Zm, FLD_imm1_10, FLD_imm2_1), \
"an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zm_INDEX3_2", 0, \
F(FLD_SME_Zm, FLD_imm2_10, FLD_imm1_2), \
"an indexed SVE vector register") \
+ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_3", 0, \
+ F(FLD_SME_Zm, FLD_imm2_10, FLD_imm1_3), \
+ "an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zm_INDEX3_10", 0, \
F(FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10), \
"an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zm_INDEX4_1", 0, \
F(FLD_SME_Zm, FLD_imm2_10, FLD_imm2_1), \
"an indexed SVE vector register") \
+ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_2", 0, \
+ F(FLD_SME_Zm, FLD_imm2_10, FLD_imm2_2), \
+ "an indexed SVE vector register") \
+ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_3", 0, \
+ F(FLD_SME_Zm, FLD_imm1_15, FLD_imm2_10, FLD_imm1_3), \
+ "an indexed SVE vector register") \
Y(SVE_REG, simple_index, "SME_Zm_INDEX4_10", 0, \
F(FLD_SME_Zm, FLD_imm1_15, FLD_imm3_10), \
"an indexed SVE vector register") \