diff mbox series

[v4,07/11] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands (regenerated files).

Message ID 20240621152331.2155296-8-srinath.parvathaneni@arm.com
State Committed
Headers
Series aarch64: Fix the FEAT_SVE2p1 related issues. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Build passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Test passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Test passed

Commit Message

Srinath Parvathaneni June 21, 2024, 3:23 p.m. UTC 
  Hi,

This patch includes the regenerated files for
[Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.

Regards,
Srinath.
---
 opcodes/aarch64-asm-2.c | 142 ++++++++++++++++++++--------------------
 opcodes/aarch64-dis-2.c | 139 +++++++++++++++++++--------------------
 opcodes/aarch64-opc-2.c |   4 +-
 3 files changed, 139 insertions(+), 146 deletions(-)
diff mbox series

Patch

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index ceb21df2a98..739a3d6e4bd 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -654,7 +654,6 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 122:
     case 123:
     case 124:
-    case 182:
     case 183:
     case 184:
     case 185:
@@ -668,30 +667,31 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 193:
     case 194:
     case 195:
-    case 211:
+    case 196:
     case 212:
     case 213:
     case 214:
-    case 223:
+    case 215:
     case 224:
     case 225:
     case 226:
     case 227:
-    case 237:
-    case 241:
-    case 245:
-    case 252:
+    case 228:
+    case 238:
+    case 242:
+    case 246:
     case 253:
-    case 260:
+    case 254:
     case 261:
     case 262:
     case 263:
+    case 264:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 6:
     case 118:
     case 119:
-    case 295:
-    case 297:
+    case 296:
+    case 298:
       return aarch64_ins_none (self, info, code, inst, errors);
     case 17:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -705,17 +705,16 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 36:
     case 37:
     case 38:
-    case 299:
+    case 300:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 39:
     case 40:
     case 41:
-    case 228:
     case 229:
-    case 232:
-    case 264:
+    case 230:
+    case 233:
     case 265:
-    case 280:
+    case 266:
     case 281:
     case 282:
     case 283:
@@ -728,6 +727,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 290:
     case 291:
     case 292:
+    case 293:
       return aarch64_ins_simple_index (self, info, code, inst, errors);
     case 42:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -766,9 +766,8 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 91:
     case 117:
     case 121:
-    case 179:
-    case 181:
-    case 202:
+    case 180:
+    case 182:
     case 203:
     case 204:
     case 205:
@@ -777,13 +776,14 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 208:
     case 209:
     case 210:
-    case 266:
-    case 293:
+    case 211:
+    case 267:
     case 294:
-    case 296:
-    case 298:
-    case 303:
+    case 295:
+    case 297:
+    case 299:
     case 304:
+    case 305:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 51:
     case 52:
@@ -793,10 +793,10 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 55:
       return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
     case 59:
-    case 169:
+    case 170:
       return aarch64_ins_fpimm (self, info, code, inst, errors);
     case 77:
-    case 177:
+    case 178:
       return aarch64_ins_limm (self, info, code, inst, errors);
     case 78:
       return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -806,11 +806,11 @@  aarch64_insert_operand (const aarch64_operand *self,
       return aarch64_ins_fbits (self, info, code, inst, errors);
     case 82:
     case 83:
-    case 174:
+    case 175:
       return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
     case 84:
-    case 173:
-    case 175:
+    case 174:
+    case 176:
       return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
     case 85:
     case 86:
@@ -887,8 +887,8 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 149:
     case 150:
     case 151:
-      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 152:
+      return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 153:
     case 154:
     case 155:
@@ -896,114 +896,112 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 157:
     case 158:
     case 159:
-      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 160:
+      return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 161:
     case 162:
     case 163:
-      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 164:
-      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 165:
-      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
     case 166:
-      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
     case 167:
-      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+      return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
     case 168:
+      return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+    case 169:
       return aarch64_ins_sve_asimm (self, info, code, inst, errors);
-    case 170:
-      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 171:
-      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+      return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
     case 172:
+      return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+    case 173:
       return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
-    case 176:
+    case 177:
       return aarch64_ins_inv_limm (self, info, code, inst, errors);
-    case 178:
+    case 179:
       return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
-    case 180:
+    case 181:
       return aarch64_ins_sve_scale (self, info, code, inst, errors);
-    case 196:
     case 197:
     case 198:
-      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 199:
+      return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
     case 200:
     case 201:
-    case 279:
+    case 202:
+    case 280:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 215:
     case 216:
     case 217:
     case 218:
-      return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
     case 219:
+      return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
     case 220:
     case 221:
     case 222:
+    case 223:
       return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
-    case 230:
     case 231:
-    case 233:
+    case 232:
     case 234:
     case 235:
     case 236:
+    case 237:
       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-    case 238:
     case 239:
-      return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 240:
-    case 242:
-    case 259:
-    case 305:
-    case 306:
-    case 307:
-      return aarch64_ins_sve_reglist (self, info, code, inst, errors);
+      return aarch64_ins_sve_index (self, info, code, inst, errors);
+    case 241:
     case 243:
+    case 260:
+      return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     case 244:
-    case 246:
+    case 245:
     case 247:
     case 248:
     case 249:
-    case 258:
-      return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
     case 250:
+    case 259:
+      return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
     case 251:
+    case 252:
       return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
-    case 254:
-    case 256:
-    case 267:
-      return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
     case 255:
     case 257:
-      return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
     case 268:
+      return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+    case 256:
+    case 258:
+      return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
     case 269:
     case 270:
     case 271:
     case 272:
     case 273:
     case 274:
-      return aarch64_ins_sme_za_array (self, info, code, inst, errors);
     case 275:
-      return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+      return aarch64_ins_sme_za_array (self, info, code, inst, errors);
     case 276:
-      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+      return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
     case 277:
-      return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
     case 278:
+      return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+    case 279:
       return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
-    case 300:
     case 301:
     case 302:
+    case 303:
       return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
+    case 306:
+    case 307:
     case 308:
     case 309:
-    case 310:
-    case 311:
       return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
-    case 312:
+    case 310:
       return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 6d381879066..e19238ab31a 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -33651,7 +33651,6 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 122:
     case 123:
     case 124:
-    case 182:
     case 183:
     case 184:
     case 185:
@@ -33665,30 +33664,31 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 193:
     case 194:
     case 195:
-    case 211:
+    case 196:
     case 212:
     case 213:
     case 214:
-    case 223:
+    case 215:
     case 224:
     case 225:
     case 226:
     case 227:
-    case 237:
-    case 241:
-    case 245:
-    case 252:
+    case 228:
+    case 238:
+    case 242:
+    case 246:
     case 253:
-    case 260:
+    case 254:
     case 261:
     case 262:
     case 263:
+    case 264:
       return aarch64_ext_regno (self, info, code, inst, errors);
     case 6:
     case 118:
     case 119:
-    case 295:
-    case 297:
+    case 296:
+    case 298:
       return aarch64_ext_none (self, info, code, inst, errors);
     case 11:
       return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -33707,17 +33707,16 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 36:
     case 37:
     case 38:
-    case 299:
+    case 300:
       return aarch64_ext_reglane (self, info, code, inst, errors);
     case 39:
     case 40:
     case 41:
-    case 228:
     case 229:
-    case 232:
-    case 264:
+    case 230:
+    case 233:
     case 265:
-    case 280:
+    case 266:
     case 281:
     case 282:
     case 283:
@@ -33730,6 +33729,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 290:
     case 291:
     case 292:
+    case 293:
       return aarch64_ext_simple_index (self, info, code, inst, errors);
     case 42:
       return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -33769,9 +33769,8 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 91:
     case 117:
     case 121:
-    case 179:
-    case 181:
-    case 202:
+    case 180:
+    case 182:
     case 203:
     case 204:
     case 205:
@@ -33780,13 +33779,14 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 208:
     case 209:
     case 210:
-    case 266:
-    case 293:
+    case 211:
+    case 267:
     case 294:
-    case 296:
-    case 298:
-    case 303:
+    case 295:
+    case 297:
+    case 299:
     case 304:
+    case 305:
       return aarch64_ext_imm (self, info, code, inst, errors);
     case 51:
     case 52:
@@ -33798,10 +33798,10 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 56:
       return aarch64_ext_shll_imm (self, info, code, inst, errors);
     case 59:
-    case 169:
+    case 170:
       return aarch64_ext_fpimm (self, info, code, inst, errors);
     case 77:
-    case 177:
+    case 178:
       return aarch64_ext_limm (self, info, code, inst, errors);
     case 78:
       return aarch64_ext_aimm (self, info, code, inst, errors);
@@ -33811,11 +33811,11 @@  aarch64_extract_operand (const aarch64_operand *self,
       return aarch64_ext_fbits (self, info, code, inst, errors);
     case 82:
     case 83:
-    case 174:
+    case 175:
       return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
     case 84:
-    case 173:
-    case 175:
+    case 174:
+    case 176:
       return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
     case 85:
     case 86:
@@ -33892,8 +33892,8 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 149:
     case 150:
     case 151:
-      return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 152:
+      return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
     case 153:
     case 154:
     case 155:
@@ -33901,115 +33901,112 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 157:
     case 158:
     case 159:
-      return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 160:
+      return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
     case 161:
     case 162:
     case 163:
-      return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 164:
-      return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
     case 165:
-      return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
     case 166:
-      return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
     case 167:
-      return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+      return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
     case 168:
+      return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+    case 169:
       return aarch64_ext_sve_asimm (self, info, code, inst, errors);
-    case 170:
-      return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
     case 171:
-      return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+      return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
     case 172:
+      return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+    case 173:
       return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
-    case 176:
+    case 177:
       return aarch64_ext_inv_limm (self, info, code, inst, errors);
-    case 178:
+    case 179:
       return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
-    case 180:
+    case 181:
       return aarch64_ext_sve_scale (self, info, code, inst, errors);
-    case 196:
     case 197:
     case 198:
-      return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
     case 199:
+      return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
     case 200:
     case 201:
-    case 279:
+    case 202:
+    case 280:
       return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
-    case 215:
     case 216:
     case 217:
     case 218:
-      return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
     case 219:
+      return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
     case 220:
     case 221:
     case 222:
+    case 223:
       return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors);
-    case 230:
     case 231:
-    case 233:
+    case 232:
     case 234:
     case 235:
     case 236:
+    case 237:
       return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
-    case 238:
     case 239:
-      return aarch64_ext_sve_index (self, info, code, inst, errors);
     case 240:
-    case 242:
-    case 259:
-      return aarch64_ext_sve_reglist (self, info, code, inst, errors);
+      return aarch64_ext_sve_index (self, info, code, inst, errors);
+    case 241:
     case 243:
+    case 260:
+      return aarch64_ext_sve_reglist (self, info, code, inst, errors);
     case 244:
-    case 246:
+    case 245:
     case 247:
     case 248:
     case 249:
-    case 258:
-      return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
     case 250:
+    case 259:
+      return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
     case 251:
+    case 252:
       return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
-    case 254:
-    case 256:
-    case 267:
-      return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
     case 255:
     case 257:
-      return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
     case 268:
+      return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
+    case 256:
+    case 258:
+      return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
     case 269:
     case 270:
     case 271:
     case 272:
     case 273:
     case 274:
-      return aarch64_ext_sme_za_array (self, info, code, inst, errors);
     case 275:
-      return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+      return aarch64_ext_sme_za_array (self, info, code, inst, errors);
     case 276:
-      return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+      return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
     case 277:
-      return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+      return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
     case 278:
+      return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+    case 279:
       return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
-    case 300:
     case 301:
     case 302:
+    case 303:
       return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
-    case 305:
     case 306:
     case 307:
-      return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
     case 308:
     case 309:
-    case 310:
-    case 311:
       return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
-    case 312:
+    case 310:
       return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 9f3853bd1ad..02cd7e680fb 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -171,6 +171,7 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
+  {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL4", (4 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_Rm}, "vector of address with a scalar register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
   {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
@@ -329,9 +330,6 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 2 SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 3 SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 4 SVE vector registers"},
   {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with post-incrementing by ammount of loaded bytes"},
   {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with pre-incrementing with write-back by ammount of stored bytes"},
   {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with post-incrementing by ammount of loaded bytes"},