diff mbox series

[v3,05/11] aarch64: Fix sve2p1 extq instruction operands (regenerated files).

Message ID 20240621113654.2079200-6-srinath.parvathaneni@arm.com
State Superseded
Headers
Series aarch64: Fix the FEAT_SVE2p1 related issues. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply

Commit Message

Srinath Parvathaneni June 21, 2024, 11:36 a.m. UTC 
  Hi,

This patch includes the regenerated files for
[Binutils] aarch64: Fix sve2p1 extq instruction operands.

Regards,
Srinath.
---
 opcodes/aarch64-asm-2.c | 16 ++++++++--------
 opcodes/aarch64-dis-2.c | 16 ++++++++--------
 opcodes/aarch64-opc-2.c |  2 +-
 3 files changed, 17 insertions(+), 17 deletions(-)
diff mbox series

Patch

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 78798049d34..417f5fe7300 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -666,15 +666,15 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 191:
     case 192:
     case 193:
-    case 208:
     case 209:
     case 210:
     case 211:
-    case 220:
+    case 212:
     case 221:
     case 222:
     case 223:
     case 224:
+    case 225:
     case 235:
     case 239:
     case 243:
@@ -708,9 +708,9 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 39:
     case 40:
     case 41:
-    case 225:
     case 226:
-    case 229:
+    case 227:
+    case 230:
     case 262:
     case 263:
     case 278:
@@ -773,6 +773,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 205:
     case 206:
     case 207:
+    case 208:
     case 264:
     case 291:
     case 292:
@@ -929,19 +930,18 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 199:
     case 277:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-    case 212:
     case 213:
     case 214:
     case 215:
-      return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
     case 216:
+      return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
     case 217:
     case 218:
     case 219:
+    case 220:
       return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
-    case 227:
     case 228:
-    case 230:
+    case 229:
     case 231:
     case 232:
     case 233:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 7819c1091b1..909f28531e9 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -33663,15 +33663,15 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 191:
     case 192:
     case 193:
-    case 208:
     case 209:
     case 210:
     case 211:
-    case 220:
+    case 212:
     case 221:
     case 222:
     case 223:
     case 224:
+    case 225:
     case 235:
     case 239:
     case 243:
@@ -33710,9 +33710,9 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 39:
     case 40:
     case 41:
-    case 225:
     case 226:
-    case 229:
+    case 227:
+    case 230:
     case 262:
     case 263:
     case 278:
@@ -33776,6 +33776,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 205:
     case 206:
     case 207:
+    case 208:
     case 264:
     case 291:
     case 292:
@@ -33934,19 +33935,18 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 199:
     case 277:
       return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
-    case 212:
     case 213:
     case 214:
     case 215:
-      return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
     case 216:
+      return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
     case 217:
     case 218:
     case 219:
+    case 220:
       return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors);
-    case 227:
     case 228:
-    case 230:
+    case 229:
     case 231:
     case 232:
     case 233:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index ad77a36730c..4f186e646e6 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -232,6 +232,7 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3_10}, "an 8-bit unsigned immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a 4-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"},
   {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"},
@@ -257,7 +258,6 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"},
-  {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5}, "an indexed SVE vector register"},