diff mbox series

[v1,07/11] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands (regenerated files).

Message ID 20240612155909.54323-8-srinath.parvathaneni@arm.com
State Superseded
Headers
Series aarch64: Fix the FEAT_SVE2p1 related issues. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply

Commit Message

Srinath Parvathaneni June 12, 2024, 3:59 p.m. UTC 
  Hi,

This patch includes the regenerated files for
[Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.

Regards,
Srinath.
---
 opcodes/aarch64-asm-2.c | 11 ++++-------
 opcodes/aarch64-dis-2.c |  6 +-----
 opcodes/aarch64-opc-2.c |  3 ---
 3 files changed, 5 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index f7c36d6f262..3b2b68b57db 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -954,9 +954,6 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 239:
     case 241:
     case 258:
-    case 304:
-    case 305:
-    case 306:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     case 242:
     case 243:
@@ -996,12 +993,12 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 300:
     case 301:
       return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
+    case 304:
+    case 305:
+    case 306:
     case 307:
-    case 308:
-    case 309:
-    case 310:
       return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
-    case 311:
+    case 308:
       return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index a85b5c434f0..477cd6feb22 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -34001,13 +34001,9 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 304:
     case 305:
     case 306:
-      return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
     case 307:
-    case 308:
-    case 309:
-    case 310:
       return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
-    case 311:
+    case 308:
       return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index b0a5ccb4a83..5eb96d5ec4a 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -328,9 +328,6 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 2 SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 3 SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 4 SVE vector registers"},
   {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with post-incrementing by ammount of loaded bytes"},
   {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with pre-incrementing with write-back by ammount of stored bytes"},
   {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with post-incrementing by ammount of loaded bytes"},