diff mbox series

[v1,10/11] aarch64: Fix FEAT_B16B16 sve2 instruction constraints.

Message ID 20240612155909.54323-11-srinath.parvathaneni@arm.com
State Superseded
Headers
Series aarch64: Fix the FEAT_SVE2p1 related issues. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply

Commit Message

Srinath Parvathaneni June 12, 2024, 3:59 p.m. UTC 
  Hi,

This patch adds missing contraints to FEAT_B16B16 sve2 instructions
bfclamp, bfmla and bfmls and add negative tests for all the bfloat
instructions.

Regression tested for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.
---
 gas/testsuite/gas/aarch64/bfloat16-1.d        |   6 +
 gas/testsuite/gas/aarch64/bfloat16-1.s        |   7 +-
 .../gas/aarch64/bfloat16-2-invalid.d          |   4 +
 .../gas/aarch64/bfloat16-2-invalid.l          | 265 ++++++++++++++++++
 .../gas/aarch64/bfloat16-2-invalid.s          | 147 ++++++++++
 gas/testsuite/gas/aarch64/bfloat16-bad.l      |   3 +
 gas/testsuite/gas/aarch64/bfloat16-invalid.d  |   2 +-
 gas/testsuite/gas/aarch64/bfloat16-invalid.l  |  17 +-
 gas/testsuite/gas/aarch64/bfloat16-invalid.s  |   9 +-
 opcodes/aarch64-tbl.h                         |  46 +--
 10 files changed, 468 insertions(+), 38 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.s

Comments

Richard Earnshaw (lists) June 13, 2024, 3:44 p.m. UTC | #1 
On 12/06/2024 16:59, srinath wrote:
> 
> Hi,
> 
> This patch adds missing contraints to FEAT_B16B16 sve2 instructions
> bfclamp, bfmla and bfmls and add negative tests for all the bfloat
> instructions.
> 
> Regression tested for aarch64-none-elf target and found no regressions.
> 
> Ok for binutils-master?
> 
> Regards,
> Srinath.
> ---
>  gas/testsuite/gas/aarch64/bfloat16-1.d        |   6 +
>  gas/testsuite/gas/aarch64/bfloat16-1.s        |   7 +-
>  .../gas/aarch64/bfloat16-2-invalid.d          |   4 +
>  .../gas/aarch64/bfloat16-2-invalid.l          | 265 ++++++++++++++++++
>  .../gas/aarch64/bfloat16-2-invalid.s          | 147 ++++++++++
>  gas/testsuite/gas/aarch64/bfloat16-bad.l      |   3 +
>  gas/testsuite/gas/aarch64/bfloat16-invalid.d  |   2 +-
>  gas/testsuite/gas/aarch64/bfloat16-invalid.l  |  17 +-
>  gas/testsuite/gas/aarch64/bfloat16-invalid.s  |   9 +-
>  opcodes/aarch64-tbl.h                         |  46 +--
>  10 files changed, 468 insertions(+), 38 deletions(-)
>  create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
>  create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
>  create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
> 
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.l
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
...
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
+.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
+.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
+.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'

It doesn't seem right to me that a test that is supposedly checking for invalid operand combinations would be reporting unsupported instructions.  Perhaps these should be in a separate test with different command-line options?

R.
Andre Vieira (lists) June 14, 2024, 3:44 p.m. UTC | #2 
On 13/06/2024 16:44, Richard Earnshaw (lists) wrote:
> On 12/06/2024 16:59, srinath wrote:
>>
>> Hi,
>>
>> This patch adds missing contraints to FEAT_B16B16 sve2 instructions
>> bfclamp, bfmla and bfmls and add negative tests for all the bfloat
>> instructions.
>>
>> Regression tested for aarch64-none-elf target and found no regressions.
>>
>> Ok for binutils-master?
>>
>> Regards,
>> Srinath.
>> ---
>>   gas/testsuite/gas/aarch64/bfloat16-1.d        |   6 +
>>   gas/testsuite/gas/aarch64/bfloat16-1.s        |   7 +-
>>   .../gas/aarch64/bfloat16-2-invalid.d          |   4 +
>>   .../gas/aarch64/bfloat16-2-invalid.l          | 265 ++++++++++++++++++
>>   .../gas/aarch64/bfloat16-2-invalid.s          | 147 ++++++++++
>>   gas/testsuite/gas/aarch64/bfloat16-bad.l      |   3 +
>>   gas/testsuite/gas/aarch64/bfloat16-invalid.d  |   2 +-
>>   gas/testsuite/gas/aarch64/bfloat16-invalid.l  |  17 +-
>>   gas/testsuite/gas/aarch64/bfloat16-invalid.s  |   9 +-
>>   opcodes/aarch64-tbl.h                         |  46 +--
>>   10 files changed, 468 insertions(+), 38 deletions(-)
>>   create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
>>   create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
>>   create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
>>
> --- a/gas/testsuite/gas/aarch64/bfloat16-invalid.l
> +++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
> ...
> +.*: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
> +.*: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
> +.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
> +.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
> +.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
> 
> It doesn't seem right to me that a test that is supposedly checking for invalid operand combinations would be reporting unsupported instructions.  Perhaps these should be in a separate test with different command-line options?

I think you misunderstood here Richard, Srinath turned this test into a 
'wrong command-line option/unsupported test' see:
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.d 
b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
index 8f24dc62083..02e3e8d8e3d 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.d
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
@@ -1,4 +1,4 @@
-#name: Test Bfloat16 instructions with wrong operand combinations
+#name: Negative test with missing +b16b16 bfloat16 flag.

The reason you got confused I think is because it also has wrong operand 
errors, which is because gas reports these before it reports missing 
support. It does so for other features too mind you, so we are 
consistent here AFAICT.

I do think however, that this test should have at least one of each of 
the new instructions with proper operands, so that we can make sure the 
test checks these are unsupported. For instance bfadd is only in here 
with wrong operands. So it's not actually testing that we don't support 
bfadd with -march=armv9.4-a

Whether we should also include wrong operands here, testing that gas 
checks those before support for the actual instruction is a decision 
that I'll leave to you Richard.  On one side if we decide to change the 
behavior we'd have to go back and change these files, but that itself 
may be a benefit to having the tests... we could make sure the behavior 
doesn't change unnoticed.
Richard Earnshaw (lists) June 14, 2024, 4:20 p.m. UTC | #3 
On 14/06/2024 16:44, Andre Vieira (lists) wrote:
> 
> 
> On 13/06/2024 16:44, Richard Earnshaw (lists) wrote:
>> On 12/06/2024 16:59, srinath wrote:
>>>
>>> Hi,
>>>
>>> This patch adds missing contraints to FEAT_B16B16 sve2 instructions
>>> bfclamp, bfmla and bfmls and add negative tests for all the bfloat
>>> instructions.
>>>
>>> Regression tested for aarch64-none-elf target and found no regressions.
>>>
>>> Ok for binutils-master?
>>>
>>> Regards,
>>> Srinath.
>>> ---
>>>   gas/testsuite/gas/aarch64/bfloat16-1.d        |   6 +
>>>   gas/testsuite/gas/aarch64/bfloat16-1.s        |   7 +-
>>>   .../gas/aarch64/bfloat16-2-invalid.d          |   4 +
>>>   .../gas/aarch64/bfloat16-2-invalid.l          | 265 ++++++++++++++++++
>>>   .../gas/aarch64/bfloat16-2-invalid.s          | 147 ++++++++++
>>>   gas/testsuite/gas/aarch64/bfloat16-bad.l      |   3 +
>>>   gas/testsuite/gas/aarch64/bfloat16-invalid.d  |   2 +-
>>>   gas/testsuite/gas/aarch64/bfloat16-invalid.l  |  17 +-
>>>   gas/testsuite/gas/aarch64/bfloat16-invalid.s  |   9 +-
>>>   opcodes/aarch64-tbl.h                         |  46 +--
>>>   10 files changed, 468 insertions(+), 38 deletions(-)
>>>   create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
>>>   create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
>>>   create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
>>>
>> --- a/gas/testsuite/gas/aarch64/bfloat16-invalid.l
>> +++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
>> ...
>> +.*: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
>> +.*: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
>> +.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
>> +.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
>> +.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
>>
>> It doesn't seem right to me that a test that is supposedly checking for invalid operand combinations would be reporting unsupported instructions.  Perhaps these should be in a separate test with different command-line options?
> 
> I think you misunderstood here Richard, Srinath turned this test into a 'wrong command-line option/unsupported test' see:
> diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
> index 8f24dc62083..02e3e8d8e3d 100644
> --- a/gas/testsuite/gas/aarch64/bfloat16-invalid.d
> +++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
> @@ -1,4 +1,4 @@
> -#name: Test Bfloat16 instructions with wrong operand combinations
> +#name: Negative test with missing +b16b16 bfloat16 flag.

That doesn't make sense to me.  Why change an existing test for one thing into a different test that does something else?  The existing test entries in the file now no-longer match the test summary.

This sort of change should be highlighted in the patch summary; patch review for complex patches is difficult enough as it is, without explanations as to why certain changes are made it's nearly impossible to intuit the reasoning behind the changes.

> 
> The reason you got confused I think is because it also has wrong operand errors, which is because gas reports these before it reports missing support. It does so for other features too mind you, so we are consistent here AFAICT.

Everything in the existing bfloat16-invalid.l is an operand test, so why conflate this with something else?  That doesn't look consistent to me.

Perhaps this could be addressed by writing it in the style of mops_invalid.[sdl] where we change the architecture features on the fly to test different errors.  It would also help if the assembler source had some comments about the expected failures.  

> 
> I do think however, that this test should have at least one of each of the new instructions with proper operands, so that we can make sure the test checks these are unsupported. For instance bfadd is only in here with wrong operands. So it's not actually testing that we don't support bfadd with -march=armv9.4-a
> 
> Whether we should also include wrong operands here, testing that gas checks those before support for the actual instruction is a decision that I'll leave to you Richard.  On one side if we decide to change the behavior we'd have to go back and change these files, but that itself may be a benefit to having the tests... we could make sure the behavior doesn't change unnoticed.


R.
diff mbox series

Patch

diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.d b/gas/testsuite/gas/aarch64/bfloat16-1.d
index 4f1df804d64..51f7e6cab20 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1.d
+++ b/gas/testsuite/gas/aarch64/bfloat16-1.d
@@ -104,3 +104,9 @@ 
 .*:	65020604 	bfsub	z4.h, z16.h, z2.h
 .*:	65010688 	bfsub	z8.h, z20.h, z1.h
 .*:	65000710 	bfsub	z16.h, z24.h, z0.h
+.*:	0420bca3 	movprfx	z3, z5
+.*:	64302483 	bfclamp	z3.h, z4.h, z16.h
+.*:	0420bca3 	movprfx	z3, z5
+.*:	647e0a03 	bfmla	z3.h, z16.h, z6.h\[7\]
+.*:	0420bca3 	movprfx	z3, z5
+.*:	647e0e03 	bfmls	z3.h, z16.h, z6.h\[7\]
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.s b/gas/testsuite/gas/aarch64/bfloat16-1.s
index b8969139145..be8fee9fcc8 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1.s
+++ b/gas/testsuite/gas/aarch64/bfloat16-1.s
@@ -110,4 +110,9 @@  bfsub z4.h, z16.h, z2.h
 bfsub z8.h, z20.h, z1.h
 bfsub z16.h, z24.h, z0.h
 
-
+movprfx z3, z5
+bfclamp z3.h, z4.h, z16.h
+movprfx z3, z5
+bfmla z3.h, z16.h, z6.h[7]
+movprfx z3, z5
+bfmls z3.h, z16.h, z6.h[7]
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
new file mode 100644
index 00000000000..1cd27454d42
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
@@ -0,0 +1,4 @@ 
+#name: Test Bfloat16 instructions with wrong operand combinations
+#as: -march=armv9.4-a+b16b16
+#source: bfloat16-2-invalid.s
+#error_output: bfloat16-2-invalid.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
new file mode 100644
index 00000000000..5da96c72ae5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
@@ -0,0 +1,265 @@ 
+.*: Assembler messages:
+.*: Error: operand mismatch -- `bfadd z0.s,p0/m,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfadd z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfadd z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.s,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfadd z0.h,p0/z,z0.h,z16.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfadd z31.d,p7/m,z31.d,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmax z0.s,p0/m,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmax z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmax z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmax z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmax z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.s,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmax z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmax z0.h,p0/z,z0.h,z16.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmax z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmax z31.d,p7/m,z31.d,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmax z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmaxnm z0.s,p0/m,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmaxnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmaxnm z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmaxnm z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.s,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmaxnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmaxnm z0.h,p0/z,z0.h,z16.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmaxnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmaxnm z31.d,p7/m,z31.d,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmaxnm z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmin z0.s,p0/m,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmin z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmin z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmin z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmin z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.s,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmin z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmin z0.h,p0/z,z0.h,z16.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmin z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmin z31.d,p7/m,z31.d,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmin z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfminnm z0.s,p0/m,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfminnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfminnm z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfminnm z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfminnm z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.s,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfminnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfminnm z0.h,p0/z,z0.h,z16.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfminnm z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfminnm z31.d,p7/m,z31.d,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfminnm z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmla z0.s,p0/m,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmla z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.s,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmla z0.h,p0/z,z0.h,z16.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmla z31.d,p7/m,z31.d,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmls z0.s,p0/m,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmls z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.s,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmls z0.h,p0/z,z0.h,z16.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmls z31.d,p7/m,z31.d,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfmul z0.s,p0/m,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfmul z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmul z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.s,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmul z0.h,p0/z,z0.h,z16.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfmul z31.d,p7/m,z31.d,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfsub z0.s,p0/m,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.h,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z0.h, p0/m, z0.h, z16.h
+.*: Error: p0-p7 expected at operand 2 -- `bfsub z0.h,p8/m,z0.h,z16.h'
+.*: Error: operand 3 must be the same register as operand 1 -- `bfsub z31.h,p0/m,z0.h,z16.h'
+.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.s,z16.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfsub z0.h,p0/z,z0.h,z16.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z0.h, p0/m, z0.h, z16.h
+.*: Error: operand mismatch -- `bfsub z31.d,p7/m,z31.d,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z31.h, p7/m, z31.h, z31.h
+.*: Error: operand mismatch -- `bfadd z0.b,z0.h,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfadd z0.s,z0.h,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfadd z0.h,z0.d,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfadd z0.h,z0.h,z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfadd z31.b,z31.s,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfadd z31.h, z31.h, z31.h
+.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h},z0.h,z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfadd {z0.h-z0.h},z0.h'
+.*: Error: comma expected between operands at operand 3 -- `bfadd z0.h,z0.h'
+.*: Error: operand mismatch -- `bfclamp z0.b,z0.h,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfclamp z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfclamp z0.s,z0.h,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfclamp z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfclamp z0.h,z0.d,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfclamp z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfclamp z0.h,z0.h,z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	bfclamp z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfclamp z31.b,z31.s,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfclamp z31.h, z31.h, z31.h
+.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h},z0.h,z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfclamp {z0.h-z0.h},z0.h'
+.*: Error: comma expected between operands at operand 3 -- `bfclamp z0.h,z0.h'
+.*: Error: operand mismatch -- `bfmla z0.b,z0.h,z0.h\[0\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z0.h, z0.h, z0.h\[0\]
+.*: Error: operand mismatch -- `bfmla z0.s,z0.h,z0.h\[6\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z0.h, z0.h, z0.h\[6\]
+.*: Error: operand mismatch -- `bfmla z0.h,z0.d,z0.h\[8\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z0.h, z0.h, z0.h\[8\]
+.*: Error: operand mismatch -- `bfmla z0.h,z0.h,z0.b\[2\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z0.h, z0.h, z0.h\[2\]
+.*: Error: operand mismatch -- `bfmla z31.b,z31.s,z31.d\[8\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmla z31.h, z31.h, z31.h\[8\]
+.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h},z0.h,z0.h\[1\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmla {z0.h-z0.h},z0.h\[2\]'
+.*: Error: expected an SVE predicate register at operand 2 -- `bfmla z0.h,z0.h\[3\]'
+.*: Error: operand mismatch -- `bfmls z0.b,z0.h,z0.h\[0\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z0.h, z0.h, z0.h\[0\]
+.*: Error: operand mismatch -- `bfmls z0.s,z0.h,z0.h\[6\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z0.h, z0.h, z0.h\[6\]
+.*: Error: operand mismatch -- `bfmls z0.h,z0.d,z0.h\[8\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z0.h, z0.h, z0.h\[8\]
+.*: Error: operand mismatch -- `bfmls z0.h,z0.h,z0.b\[2\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z0.h, z0.h, z0.h\[2\]
+.*: Error: operand mismatch -- `bfmls z31.b,z31.s,z31.d\[8\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmls z31.h, z31.h, z31.h\[8\]
+.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h},z0.h,z0.h\[1\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmls {z0.h-z0.h},z0.h\[2\]'
+.*: Error: expected an SVE predicate register at operand 2 -- `bfmls z0.h,z0.h\[3\]'
+.*: Error: operand mismatch -- `bfmul z0.b,z0.h,z0.h\[0\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z0.h, z0.h, z0.h\[0\]
+.*: Error: operand mismatch -- `bfmul z0.s,z0.h,z0.h\[6\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z0.h, z0.h, z0.h\[6\]
+.*: Error: operand mismatch -- `bfmul z0.h,z0.d,z0.h\[8\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z0.h, z0.h, z0.h\[8\]
+.*: Error: operand mismatch -- `bfmul z0.h,z0.h,z0.b\[2\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z0.h, z0.h, z0.h\[2\]
+.*: Error: operand mismatch -- `bfmul z31.b,z31.s,z31.d\[8\]'
+.*: Info:    did you mean this\?
+.*: Info:    	bfmul z31.h, z31.h, z31.h\[8\]
+.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h},z0.h,z0.h\[1\]'
+.*: Error: expected an SVE vector register at operand 1 -- `bfmul {z0.h-z0.h},z0.h\[2\]'
+.*: Error: expected an SVE predicate register at operand 2 -- `bfmul z0.h,z0.h\[3\]'
+.*: Error: operand mismatch -- `bfsub z0.b,z0.h,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfsub z0.s,z0.h,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfsub z0.h,z0.d,z0.h'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfsub z0.h,z0.h,z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z0.h, z0.h, z0.h
+.*: Error: operand mismatch -- `bfsub z31.b,z31.s,z31.d'
+.*: Info:    did you mean this\?
+.*: Info:    	bfsub z31.h, z31.h, z31.h
+.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h},z0.h,z0.h'
+.*: Error: expected an SVE vector register at operand 1 -- `bfsub {z0.h-z0.h},z0.h'
+.*: Error: comma expected between operands at operand 3 -- `bfsub z0.h,z0.h'
+.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z1.h,z3.h,z16.h'
+.*: Warning: output register of preceding `movprfx' not used in current instruction at operand 1 -- `bfmla z10.h,z16.h,z3.h\[7\]'
+.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfmls z1.h,z3.h,z3.h\[7\]'
+.*: Warning: instruction opens new dependency sequence without ending previous one -- `movprfx z4,z5'
+.*: Warning: output register of preceding `movprfx' expected as output at operand 1 -- `bfclamp z2.h,z3.h,z4.h'
diff --git a/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
new file mode 100644
index 00000000000..d690f121bdf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
@@ -0,0 +1,147 @@ 
+bfadd z0.s, p0/m, z0.h, z16.h
+bfadd z0.h, p0/z, z0.h, z16.h
+bfadd z0.h, p8/m, z0.h, z16.h
+bfadd z31.h, p0/m, z0.h, z16.h
+bfadd z0.h, p0/z, z0.s, z16.h
+bfadd z0.h, p0/z, z0.h, z16.d
+bfadd z31.d, p7/m, z31.d, z31.d
+
+bfmax z0.s, p0/m, z0.h, z16.h
+bfmax z0.h, p0/z, z0.h, z16.h
+bfmax z0.h, p8/m, z0.h, z16.h
+bfmax z31.h, p0/m, z0.h, z16.h
+bfmax z0.h, p0/z, z0.s, z16.h
+bfmax z0.h, p0/z, z0.h, z16.d
+bfmax z31.d, p7/m, z31.d, z31.d
+
+bfmaxnm z0.s, p0/m, z0.h, z16.h
+bfmaxnm z0.h, p0/z, z0.h, z16.h
+bfmaxnm z0.h, p8/m, z0.h, z16.h
+bfmaxnm z31.h, p0/m, z0.h, z16.h
+bfmaxnm z0.h, p0/z, z0.s, z16.h
+bfmaxnm z0.h, p0/z, z0.h, z16.d
+bfmaxnm z31.d, p7/m, z31.d, z31.d
+
+bfmin z0.s, p0/m, z0.h, z16.h
+bfmin z0.h, p0/z, z0.h, z16.h
+bfmin z0.h, p8/m, z0.h, z16.h
+bfmin z31.h, p0/m, z0.h, z16.h
+bfmin z0.h, p0/z, z0.s, z16.h
+bfmin z0.h, p0/z, z0.h, z16.d
+bfmin z31.d, p7/m, z31.d, z31.d
+
+bfminnm z0.s, p0/m, z0.h, z16.h
+bfminnm z0.h, p0/z, z0.h, z16.h
+bfminnm z0.h, p8/m, z0.h, z16.h
+bfminnm z31.h, p0/m, z0.h, z16.h
+bfminnm z0.h, p0/z, z0.s, z16.h
+bfminnm z0.h, p0/z, z0.h, z16.d
+bfminnm z31.d, p7/m, z31.d, z31.d
+
+bfmla z0.s, p0/m, z0.h, z16.h
+bfmla z0.h, p0/z, z0.h, z16.h
+bfmla z0.h, p8/m, z0.h, z16.h
+bfmla z31.h, p0/m, z0.h, z16.h
+bfmla z0.h, p0/z, z0.s, z16.h
+bfmla z0.h, p0/z, z0.h, z16.d
+bfmla z31.d, p7/m, z31.d, z31.d
+
+bfmls z0.s, p0/m, z0.h, z16.h
+bfmls z0.h, p0/z, z0.h, z16.h
+bfmls z0.h, p8/m, z0.h, z16.h
+bfmls z31.h, p0/m, z0.h, z16.h
+bfmls z0.h, p0/z, z0.s, z16.h
+bfmls z0.h, p0/z, z0.h, z16.d
+bfmls z31.d, p7/m, z31.d, z31.d
+
+bfmul z0.s, p0/m, z0.h, z16.h
+bfmul z0.h, p0/z, z0.h, z16.h
+bfmul z0.h, p8/m, z0.h, z16.h
+bfmul z31.h, p0/m, z0.h, z16.h
+bfmul z0.h, p0/z, z0.s, z16.h
+bfmul z0.h, p0/z, z0.h, z16.d
+bfmul z31.d, p7/m, z31.d, z31.d
+
+bfsub z0.s, p0/m, z0.h, z16.h
+bfsub z0.h, p0/z, z0.h, z16.h
+bfsub z0.h, p8/m, z0.h, z16.h
+bfsub z31.h, p0/m, z0.h, z16.h
+bfsub z0.h, p0/z, z0.s, z16.h
+bfsub z0.h, p0/z, z0.h, z16.d
+bfsub z31.d, p7/m, z31.d, z31.d
+
+bfadd z0.b, z0.h, z0.h
+bfadd z31.h, z0.h, z0.h
+bfadd z0.s, z0.h, z0.h
+bfadd z0.h, z0.d, z0.h
+bfadd z0.h, z0.h, z0.b
+bfadd z31.b, z31.s, z31.d
+bfadd {z0.h}, z0.h, z0.h
+bfadd {z0.h - z0.h}, z0.h
+bfadd z0.h, z0.h
+
+bfclamp z0.b, z0.h, z0.h
+bfclamp z31.h, z0.h, z0.h
+bfclamp z0.s, z0.h, z0.h
+bfclamp z0.h, z0.d, z0.h
+bfclamp z0.h, z0.h, z0.b
+bfclamp z31.b, z31.s, z31.d
+bfclamp {z0.h}, z0.h, z0.h
+bfclamp {z0.h - z0.h}, z0.h
+bfclamp z0.h, z0.h
+
+bfmla z0.b, z0.h, z0.h[0]
+bfmla z31.h, z0.h, z0.h[3]
+bfmla z0.s, z0.h, z0.h[6]
+bfmla z0.h, z0.d, z0.h[8]
+bfmla z0.h, z0.h, z0.b[2]
+bfmla z31.b, z31.s, z31.d[8]
+bfmla {z0.h}, z0.h, z0.h[1]
+bfmla {z0.h - z0.h}, z0.h[2]
+bfmla z0.h, z0.h[3]
+
+bfmls z0.b, z0.h, z0.h[0]
+bfmls z31.h, z0.h, z0.h[3]
+bfmls z0.s, z0.h, z0.h[6]
+bfmls z0.h, z0.d, z0.h[8]
+bfmls z0.h, z0.h, z0.b[2]
+bfmls z31.b, z31.s, z31.d[8]
+bfmls {z0.h}, z0.h, z0.h[1]
+bfmls {z0.h - z0.h}, z0.h[2]
+bfmls z0.h, z0.h[3]
+
+bfmul z0.b, z0.h, z0.h[0]
+bfmul z31.h, z0.h, z0.h[3]
+bfmul z0.s, z0.h, z0.h[6]
+bfmul z0.h, z0.d, z0.h[8]
+bfmul z0.h, z0.h, z0.b[2]
+bfmul z31.b, z31.s, z31.d[8]
+bfmul {z0.h}, z0.h, z0.h[1]
+bfmul {z0.h - z0.h}, z0.h[2]
+bfmul z0.h, z0.h[3]
+
+bfsub z0.b, z0.h, z0.h
+bfsub z31.h, z0.h, z0.h
+bfsub z0.s, z0.h, z0.h
+bfsub z0.h, z0.d, z0.h
+bfsub z0.h, z0.h, z0.b
+bfsub z31.b, z31.s, z31.d
+bfsub {z0.h}, z0.h, z0.h
+bfsub {z0.h - z0.h}, z0.h
+bfsub z0.h, z0.h
+
+bfmla z0.h, p0/m, z4.h, z16.h
+movprfx z3, z5
+bfclamp z1.h, z3.h, z16.h
+
+movprfx z3, z5
+bfmla z10.h, z16.h, z3.h[7]
+
+movprfx z3, z5
+bfmls z1.h, z3.h, z3.h[7]
+
+movprfx z2, z3
+movprfx z4, z5
+bfclamp z2.h, z3.h, z4.h
+bfmla z4.h, z5.h, z6.h[7]
+bfmls z3.h, z1.h, z4.h[7]
diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.l b/gas/testsuite/gas/aarch64/bfloat16-bad.l
index 1519a2921f3..d4098bf7e8d 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-bad.l
+++ b/gas/testsuite/gas/aarch64/bfloat16-bad.l
@@ -95,3 +95,6 @@ 
 .*: Error: selected processor does not support `bfsub z4.h,z16.h,z2.h'
 .*: Error: selected processor does not support `bfsub z8.h,z20.h,z1.h'
 .*: Error: selected processor does not support `bfsub z16.h,z24.h,z0.h'
+.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
+.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
+.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
index 8f24dc62083..02e3e8d8e3d 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.d
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
@@ -1,4 +1,4 @@ 
-#name: Test Bfloat16 instructions with wrong operand combinations
+#name: Negative test with missing +b16b16 bfloat16 flag.
 #as: -march=armv9.4-a
 #source: bfloat16-invalid.s
 #error_output: bfloat16-invalid.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
index 0b1354a899e..87e5125e19a 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.l
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
@@ -1,8 +1,11 @@ 
 .*: Assembler messages:
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfadd .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmax .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmin .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfminnm .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
-[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfadd .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmax .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmin .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfminnm .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
+.*: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
+.*: Error: selected processor does not support `bfclamp z3.h,z4.h,z16.h'
+.*: Error: selected processor does not support `bfmla z3.h,z16.h,z6.h\[7\]'
+.*: Error: selected processor does not support `bfmls z3.h,z16.h,z6.h\[7\]'
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.s b/gas/testsuite/gas/aarch64/bfloat16-invalid.s
index a5bdfc81a91..aa66fe6f4ee 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-invalid.s
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.s
@@ -1,13 +1,10 @@ 
 bfadd z0.h, p0/m, z1.h, z0.h
-
 bfmax z0.h, p0/m, z1.h, z0.h
-
 bfmaxnm z0.h, p0/m, z1.h, z0.h
-
 bfmin z0.h, p0/m, z1.h, z0.h
-
 bfminnm z0.h, p0/m, z1.h, z0.h
-
 bfmul z0.h, p0/m, z1.h, z0.h
-
 bfsub z0.h, p0/m, z1.h, z0.h
+bfclamp z3.h,z4.h,z16.h
+bfmla z3.h,z16.h,z6.h[7]
+bfmls z3.h,z16.h,z6.h[7]
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5172515adde..1ed7032697d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2717,8 +2717,8 @@  static const aarch64_feature_set aarch64_feature_the =
   AARCH64_FEATURE (THE);
 static const aarch64_feature_set aarch64_feature_d128_the =
   AARCH64_FEATURES (2, D128, THE);
-static const aarch64_feature_set aarch64_feature_b16b16 =
-  AARCH64_FEATURE (B16B16);
+static const aarch64_feature_set aarch64_feature_b16b16_sve2 =
+  AARCH64_FEATURES (2, B16B16, SVE2);
 static const aarch64_feature_set aarch64_feature_sme2p1 =
   AARCH64_FEATURE (SME2p1);
 static const aarch64_feature_set aarch64_feature_sve2p1 =
@@ -2807,7 +2807,7 @@  static const aarch64_feature_set aarch64_feature_lut_sve2 =
 #define D128	  &aarch64_feature_d128
 #define THE	  &aarch64_feature_the
 #define D128_THE  &aarch64_feature_d128_the
-#define B16B16  &aarch64_feature_b16b16
+#define B16B16_SVE2  &aarch64_feature_b16b16_sve2
 #define SME2p1  &aarch64_feature_sme2p1
 #define SVE2p1  &aarch64_feature_sve2p1
 #define RCPC3	  &aarch64_feature_rcpc3
@@ -2893,11 +2893,11 @@  static const aarch64_feature_set aarch64_feature_lut_sve2 =
 #define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
     FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
-#define B16B16_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
-  { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
+#define B16B16_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+  { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \
     FLAGS | F_STRICT, 0, TIED, NULL }
-#define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
-  { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \
+#define B16B16_SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
+  { NAME, OPCODE, MASK, CLASS, OP, B16B16_SVE2, OPS, QUALS, \
     FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
 #define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \
@@ -6475,22 +6475,22 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0),
 
 /* BFloat16 SVE Instructions.  */
-  B16B16_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
-  B16B16_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
-  B16B16_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSN("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
-  B16B16_INSN("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
-  B16B16_INSN("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
-  B16B16_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
+  B16B16_SVE2_INSNC("bfadd", 0x65008000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfmax", 0x65068000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfmaxnm", 0x65048000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfmin", 0x65078000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfminnm", 0x65058000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfmla", 0x65200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
+  B16B16_SVE2_INSNC("bfmls", 0x65202000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 0),
+  B16B16_SVE2_INSNC("bfmul", 0x65028000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfsub", 0x65018000, 0xffffe000, sve_misc, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_SMSS, 0, C_SCAN_MOVPRFX, 2),
+  B16B16_SVE2_INSNC("bfclamp", 0x64202400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0),
+  B16B16_SVE2_INSNC("bfmla", 0x64200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),
+  B16B16_SVE2_INSNC("bfmls", 0x64200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),
+  B16B16_SVE2_INSN("bfadd", 0x65000000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
+  B16B16_SVE2_INSN("bfmul", 0x65000800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
+  B16B16_SVE2_INSN("bfsub", 0x65000400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0, 0),
+  B16B16_SVE2_INSN("bfmul", 0x64202800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
 
 /* SME2.1 movaz instructions.  */
   SME2p1_INSN ("movaz", 0xc0060600, 0xffff1f83, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_vrsb_2), OP_SVE_BB, 0, 0),