diff mbox series

aarch64: Add support for Armv9.5-A architecture

Message ID 20240610131852.293901-1-claudio.bantaloukas@arm.com
State New
Headers
Series aarch64: Add support for Armv9.5-A architecture |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Claudio Bantaloukas June 10, 2024, 1:18 p.m. UTC 
  The new -march=armv9.5-a flag enables access to the
mandatory cpa, lut and faminmax extensions.
Existing test cases for features are extended to verify they
work without additional flags.
---

Hi, 
Is this ok for master? I do not have commit rights yet, if ok, can someone commit it on my behalf?

Regression tested with aarch64-none-elf target and found no regressions.

Thanks,
Claudio Bantaloukas

 gas/NEWS                                     |  2 ++
 gas/config/tc-aarch64.c                      |  1 +
 gas/doc/c-aarch64.texi                       |  3 ++-
 gas/testsuite/gas/aarch64/advsimd-faminmax.d |  3 ++-
 gas/testsuite/gas/aarch64/advsimd-lut.d      |  1 +
 gas/testsuite/gas/aarch64/armv9_5.d          | 10 ++++++++++
 gas/testsuite/gas/aarch64/armv9_5.s          |  9 +++++++++
 gas/testsuite/gas/aarch64/cpa-addsub.d       |  1 +
 gas/testsuite/gas/aarch64/cpa-sve.d          |  1 +
 gas/testsuite/gas/aarch64/sme2-faminmax.d    |  1 +
 gas/testsuite/gas/aarch64/sve2-faminmax.d    |  3 ++-
 gas/testsuite/gas/aarch64/sve2-lut.d         |  3 ++-
 include/opcode/aarch64.h                     |  8 ++++++++
 13 files changed, 42 insertions(+), 4 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/armv9_5.d
 create mode 100644 gas/testsuite/gas/aarch64/armv9_5.s
diff mbox series

Patch

diff --git a/gas/NEWS b/gas/NEWS
index e51c3bbba6d..5e7f2e59399 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@ 
 -*- text -*-
 
+* Add support for 'armv9.5-a' for -march in AArch64 GAS.
+
 * In x86 Intel syntax undue mnemonic suffixes are now warned about.  This is
   a first step towards rejecting their use where unjustified.
 
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index fec17c40a43..f1421b32116 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10456,6 +10456,7 @@  static const struct aarch64_arch_option_table aarch64_archs[] = {
   {"armv9.2-a",	AARCH64_ARCH_FEATURES (V9_2A)},
   {"armv9.3-a",	AARCH64_ARCH_FEATURES (V9_3A)},
   {"armv9.4-a",	AARCH64_ARCH_FEATURES (V9_4A)},
+  {"armv9.5-a", AARCH64_ARCH_FEATURES (V9_5A)},
   {NULL, AARCH64_NO_FEATURES}
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index b622f30b146..d190eae742e 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -116,7 +116,7 @@  following architecture names are recognized: @code{armv8-a},
 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8.8-a},
 @code{armv8.9-a}, @code{armv8-r}, @code{armv9-a}, @code{armv9.1-a},
-@code{armv9.2-a}, @code{armv9.3-a} and @code{armv9.4-a}.
+@code{armv9.2-a}, @code{armv9.3-a}, @code{armv9.4-a} and @code{armv9.5-a}.
 
 If both @option{-mcpu} and @option{-march} are specified, the
 assembler will use the setting for @option{-mcpu}.  If neither are
@@ -314,6 +314,7 @@  automatically cause those extensions to be disabled.
 @item @code{armv9.2-a} @tab @code{armv9.1-a}, @code{armv8.7-a}
 @item @code{armv9.3-a} @tab @code{armv9.2-a}, @code{armv8.8-a}
 @item @code{armv9.4-a} @tab @code{armv9.3-a}, @code{armv8.9-a}
+@item @code{armv9.5-a} @tab @code{armv9.4-a}, @code{cpa}, @code{lut}, @code{faminmax}
 @item @code{armv8-r} @tab @code{armv8.4-a+nolor}
 @end multitable
 
diff --git a/gas/testsuite/gas/aarch64/advsimd-faminmax.d b/gas/testsuite/gas/aarch64/advsimd-faminmax.d
index 96df2a7e2cf..486e404e9af 100644
--- a/gas/testsuite/gas/aarch64/advsimd-faminmax.d
+++ b/gas/testsuite/gas/aarch64/advsimd-faminmax.d
@@ -1,4 +1,5 @@ 
 #objdump: -dr
+#as: -march=armv9.5-a
 #as: -march=armv8-a+faminmax
 
 .*:     file format .*
@@ -57,4 +58,4 @@  Disassembly of section \.text:
 [^:]+:	6ee0dfe0 	famin	v0.2d, v31.2d, v0.2d
 [^:]+:	6effdc00 	famin	v0.2d, v0.2d, v31.2d
 [^:]+:	6ef0ddd2 	famin	v18.2d, v14.2d, v16.2d
-[^:]+:	2ef3dc23 	.inst	0x2ef3dc23 ; undefined
\ No newline at end of file
+[^:]+:	2ef3dc23 	.inst	0x2ef3dc23 ; undefined
diff --git a/gas/testsuite/gas/aarch64/advsimd-lut.d b/gas/testsuite/gas/aarch64/advsimd-lut.d
index 0240d0ded6d..f95c9c6cda1 100644
--- a/gas/testsuite/gas/aarch64/advsimd-lut.d
+++ b/gas/testsuite/gas/aarch64/advsimd-lut.d
@@ -1,4 +1,5 @@ 
 #objdump: -dr
+#as: -march=armv9.5-a
 #as: -march=armv8-a+lut
 
 .*:     file format .*
diff --git a/gas/testsuite/gas/aarch64/armv9_5.d b/gas/testsuite/gas/aarch64/armv9_5.d
new file mode 100644
index 00000000000..22a64a514e4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv9_5.d
@@ -0,0 +1,10 @@ 
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+:	9a002000 	addpt	x0, x0, x0
+[^:]+:	0ec01c00 	famax	v0.4h, v0.4h, v0.4h
+[^:]+:	4e801000 	luti2	v0.16b, {v0.16b}, v0\[0\]
diff --git a/gas/testsuite/gas/aarch64/armv9_5.s b/gas/testsuite/gas/aarch64/armv9_5.s
new file mode 100644
index 00000000000..a6a11743ce3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/armv9_5.s
@@ -0,0 +1,9 @@ 
+	.text
+
+	.arch	armv9.5-a
+	// CPA
+	addpt   x0, x0, x0
+	// FAMINMAX
+	famax	v0.4h, v0.4h, v0.4h
+	// LUT
+	luti2	v0.16b, { v0.16b }, v0[0]
diff --git a/gas/testsuite/gas/aarch64/cpa-addsub.d b/gas/testsuite/gas/aarch64/cpa-addsub.d
index 73e9ea28604..9cc66d754c7 100644
--- a/gas/testsuite/gas/aarch64/cpa-addsub.d
+++ b/gas/testsuite/gas/aarch64/cpa-addsub.d
@@ -1,4 +1,5 @@ 
 #name: Tests for CPA instructions ((M)ADDPT and (M)SUBPT).
+#as: -march=armv9.5-a
 #as: -march=armv8-a+cpa
 #objdump: -dr
 
diff --git a/gas/testsuite/gas/aarch64/cpa-sve.d b/gas/testsuite/gas/aarch64/cpa-sve.d
index e2bf48a35bf..090504f4091 100644
--- a/gas/testsuite/gas/aarch64/cpa-sve.d
+++ b/gas/testsuite/gas/aarch64/cpa-sve.d
@@ -1,4 +1,5 @@ 
 #name: Tests for CPA+SVE instructions.
+#as: -march=armv9.5-a+sve
 #as: -march=armv8-a+sve+cpa
 #objdump: -dr
 
diff --git a/gas/testsuite/gas/aarch64/sme2-faminmax.d b/gas/testsuite/gas/aarch64/sme2-faminmax.d
index 9a6d69e30d8..9eeb487b32d 100644
--- a/gas/testsuite/gas/aarch64/sme2-faminmax.d
+++ b/gas/testsuite/gas/aarch64/sme2-faminmax.d
@@ -1,4 +1,5 @@ 
 #objdump: -dr
+#as: -march=armv9.5-a+sme2
 #as: -march=armv8-a+faminmax+sme2
 
 .*:     file format .*
diff --git a/gas/testsuite/gas/aarch64/sve2-faminmax.d b/gas/testsuite/gas/aarch64/sve2-faminmax.d
index d85019ccd29..7a2743bacc9 100644
--- a/gas/testsuite/gas/aarch64/sve2-faminmax.d
+++ b/gas/testsuite/gas/aarch64/sve2-faminmax.d
@@ -1,4 +1,5 @@ 
 #objdump: -dr
+#as: -march=armv9.5-a+sve2
 #as: -march=armv8-a+faminmax+sve2
 
 .*:     file format .*
@@ -87,4 +88,4 @@  Disassembly of section \.text:
  138:	654f9ce5 	famin	z5.h, p7/m, z5.h, z7.h
  13c:	04d13d05 	movprfx	z5.d, p7/m, z8.d
  140:	65cf9d25 	famin	z5.d, p7/m, z5.d, z9.d
- 144:	650f9d25 	.inst	0x650f9d25 ; undefined
\ No newline at end of file
+ 144:	650f9d25 	.inst	0x650f9d25 ; undefined
diff --git a/gas/testsuite/gas/aarch64/sve2-lut.d b/gas/testsuite/gas/aarch64/sve2-lut.d
index 7b39b17d35d..cdbc13ea1ce 100644
--- a/gas/testsuite/gas/aarch64/sve2-lut.d
+++ b/gas/testsuite/gas/aarch64/sve2-lut.d
@@ -1,4 +1,5 @@ 
 #objdump: -dr
+#as: -march=armv9.5-a+sve2
 #as: -march=armv8-a+lut+sve2
 
 .*:     file format .*
@@ -38,4 +39,4 @@  Disassembly of section \.text:
 [^:]+:	4520b7e0 	luti4	z0.h, \{z31.h-z0.h\}, z0\[0\]
 [^:]+:	453fb400 	luti4	z0.h, \{z0.h-z1.h\}, z31\[0\]
 [^:]+:	45e0b400 	luti4	z0.h, \{z0.h-z1.h\}, z0\[3\]
-[^:]+:	45afb524 	luti4	z4.h, \{z9.h-z10.h\}, z15\[2\]
\ No newline at end of file
+[^:]+:	45afb524 	luti4	z4.h, \{z9.h-z10.h\}, z15\[2\]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 8a21611e3ff..f0cdb80a5f9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -238,6 +238,8 @@  enum aarch64_feature_bit {
   AARCH64_FEATURE_FP8,
   /* LUT instructions.  */
   AARCH64_FEATURE_LUT,
+  /* Armv9.5-A processors.  */
+  AARCH64_FEATURE_V9_5A,
   AARCH64_NUM_FEATURES
 };
 
@@ -328,6 +330,10 @@  enum aarch64_feature_bit {
 #define AARCH64_ARCH_V9_2A_FEATURES(X)	AARCH64_ARCH_V8_7A_FEATURES (X)
 #define AARCH64_ARCH_V9_3A_FEATURES(X)	AARCH64_ARCH_V8_8A_FEATURES (X)
 #define AARCH64_ARCH_V9_4A_FEATURES(X)	AARCH64_ARCH_V8_9A_FEATURES (X)
+#define AARCH64_ARCH_V9_5A_FEATURES(X)	(AARCH64_FEATBIT (X, V9_5A)	\
+					 | AARCH64_FEATBIT (X, CPA)	\
+					 | AARCH64_FEATBIT (X, LUT)	\
+					 | AARCH64_FEATBIT (X, FAMINMAX))
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8A(X)	(AARCH64_FEATBIT (X, V8) \
@@ -365,6 +371,8 @@  enum aarch64_feature_bit {
 				 | AARCH64_ARCH_V9_3A_FEATURES (X))
 #define AARCH64_ARCH_V9_4A(X)	(AARCH64_ARCH_V9_3A (X) \
 				 | AARCH64_ARCH_V9_4A_FEATURES (X))
+#define AARCH64_ARCH_V9_5A(X)	(AARCH64_ARCH_V9_4A (X) \
+				 | AARCH64_ARCH_V9_5A_FEATURES (X))
 
 #define AARCH64_ARCH_NONE(X)	0