diff mbox series

[v2,2/2] gas, aarch64: Add SME2 lutv2 extension generated files

Message ID 20240607142649.592529-2-saurabh.jha@arm.com
State Superseded
Headers
Series [v2,1/2] gas, aarch64: Add SME2 lutv2 extension |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 fail Testing failed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Saurabh Jha June 7, 2024, 2:26 p.m. UTC 
  Adds generated files for the previous patch. No other changes.
---
 opcodes/aarch64-asm-2.c |  83 +++++++++++-----------
 opcodes/aarch64-dis-2.c | 150 +++++++++++++++++++++++++---------------
 opcodes/aarch64-opc-2.c |   3 +
 3 files changed, 139 insertions(+), 97 deletions(-)

Comments

Richard Earnshaw (lists) June 12, 2024, 1:38 p.m. UTC | #1 
On 07/06/2024 15:26, saurabh.jha@arm.com wrote:
> 
> Adds generated files for the previous patch. No other changes.
> ---
>  opcodes/aarch64-asm-2.c |  83 +++++++++++-----------
>  opcodes/aarch64-dis-2.c | 150 +++++++++++++++++++++++++---------------
>  opcodes/aarch64-opc-2.c |   3 +
>  3 files changed, 139 insertions(+), 97 deletions(-)
> 

The Linaro CI is showing: 
FAIL: 3 regressions

regressions.sum:
		=== gas tests ===

Running gas:gas/aarch64/aarch64.exp ...
FAIL: gas/aarch64/sme2-lutv2 
FAIL: gas/aarch64/sme2-lutv2-bad 
FAIL: gas/aarch64/sme2-lutv2-illegal 

Could you check this out please and fix if needed?

R.
Saurabh Jha June 13, 2024, 12:48 p.m. UTC | #2 
On 6/12/2024 2:38 PM, Richard Earnshaw (lists) wrote:
> On 07/06/2024 15:26, saurabh.jha@arm.com wrote:
>>
>> Adds generated files for the previous patch. No other changes.
>> ---
>>   opcodes/aarch64-asm-2.c |  83 +++++++++++-----------
>>   opcodes/aarch64-dis-2.c | 150 +++++++++++++++++++++++++---------------
>>   opcodes/aarch64-opc-2.c |   3 +
>>   3 files changed, 139 insertions(+), 97 deletions(-)
>>
> 
> The Linaro CI is showing:
> FAIL: 3 regressions
> 
> regressions.sum:
> 		=== gas tests ===
> 
> Running gas:gas/aarch64/aarch64.exp ...
> FAIL: gas/aarch64/sme2-lutv2
> FAIL: gas/aarch64/sme2-lutv2-bad
> FAIL: gas/aarch64/sme2-lutv2-illegal
> 
> Could you check this out please and fix if needed?
> 
> R.
I just pushed a v3 of this patch series here 
https://sourceware.org/pipermail/binutils/2024-June/134752.html. Fixed a 
merge conflict.

Saurabh
diff mbox series

Patch

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index a4b02cd9a25..9b91ae44757 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -677,19 +677,19 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 224:
     case 235:
     case 239:
-    case 243:
-    case 250:
-    case 251:
-    case 258:
-    case 259:
+    case 244:
+    case 252:
+    case 253:
     case 260:
     case 261:
+    case 262:
+    case 263:
       return aarch64_ins_regno (self, info, code, inst, errors);
     case 6:
     case 118:
     case 119:
-    case 293:
     case 295:
+    case 298:
       return aarch64_ins_none (self, info, code, inst, errors);
     case 17:
       return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -703,7 +703,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 36:
     case 37:
     case 38:
-    case 297:
+    case 300:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case 39:
     case 40:
@@ -711,10 +711,8 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 225:
     case 226:
     case 229:
-    case 262:
-    case 263:
-    case 278:
-    case 279:
+    case 264:
+    case 265:
     case 280:
     case 281:
     case 282:
@@ -726,6 +724,8 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 288:
     case 289:
     case 290:
+    case 291:
+    case 292:
       return aarch64_ins_simple_index (self, info, code, inst, errors);
     case 42:
       return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -773,13 +773,14 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 205:
     case 206:
     case 207:
-    case 264:
-    case 291:
-    case 292:
+    case 266:
+    case 293:
     case 294:
     case 296:
-    case 301:
-    case 302:
+    case 297:
+    case 299:
+    case 304:
+    case 305:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 51:
     case 52:
@@ -927,7 +928,7 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 197:
     case 198:
     case 199:
-    case 277:
+    case 279:
       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
     case 212:
     case 213:
@@ -953,55 +954,57 @@  aarch64_insert_operand (const aarch64_operand *self,
       return aarch64_ins_sve_index (self, info, code, inst, errors);
     case 238:
     case 240:
-    case 257:
-    case 303:
-    case 304:
-    case 305:
+    case 259:
+    case 306:
+    case 307:
+    case 308:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     case 241:
     case 242:
-    case 244:
     case 245:
     case 246:
     case 247:
-    case 256:
-      return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
     case 248:
     case 249:
+    case 258:
+      return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
+    case 243:
+    case 250:
+    case 251:
       return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
-    case 252:
     case 254:
-    case 265:
+    case 256:
+    case 267:
       return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
-    case 253:
     case 255:
+    case 257:
       return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
-    case 266:
-    case 267:
     case 268:
     case 269:
     case 270:
     case 271:
     case 272:
-      return aarch64_ins_sme_za_array (self, info, code, inst, errors);
     case 273:
-      return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
     case 274:
-      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+      return aarch64_ins_sme_za_array (self, info, code, inst, errors);
     case 275:
-      return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+      return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
     case 276:
+      return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+    case 277:
+      return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+    case 278:
       return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
-    case 298:
-    case 299:
-    case 300:
+    case 301:
+    case 302:
+    case 303:
       return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
-    case 306:
-    case 307:
-    case 308:
     case 309:
-      return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
     case 310:
+    case 311:
+    case 312:
+      return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+    case 313:
       return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 35501d6777e..37bd526d2b0 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -204,32 +204,54 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                             }
                                           else
                                             {
-                                              if (((word >> 22) & 0x1) == 0)
+                                              if (((word >> 20) & 0x1) == 0)
                                                 {
-                                                  if (((word >> 14) & 0x1) == 0)
+                                                  if (((word >> 22) & 0x1) == 0)
                                                     {
-                                                      /* 33222222222211111111110000000000
-                                                         10987654321098765432109876543210
-                                                         x1000000x00x101xx0xxxxxxxxxxxxxx
-                                                         luti4.  */
-                                                      return 2670;
+                                                      if (((word >> 14) & 0x1) == 0)
+                                                        {
+                                                          if (((word >> 15) & 0x1) == 0)
+                                                            {
+                                                              /* 33222222222211111111110000000000
+                                                                 10987654321098765432109876543210
+                                                                 x1000000x000101x00xxxxxxxxxxxxxx
+                                                                 luti4.  */
+                                                              return 3393;
+                                                            }
+                                                          else
+                                                            {
+                                                              /* 33222222222211111111110000000000
+                                                                 10987654321098765432109876543210
+                                                                 x1000000x000101x10xxxxxxxxxxxxxx
+                                                                 luti4.  */
+                                                              return 2670;
+                                                            }
+                                                        }
+                                                      else
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             x1000000x000101xx1xxxxxxxxxxxxxx
+                                                             luti4.  */
+                                                          return 2669;
+                                                        }
                                                     }
                                                   else
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x1000000x00x101xx1xxxxxxxxxxxxxx
+                                                         x1000000x100101xxxxxxxxxxxxxxxxx
                                                          luti4.  */
-                                                      return 2669;
+                                                      return 2668;
                                                     }
                                                 }
                                               else
                                                 {
                                                   /* 33222222222211111111110000000000
                                                      10987654321098765432109876543210
-                                                     x1000000x10x101xxxxxxxxxxxxxxxxx
+                                                     x1000000xx01101xxxxxxxxxxxxxxxxx
                                                      luti4.  */
-                                                  return 2668;
+                                                  return 3394;
                                                 }
                                             }
                                         }
@@ -328,21 +350,32 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                                     {
                                                       if (((word >> 23) & 0x1) == 0)
                                                         {
-                                                          if (((word >> 17) & 0x1) == 0)
+                                                          if (((word >> 16) & 0x1) == 0)
                                                             {
-                                                              /* 33222222222211111111110000000000
-                                                                 10987654321098765432109876543210
-                                                                 x1000000010x110xxxxx00xxxxxxxxxx
-                                                                 movt.  */
-                                                              return 2688;
+                                                              if (((word >> 17) & 0x1) == 0)
+                                                                {
+                                                                  /* 33222222222211111111110000000000
+                                                                     10987654321098765432109876543210
+                                                                     x1000000010x1100xxxx00xxxxxxxxxx
+                                                                     movt.  */
+                                                                  return 2688;
+                                                                }
+                                                              else
+                                                                {
+                                                                  /* 33222222222211111111110000000000
+                                                                     10987654321098765432109876543210
+                                                                     x1000000010x1110xxxx00xxxxxxxxxx
+                                                                     movt.  */
+                                                                  return 2687;
+                                                                }
                                                             }
                                                           else
                                                             {
                                                               /* 33222222222211111111110000000000
                                                                  10987654321098765432109876543210
-                                                                 x1000000010x111xxxxx00xxxxxxxxxx
+                                                                 x1000000010x11x1xxxx00xxxxxxxxxx
                                                                  movt.  */
-                                                              return 2687;
+                                                              return 3395;
                                                             }
                                                         }
                                                       else
@@ -33674,19 +33707,19 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 224:
     case 235:
     case 239:
-    case 243:
-    case 250:
-    case 251:
-    case 258:
-    case 259:
+    case 244:
+    case 252:
+    case 253:
     case 260:
     case 261:
+    case 262:
+    case 263:
       return aarch64_ext_regno (self, info, code, inst, errors);
     case 6:
     case 118:
     case 119:
-    case 293:
     case 295:
+    case 298:
       return aarch64_ext_none (self, info, code, inst, errors);
     case 11:
       return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -33705,7 +33738,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 36:
     case 37:
     case 38:
-    case 297:
+    case 300:
       return aarch64_ext_reglane (self, info, code, inst, errors);
     case 39:
     case 40:
@@ -33713,10 +33746,8 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 225:
     case 226:
     case 229:
-    case 262:
-    case 263:
-    case 278:
-    case 279:
+    case 264:
+    case 265:
     case 280:
     case 281:
     case 282:
@@ -33728,6 +33759,8 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 288:
     case 289:
     case 290:
+    case 291:
+    case 292:
       return aarch64_ext_simple_index (self, info, code, inst, errors);
     case 42:
       return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -33776,13 +33809,14 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 205:
     case 206:
     case 207:
-    case 264:
-    case 291:
-    case 292:
+    case 266:
+    case 293:
     case 294:
     case 296:
-    case 301:
-    case 302:
+    case 297:
+    case 299:
+    case 304:
+    case 305:
       return aarch64_ext_imm (self, info, code, inst, errors);
     case 51:
     case 52:
@@ -33932,7 +33966,7 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 197:
     case 198:
     case 199:
-    case 277:
+    case 279:
       return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
     case 212:
     case 213:
@@ -33958,56 +33992,58 @@  aarch64_extract_operand (const aarch64_operand *self,
       return aarch64_ext_sve_index (self, info, code, inst, errors);
     case 238:
     case 240:
-    case 257:
+    case 259:
       return aarch64_ext_sve_reglist (self, info, code, inst, errors);
     case 241:
     case 242:
-    case 244:
     case 245:
     case 246:
     case 247:
-    case 256:
-      return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
     case 248:
     case 249:
+    case 258:
+      return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
+    case 243:
+    case 250:
+    case 251:
       return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
-    case 252:
     case 254:
-    case 265:
+    case 256:
+    case 267:
       return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
-    case 253:
     case 255:
+    case 257:
       return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
-    case 266:
-    case 267:
     case 268:
     case 269:
     case 270:
     case 271:
     case 272:
-      return aarch64_ext_sme_za_array (self, info, code, inst, errors);
     case 273:
-      return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
     case 274:
-      return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+      return aarch64_ext_sme_za_array (self, info, code, inst, errors);
     case 275:
-      return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+      return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
     case 276:
+      return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+    case 277:
+      return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+    case 278:
       return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
-    case 298:
-    case 299:
-    case 300:
-      return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
+    case 301:
+    case 302:
     case 303:
-    case 304:
-    case 305:
-      return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
+      return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
     case 306:
     case 307:
     case 308:
+      return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
     case 309:
-      return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
     case 310:
+    case 311:
+    case 312:
+      return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+    case 313:
       return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index bd1aa4f27c1..30577ffda64 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -267,10 +267,12 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZdnT, FLD_SME_Zdn2_0}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm}, "an SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"},
@@ -319,6 +321,7 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"},
   {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX2_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
   {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
   {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},