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[2/2] RISC-V: Add support for Zcmop extension

Message ID 20240606093238.45579-3-zengxiao@eswincomputing.com
State New
Headers
Series RISC-V: Add support for Zimop and Zcmop extension |

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linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
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Commit Message

Xiao Zeng June 6, 2024, 9:32 a.m. UTC 
  This implements the Zcmop (Compressed Zimop) extension, as of version 1.0.

View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>

1 The Zcmop extension requires the Zca extension.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zcmop.d: New test.
	* testsuite/gas/riscv/zcmop.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_C_MOP_1): Define.
	(MASK_C_MOP_1): Ditto.
	(MATCH_C_MOP_3): Ditto.
	(MASK_C_MOP_3): Ditto.
	(MATCH_C_MOP_5): Ditto.
	(MASK_C_MOP_5): Ditto.
	(MATCH_C_MOP_7): Ditto.
	(MASK_C_MOP_7): Ditto.
	(MATCH_C_MOP_9): Ditto.
	(MASK_C_MOP_9): Ditto.
	(MATCH_C_MOP_11): Ditto.
	(MASK_C_MOP_11): Ditto.
	(MATCH_C_MOP_13): Ditto.
	(MASK_C_MOP_13): Ditto.
	(MATCH_C_MOP_15): Ditto.
	(MASK_C_MOP_15): Ditto.
	(DECLARE_INSN): New declarations for Zcmop.
	* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zcmop instructions.
---
 bfd/elfxx-riscv.c                    |  6 ++++++
 gas/NEWS                             |  2 ++
 gas/testsuite/gas/riscv/march-help.l |  1 +
 gas/testsuite/gas/riscv/zcmop.d      | 16 ++++++++++++++++
 gas/testsuite/gas/riscv/zcmop.s      | 10 ++++++++++
 include/opcode/riscv-opc.h           | 26 ++++++++++++++++++++++++++
 include/opcode/riscv.h               |  1 +
 opcodes/riscv-opc.c                  | 10 ++++++++++
 8 files changed, 72 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zcmop.d
 create mode 100644 gas/testsuite/gas/riscv/zcmop.s
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 87b88513f5c..2dcd6c62a1b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1271,6 +1271,7 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zcf", "zca",	check_implicit_always},
   {"zcd", "zca",	check_implicit_always},
   {"zcb", "zca",	check_implicit_always},
+  {"zcmop", "zca",	check_implicit_always},
   {"zcmp", "zca",	check_implicit_always},
   {"smaia", "ssaia",		check_implicit_always},
   {"smcntrpmf", "zicsr",	check_implicit_always},
@@ -1432,6 +1433,7 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zcb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zcf",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zcd",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zcmop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zcmp",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {NULL, 0, 0, 0, 0}
 };
@@ -2683,6 +2685,8 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return (riscv_subset_supports (rps, "zcb")
 	      && riscv_subset_supports (rps, "zmmul"));
+    case INSN_CLASS_ZCMOP:
+      return riscv_subset_supports (rps, "zcmop");
     case INSN_CLASS_ZCMP:
       return riscv_subset_supports (rps, "zcmp");
     case INSN_CLASS_SVINVAL:
@@ -2955,6 +2959,8 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zcb' and `zbb");
     case INSN_CLASS_ZCB_AND_ZMMUL:
       return _("zcb' and `zmmul', or `zcb' and `m");
+    case INSN_CLASS_ZCMOP:
+      return "zcmop";
     case INSN_CLASS_ZCMP:
       return "zcmp";
     case INSN_CLASS_SVINVAL:
diff --git a/gas/NEWS b/gas/NEWS
index e6c1507349f..4d21dd5362b 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -21,6 +21,8 @@ 
 
 * Add support for RISC-V Zimop extension with version 1.0.
 
+* Add support for RISC-V Zcmop extension with version 1.0.
+
 * Add support for RISC-V Zcmp extension with version 1.0.
 
 * Add support for RISC-V Zfbfmin extension with version 1.0.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index dace28179b8..817b9aec5f3 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -94,6 +94,7 @@  All available -march extensions for RISC-V:
 	zcb                                     1.0
 	zcf                                     1.0
 	zcd                                     1.0
+	zcmop                                   1.0
 	zcmp                                    1.0
 	smaia                                   1.0
 	smcntrpmf                               1.0
diff --git a/gas/testsuite/gas/riscv/zcmop.d b/gas/testsuite/gas/riscv/zcmop.d
new file mode 100644
index 00000000000..5f608c676c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmop.d
@@ -0,0 +1,16 @@ 
+#as: -march=rv64i_zcmop
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+6081[ 	]+c.mop.1
+[ 	]+[0-9a-f]+:[ 	]+6181[ 	]+c.mop.3
+[ 	]+[0-9a-f]+:[ 	]+6281[ 	]+c.mop.5
+[ 	]+[0-9a-f]+:[ 	]+6381[ 	]+c.mop.7
+[ 	]+[0-9a-f]+:[ 	]+6481[ 	]+c.mop.9
+[ 	]+[0-9a-f]+:[ 	]+6581[ 	]+c.mop.11
+[ 	]+[0-9a-f]+:[ 	]+6681[ 	]+c.mop.13
+[ 	]+[0-9a-f]+:[ 	]+6781[ 	]+c.mop.15
diff --git a/gas/testsuite/gas/riscv/zcmop.s b/gas/testsuite/gas/riscv/zcmop.s
new file mode 100644
index 00000000000..4b02e694f46
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmop.s
@@ -0,0 +1,10 @@ 
+target:
+	# c.mop.n
+	c.mop.1
+	c.mop.3
+	c.mop.5
+	c.mop.7
+	c.mop.9
+	c.mop.11
+	c.mop.13
+	c.mop.15
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 8ba95399430..c7403d42734 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2271,6 +2271,23 @@ 
 #define MASK_C_NOT 0xfc7f
 #define MATCH_C_MUL 0x9c41
 #define MASK_C_MUL 0xfc63
+/* Zcmop instructions.  */
+#define MATCH_C_MOP_1 0x6081
+#define MASK_C_MOP_1 0xffff
+#define MATCH_C_MOP_3 0x6181
+#define MASK_C_MOP_3 0xffff
+#define MATCH_C_MOP_5 0x6281
+#define MASK_C_MOP_5 0xffff
+#define MATCH_C_MOP_7 0x6381
+#define MASK_C_MOP_7 0xffff
+#define MATCH_C_MOP_9 0x6481
+#define MASK_C_MOP_9 0xffff
+#define MATCH_C_MOP_11 0x6581
+#define MASK_C_MOP_11 0xffff
+#define MATCH_C_MOP_13 0x6681
+#define MASK_C_MOP_13 0xffff
+#define MATCH_C_MOP_15 0x6781
+#define MASK_C_MOP_15 0xffff
 /* Zcmp instructions.  */
 #define MATCH_CM_PUSH 0xb802
 #define MASK_CM_PUSH 0xff03
@@ -4176,6 +4193,15 @@  DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU)
 DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH)
 DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB)
 DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH)
+/* Zcmop instructions.  */
+DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1)
+DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3)
+DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5)
+DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7)
+DECLARE_INSN(c_mop_9, MATCH_C_MOP_9, MASK_C_MOP_9)
+DECLARE_INSN(c_mop_11, MATCH_C_MOP_11, MASK_C_MOP_11)
+DECLARE_INSN(c_mop_13, MATCH_C_MOP_13, MASK_C_MOP_13)
+DECLARE_INSN(c_mop_15, MATCH_C_MOP_15, MASK_C_MOP_15)
 /* Zcmp instructions.  */
 DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH)
 DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 2b2ed0dbce8..8f546772de0 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -487,6 +487,7 @@  enum riscv_insn_class
   INSN_CLASS_ZCB_AND_ZBA,
   INSN_CLASS_ZCB_AND_ZBB,
   INSN_CLASS_ZCB_AND_ZMMUL,
+  INSN_CLASS_ZCMOP,
   INSN_CLASS_ZCMP,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 45269e095a6..78144fca675 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2137,6 +2137,16 @@  const struct riscv_opcode riscv_opcodes[] =
 {"c.zext.b",   0, INSN_CLASS_ZCB, "Cs",  MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 },
 {"c.sext.w",  64, INSN_CLASS_ZCB, "d",  MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
 
+/* Zcmop instructions.  */
+{"c.mop.1",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_1,  MASK_C_MOP_1, match_opcode, 0 },
+{"c.mop.3",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_3,  MASK_C_MOP_3, match_opcode, 0 },
+{"c.mop.5",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_5,  MASK_C_MOP_5, match_opcode, 0 },
+{"c.mop.7",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_7,  MASK_C_MOP_7, match_opcode, 0 },
+{"c.mop.9",     0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_9,  MASK_C_MOP_9, match_opcode, 0 },
+{"c.mop.11",    0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_11, MASK_C_MOP_11, match_opcode, 0 },
+{"c.mop.13",    0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_13, MASK_C_MOP_13, match_opcode, 0 },
+{"c.mop.15",    0,  INSN_CLASS_ZCMOP, "",  MATCH_C_MOP_15, MASK_C_MOP_15, match_opcode, 0 },
+
 /* Zcmp instructions.  */
 {"cm.push",    0,  INSN_CLASS_ZCMP, "{Wcr},Wcp",  MATCH_CM_PUSH, MASK_CM_PUSH, match_opcode, 0 },
 {"cm.pop",     0,  INSN_CLASS_ZCMP, "{Wcr},Wcp",  MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 },