diff mbox series

[1/3] RISC-V: Add support for Zfbfmin extension

Message ID 20240606075953.28696-2-zengxiao@eswincomputing.com
State New
Headers
Series RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply

Commit Message

Xiao Zeng June 6, 2024, 7:59 a.m. UTC 
  This implements the Zfbfmin extension, as of version 1.0.

View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts>

1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and
  FMV.H.X instructions as defined in the Zfh extension.

2 The Zfhmin extension includes the following instructions from the Zfh
  extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in:
  <https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc>

3 Zfhmin extension depend on 'F'.

4 Simply put, just make Zfbfmin dependent on Zfhmin.

Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and
FMV.H.X instructions an independent extension to achieve precise dependency
relationships for the Zfbfmin.

5 For relevant information in gcc, please refer to:
  <https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zfbfmin.d: New test.
	* testsuite/gas/riscv/zfbfmin.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define.
	(MASK_FCVT_BF16_S): Ditto.
	(MATCH_FCVT_S_BF16): Ditto.
	(MASK_FCVT_S_BF16): Ditto.
	(DECLARE_INSN): New declarations for Zfbfmin.
	* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zfbfmin instructions.
---
 bfd/elfxx-riscv.c                    |  6 ++++++
 gas/NEWS                             |  2 ++
 gas/testsuite/gas/riscv/march-help.l |  1 +
 gas/testsuite/gas/riscv/zfbfmin.d    | 11 +++++++++++
 gas/testsuite/gas/riscv/zfbfmin.s    |  6 ++++++
 include/opcode/riscv-opc.h           |  8 ++++++++
 include/opcode/riscv.h               |  1 +
 opcodes/riscv-opc.c                  |  5 +++++
 8 files changed, 40 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
 create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 5cb063a68a9..1d70139725a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1222,6 +1222,7 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zihpm", "zicsr",		check_implicit_always},
   {"zcd", "d",		check_implicit_always},
   {"zcf", "f",		check_implicit_always},
+  {"zfbfmin", "zfhmin",	check_implicit_always},
   {"zfa", "f",		check_implicit_always},
   {"d", "f",		check_implicit_always},
   {"zfh", "zfhmin",	check_implicit_always},
@@ -1359,6 +1360,7 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zabha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zalrsc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zfbfmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfa",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2582,6 +2584,8 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	       && riscv_subset_supports (rps, "q"))
 	      || (riscv_subset_supports (rps, "zhinxmin")
 		  && riscv_subset_supports (rps, "zqinx")));
+    case INSN_CLASS_ZFBFMIN:
+      return riscv_subset_supports (rps, "zfbfmin");
     case INSN_CLASS_ZFA:
       return riscv_subset_supports (rps, "zfa");
     case INSN_CLASS_D_AND_ZFA:
@@ -2836,6 +2840,8 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
 	return "zhinxmin";
       else
 	return _("zfhmin' and `q', or `zhinxmin' and `zqinx");
+    case INSN_CLASS_ZFBFMIN:
+      return "zfbfmin";
     case INSN_CLASS_ZFA:
       return "zfa";
     case INSN_CLASS_D_AND_ZFA:
diff --git a/gas/NEWS b/gas/NEWS
index e51c3bbba6d..cdf30941894 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -21,6 +21,8 @@ 
 
 * Add support for RISC-V Zcmp extension with version 1.0.
 
+* Add support for RISC-V Zfbfmin extension with version 1.0.
+
 * The base register operand in D(X,B) and D(L,B) may be explicitly omitted
   in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0)
   D(X,%r0), D(L,0), and D(L,%r0).
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 5b5a36633e1..57c73b3074e 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -25,6 +25,7 @@  All available -march extensions for RISC-V:
 	zabha                                   1.0
 	zalrsc                                  1.0
 	zawrs                                   1.0
+	zfbfmin                                 1.0
 	zfa                                     1.0
 	zfh                                     1.0
 	zfhmin                                  1.0
diff --git a/gas/testsuite/gas/riscv/zfbfmin.d b/gas/testsuite/gas/riscv/zfbfmin.d
new file mode 100644
index 00000000000..7cacc0bd684
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfbfmin.d
@@ -0,0 +1,11 @@ 
+#as: -march=rv64i_zfbfmin
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+4485f553[ 	]+fcvt.bf16.s[ 	]+fa0,fa1
+[ 	]+[0-9a-f]+:[ 	]+44858553[ 	]+fcvt.bf16.s[ 	]+fa0,fa1,rne
+[ 	]+[0-9a-f]+:[ 	]+40658553[ 	]+fcvt.s.bf16[ 	]+fa0,fa1
diff --git a/gas/testsuite/gas/riscv/zfbfmin.s b/gas/testsuite/gas/riscv/zfbfmin.s
new file mode 100644
index 00000000000..c9a9af3e394
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfbfmin.s
@@ -0,0 +1,6 @@ 
+target:
+	# fcvt.bf16.s
+	fcvt.bf16.s	fa0, fa1
+	fcvt.bf16.s	fa0, fa1, rne
+	# fcvt.s.bf16
+	fcvt.s.bf16	fa0, fa1
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index cd957ef9b6f..ef33aeb1b36 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2365,6 +2365,11 @@ 
 #define MASK_WRS_NTO 0xffffffff
 #define MATCH_WRS_STO 0x01d00073
 #define MASK_WRS_STO 0xffffffff
+/* Zfbfmin intructions.  */
+#define MATCH_FCVT_BF16_S 0x44800053
+#define MASK_FCVT_BF16_S 0xfff0007f
+#define MATCH_FCVT_S_BF16 0x40600053
+#define MASK_FCVT_S_BF16 0xfff0007f
 /* Vendor-specific (CORE-V) Xcvmac instructions.  */
 #define MATCH_CV_MAC       0x9000302b
 #define MASK_CV_MAC        0xfe00707f
@@ -3969,6 +3974,9 @@  DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL)
 /* Zawrs instructions.  */
 DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
 DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
+/* Zfbfmin instructions.  */
+DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
+DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
 /* Zvbb/Zvkb instructions.  */
 DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
 DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 0653ae57255..dfb86966b0a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -449,6 +449,7 @@  enum riscv_insn_class
   INSN_CLASS_ZFHMIN_INX,
   INSN_CLASS_ZFHMIN_AND_D_INX,
   INSN_CLASS_ZFHMIN_AND_Q_INX,
+  INSN_CLASS_ZFBFMIN,
   INSN_CLASS_ZFA,
   INSN_CLASS_D_AND_ZFA,
   INSN_CLASS_Q_AND_ZFA,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4bb54b7eaf0..1ccf0685b2b 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -829,6 +829,11 @@  const struct riscv_opcode riscv_opcodes[] =
 {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX,   "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 },
 {"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX,   "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
 
+/* Zfbfmin instructions.  */
+{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S",   MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
+{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 },
+{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S",   MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
+
 /* Single-precision floating-point instruction subset.  */
 {"frcsr",      0, INSN_CLASS_F_INX,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
 {"frsr",       0, INSN_CLASS_F_INX,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },