diff mbox series

[PING,2/3] RISC-V: Add support for Zvfbfmin extension

Message ID	20240605013613.78830-3-zengxiao@eswincomputing.com
State	New
Headers	DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6F6633A72103 From: Xiao Zeng <zengxiao@eswincomputing.com> To: binutils@sourceware.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, nelson@rivosinc.com, zhengyu@eswincomputing.com, Xiao Zeng <zengxiao@eswincomputing.com> Subject: [PING] [PATCH 2/3] RISC-V: Add support for Zvfbfmin extension Date: Wed, 5 Jun 2024 09:36:12 +0800 Message-Id: <20240605013613.78830-3-zengxiao@eswincomputing.com> In-Reply-To: <20240605013613.78830-1-zengxiao@eswincomputing.com> References: <20240605013613.78830-1-zengxiao@eswincomputing.com> Precedence: list Errors-To: binutils-bounces+patchwork=sourceware.org@sourceware.org
Series	RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension \| [PING,0/3] RISC-V: Add support for Zfbfmin Zvfbfmin and Zvfbfwma extension [PING,1/3] RISC-V: Add support for Zfbfmin extension [PING,2/3] RISC-V: Add support for Zvfbfmin extension [PING,3/3] RISC-V: Add support for Zvfbfwma extension

Checks

Context	Check	Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm	success	Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64	success	Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64	success	Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-arm	success	Testing passed

Commit Message

Xiao Zeng June 5, 2024, 1:36 a.m. UTC

  This implements the Zvfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts>

Depending on different usage scenarios, the Zvfbfmin extension may
depend on 'V' or 'Zve32f'. This patch only implements dependencies
in scenario of Embedded Processor. In scenario of Application
Processor, it is necessary to explicitly indicate the dependent
'V' extension.

For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Updated.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zvfbfmin-rv32.d: New test.
	* testsuite/gas/riscv/zvfbfmin-rv32.s: New test.
	* testsuite/gas/riscv/zvfbfmin-rv64.d: New test.
	* testsuite/gas/riscv/zvfbfmin-rv64.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
	(MASK_VFNCVTBF16_F_F_W): Ditto.
	(MATCH_VFWCVTBF16_F_F_V): Ditto.
	(MASK_VFWCVTBF16_F_F_V): Ditto.
	(DECLARE_INSN): New declarations for Zvfbfmin.
	* opcode/riscv.h (enum riscv_insn_class): Add
	INSN_CLASS_ZVFBFMIN

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvfbfmin instructions.
---
 bfd/elfxx-riscv.c                       |  6 ++++++
 gas/NEWS                                |  2 ++
 gas/testsuite/gas/riscv/march-help.l    |  1 +
 gas/testsuite/gas/riscv/zvfbfmin-rv32.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvfbfmin-rv32.s |  7 +++++++
 gas/testsuite/gas/riscv/zvfbfmin-rv64.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvfbfmin-rv64.s |  7 +++++++
 include/opcode/riscv-opc.h              |  8 ++++++++
 include/opcode/riscv.h                  |  1 +
 opcodes/riscv-opc.c                     |  4 ++++
 10 files changed, 60 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.d
 create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.s
 create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.d
 create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.s

Comments

Nelson Chu June 6, 2024, 2:33 a.m. UTC | #1

On Wed, Jun 5, 2024 at 9:30 AM Xiao Zeng <zengxiao@eswincomputing.com>
wrote:

> This implements the Zvfbfmin extension, as of version 1.0.
> View detailed information in:
> <
> https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts
> >
>
> Depending on different usage scenarios, the Zvfbfmin extension may
> depend on 'V' or 'Zve32f'. This patch only implements dependencies
> in scenario of Embedded Processor. In scenario of Application
> Processor, it is necessary to explicitly indicate the dependent
> 'V' extension.
>
> For relevant information in gcc, please refer to:
> <
> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09
> >
>
> bfd/ChangeLog:
>
>         * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
>         (riscv_multi_subset_supports_ext): Ditto.
>
> gas/ChangeLog:
>
>         * NEWS: Updated.
>         * testsuite/gas/riscv/march-help.l: Ditto.
>         * testsuite/gas/riscv/zvfbfmin-rv32.d: New test.
>         * testsuite/gas/riscv/zvfbfmin-rv32.s: New test.
>         * testsuite/gas/riscv/zvfbfmin-rv64.d: New test.
>         * testsuite/gas/riscv/zvfbfmin-rv64.s: New test.
>
> include/ChangeLog:
>
>         * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
>         (MASK_VFNCVTBF16_F_F_W): Ditto.
>         (MATCH_VFWCVTBF16_F_F_V): Ditto.
>         (MASK_VFWCVTBF16_F_F_V): Ditto.
>         (DECLARE_INSN): New declarations for Zvfbfmin.
>         * opcode/riscv.h (enum riscv_insn_class): Add
>         INSN_CLASS_ZVFBFMIN
>
> opcodes/ChangeLog:
>
>         * riscv-opc.c: Add Zvfbfmin instructions.
> ---
>  bfd/elfxx-riscv.c                       |  6 ++++++
>  gas/NEWS                                |  2 ++
>  gas/testsuite/gas/riscv/march-help.l    |  1 +
>  gas/testsuite/gas/riscv/zvfbfmin-rv32.d | 12 ++++++++++++
>  gas/testsuite/gas/riscv/zvfbfmin-rv32.s |  7 +++++++
>  gas/testsuite/gas/riscv/zvfbfmin-rv64.d | 12 ++++++++++++
>  gas/testsuite/gas/riscv/zvfbfmin-rv64.s |  7 +++++++
>  include/opcode/riscv-opc.h              |  8 ++++++++
>  include/opcode/riscv.h                  |  1 +
>  opcodes/riscv-opc.c                     |  4 ++++
>  10 files changed, 60 insertions(+)
>  create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.d
>  create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.s
>  create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.d
>  create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index d9709a232e6..3d303f02b58 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1192,6 +1192,7 @@ static struct riscv_implicit_subset
> riscv_implicit_subsets[] =
>    {"v", "zve64d",      check_implicit_always},
>    {"v", "zvl128b",     check_implicit_always},
>    {"zabha", "a",       check_implicit_always},
> +  {"zvfbfmin", "zve32f",       check_implicit_always},
>    {"zvfh", "zvfhmin",  check_implicit_always},
>    {"zvfh", "zfhmin",   check_implicit_always},
>    {"zvfhmin", "zve32f",        check_implicit_always},
> @@ -1394,6 +1395,7 @@ static struct riscv_supported_ext
> riscv_supported_std_z_ext[] =
>    {"zvbb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvbc",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvfh",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> +  {"zvfbfmin",         ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvfhmin",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvkb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>    {"zvkg",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> @@ -2644,6 +2646,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
>        return riscv_subset_supports (rps, "zvbb");
>      case INSN_CLASS_ZVBC:
>        return riscv_subset_supports (rps, "zvbc");
> +    case INSN_CLASS_ZVFBFMIN:
> +      return riscv_subset_supports (rps, "zvfbfmin");
>

I would like to keep the bf16 stuff together.


>      case INSN_CLASS_ZVKB:
>        return riscv_subset_supports (rps, "zvkb");
>      case INSN_CLASS_ZVKG:
> @@ -2908,6 +2912,8 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
>        return _("zvbb");
>      case INSN_CLASS_ZVBC:
>        return _("zvbc");
> +    case INSN_CLASS_ZVFBFMIN:
> +      return "zvfbfmin";
>

Likewise, keep the bf16 stuff together.


>      case INSN_CLASS_ZVKB:
>        return _("zvkb");
>      case INSN_CLASS_ZVKG:
> diff --git a/gas/NEWS b/gas/NEWS
> index b88c54fc5c3..2c75966d0ce 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
>  -*- text -*-
>
> +* Add support for RISC-V Zvfbfmin extension with version 1.0.
> +
>  * Add support for RISC-V Zfbfmin extension with version 1.0.
>
>  * In x86 Intel syntax undue mnemonic suffixes are now warned about.  This
> is
> diff --git a/gas/testsuite/gas/riscv/march-help.l
> b/gas/testsuite/gas/riscv/march-help.l
> index 9deaa841622..1a2ac1eaa08 100644
> --- a/gas/testsuite/gas/riscv/march-help.l
> +++ b/gas/testsuite/gas/riscv/march-help.l
> @@ -59,6 +59,7 @@ All available -march extensions for RISC-V:
>         zvbb                                    1.0
>         zvbc                                    1.0
>         zvfh                                    1.0
> +       zvfbfmin                                1.0
>         zvfhmin                                 1.0
>         zvkb                                    1.0
>         zvkg                                    1.0
> diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
> b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
> new file mode 100644
> index 00000000000..b52e19d30be
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv32i_zvfbfmin
> +#objdump: -d
> +
> +.*:[   ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[      ]+[0-9a-f]+:[   ]+4a8e9257[     ]+vfncvtbf16.f.f.w[
>  ]+v4,v8
> +[      ]+[0-9a-f]+:[   ]+488e9257[     ]+vfncvtbf16.f.f.w[
>  ]+v4,v8,v0.t
> +[      ]+[0-9a-f]+:[   ]+4a869257[     ]+vfwcvtbf16.f.f.v[
>  ]+v4,v8
> +[      ]+[0-9a-f]+:[   ]+48869257[     ]+vfwcvtbf16.f.f.v[
>  ]+v4,v8,v0.t
> diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
> b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
> new file mode 100644
> index 00000000000..9a4493d84d1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
> @@ -0,0 +1,7 @@
> +target:
> +       # vfncvtbf16.f.f.w
> +       vfncvtbf16.f.f.w v4, v8
> +       vfncvtbf16.f.f.w v4, v8, v0.t
> +       # vfwcvtbf16.f.f.v
> +       vfwcvtbf16.f.f.v v4, v8
> +       vfwcvtbf16.f.f.v v4, v8, v0.t
> diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
> b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
> new file mode 100644
> index 00000000000..ce973812fe1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv64iv_zvfbfmin
> +#objdump: -d
> +
> +.*:[   ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[      ]+[0-9a-f]+:[   ]+4a8e9257[     ]+vfncvtbf16.f.f.w[     ]+v4,v8
> +[      ]+[0-9a-f]+:[   ]+488e9257[     ]+vfncvtbf16.f.f.w[
>  ]+v4,v8,v0.t
> +[      ]+[0-9a-f]+:[   ]+4a869257[     ]+vfwcvtbf16.f.f.v[     ]+v4,v8
> +[      ]+[0-9a-f]+:[   ]+48869257[     ]+vfwcvtbf16.f.f.v[
>  ]+v4,v8,v0.t
> diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
> b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
> new file mode 100644
> index 00000000000..9a4493d84d1
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
> @@ -0,0 +1,7 @@
> +target:
> +       # vfncvtbf16.f.f.w
> +       vfncvtbf16.f.f.w v4, v8
> +       vfncvtbf16.f.f.w v4, v8, v0.t
> +       # vfwcvtbf16.f.f.v
> +       vfwcvtbf16.f.f.v v4, v8
> +       vfwcvtbf16.f.f.v v4, v8, v0.t
>

If rv32 and rv64 have the same encodings, then no need to add two test
cases for them, just one zvfbfmin.s/d is enough.


> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 26d60bc585e..32b971fb2b3 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2370,6 +2370,11 @@
>  #define MASK_FCVT_BF16_S 0xfff0007f
>  #define MATCH_FCVT_S_BF16 0x40600053
>  #define MASK_FCVT_S_BF16 0xfff0007f
> +/* Zvfbfmin intructions.  */
> +#define MATCH_VFNCVTBF16_F_F_W 0x480e9057
> +#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
> +#define MATCH_VFWCVTBF16_F_F_V 0x48069057
> +#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
>  /* Vendor-specific (CORE-V) Xcvmac instructions.  */
>  #define MATCH_CV_MAC       0x9000302b
>  #define MASK_CV_MAC        0xfe00707f
> @@ -3920,6 +3925,9 @@ DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
>  /* Zfbfmin instructions.  */
>  DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
>  DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
> +/* Zvfbfmin instructions.  */
> +DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W,
> MASK_VFNCVTBF16_F_F_W)
> +DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V,
> MASK_VFWCVTBF16_F_F_V)
>  /* Zvbb/Zvkb instructions.  */
>  DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
>  DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 0e58dbe3d03..4d21b6c3926 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -471,6 +471,7 @@ enum riscv_insn_class
>    INSN_CLASS_ZVEF,
>    INSN_CLASS_ZVBB,
>    INSN_CLASS_ZVBC,
> +  INSN_CLASS_ZVFBFMIN,
>

Likewise, keep the bf16 stuff together.


>    INSN_CLASS_ZVKB,
>    INSN_CLASS_ZVKG,
>    INSN_CLASS_ZVKNED,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 9f99aa6c792..0a470aee7cc 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -2041,6 +2041,10 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV,
> MASK_VCLMULH_VV, match_opcode, 0},
>  {"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX,
> MASK_VCLMULH_VX, match_opcode, 0},
>
> +/* Zvfbfmin instructions.  */
> +{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm",
> MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
> +{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm",
> MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
> +
>

Likewise, keep the bf16 stuff together.


>  /* Zvkg instructions.  */
>  {"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV,
> MASK_VGHSH_VV, match_opcode, 0},
>  {"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV,
> MASK_VGMUL_VV, match_opcode, 0},
> --
> 2.17.1
>
>

Nelson Chu June 6, 2024, 2:49 a.m. UTC | #2

On Thu, Jun 6, 2024 at 10:33 AM Nelson Chu <nelson@rivosinc.com> wrote:

>      case INSN_CLASS_ZVBC:
>>        return riscv_subset_supports (rps, "zvbc");
>> +    case INSN_CLASS_ZVFBFMIN:
>> +      return riscv_subset_supports (rps, "zvfbfmin");
>>
>
> I would like to keep the bf16 stuff together.
>

I just noticed that since zfh and zvfh are not placed together, it should
be fine that zvfbfmin is placed with zvfh.  Alphabetical order here is not
important since parser will handle it.  It would be good if the related
stuff was put together, so that it is easier to maintain.

Nelson

Xiao Zeng June 6, 2024, 6:22 a.m. UTC | #3

2024-06-06 10:33  Nelson Chu <nelson@rivosinc.com> wrote:
>
>On Wed, Jun 5, 2024 at 9:30 AM Xiao Zeng <zengxiao@eswincomputing.com>
>wrote:
>
>> This implements the Zvfbfmin extension, as of version 1.0.
>> View detailed information in:
>> <
>> https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zvfbfmin---vector-bf16-converts
>> >
>>
>> Depending on different usage scenarios, the Zvfbfmin extension may
>> depend on 'V' or 'Zve32f'. This patch only implements dependencies
>> in scenario of Embedded Processor. In scenario of Application
>> Processor, it is necessary to explicitly indicate the dependent
>> 'V' extension.
>>
>> For relevant information in gcc, please refer to:
>> <
>> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1ddf65c5fc6ba7cf5826e1c02c569c923a541c09
>> >
>>
>> bfd/ChangeLog:
>>
>>         * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zvfbfmin.
>>         (riscv_multi_subset_supports_ext): Ditto.
>>
>> gas/ChangeLog:
>>
>>         * NEWS: Updated.
>>         * testsuite/gas/riscv/march-help.l: Ditto.
>>         * testsuite/gas/riscv/zvfbfmin-rv32.d: New test.
>>         * testsuite/gas/riscv/zvfbfmin-rv32.s: New test.
>>         * testsuite/gas/riscv/zvfbfmin-rv64.d: New test.
>>         * testsuite/gas/riscv/zvfbfmin-rv64.s: New test.
>>
>> include/ChangeLog:
>>
>>         * opcode/riscv-opc.h (MATCH_VFNCVTBF16_F_F_W): Define.
>>         (MASK_VFNCVTBF16_F_F_W): Ditto.
>>         (MATCH_VFWCVTBF16_F_F_V): Ditto.
>>         (MASK_VFWCVTBF16_F_F_V): Ditto.
>>         (DECLARE_INSN): New declarations for Zvfbfmin.
>>         * opcode/riscv.h (enum riscv_insn_class): Add
>>         INSN_CLASS_ZVFBFMIN
>>
>> opcodes/ChangeLog:
>>
>>         * riscv-opc.c: Add Zvfbfmin instructions.
>> ---
>>  bfd/elfxx-riscv.c                       |  6 ++++++
>>  gas/NEWS                                |  2 ++
>>  gas/testsuite/gas/riscv/march-help.l    |  1 +
>>  gas/testsuite/gas/riscv/zvfbfmin-rv32.d | 12 ++++++++++++
>>  gas/testsuite/gas/riscv/zvfbfmin-rv32.s |  7 +++++++
>>  gas/testsuite/gas/riscv/zvfbfmin-rv64.d | 12 ++++++++++++
>>  gas/testsuite/gas/riscv/zvfbfmin-rv64.s |  7 +++++++
>>  include/opcode/riscv-opc.h              |  8 ++++++++
>>  include/opcode/riscv.h                  |  1 +
>>  opcodes/riscv-opc.c                     |  4 ++++
>>  10 files changed, 60 insertions(+)
>>  create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.d
>>  create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv32.s
>>  create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.d
>>  create mode 100644 gas/testsuite/gas/riscv/zvfbfmin-rv64.s
>>
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index d9709a232e6..3d303f02b58 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1192,6 +1192,7 @@ static struct riscv_implicit_subset
>> riscv_implicit_subsets[] =
>>    {"v", "zve64d",      check_implicit_always},
>>    {"v", "zvl128b",     check_implicit_always},
>>    {"zabha", "a",       check_implicit_always},
>> +  {"zvfbfmin", "zve32f",       check_implicit_always},
>>    {"zvfh", "zvfhmin",  check_implicit_always},
>>    {"zvfh", "zfhmin",   check_implicit_always},
>>    {"zvfhmin", "zve32f",        check_implicit_always},
>> @@ -1394,6 +1395,7 @@ static struct riscv_supported_ext
>> riscv_supported_std_z_ext[] =
>>    {"zvbb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>>    {"zvbc",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>>    {"zvfh",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>> +  {"zvfbfmin",         ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>>    {"zvfhmin",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>>    {"zvkb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>>    {"zvkg",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
>> @@ -2644,6 +2646,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
>> *rps,
>>        return riscv_subset_supports (rps, "zvbb");
>>      case INSN_CLASS_ZVBC:
>>        return riscv_subset_supports (rps, "zvbc");
>> +    case INSN_CLASS_ZVFBFMIN:
>> +      return riscv_subset_supports (rps, "zvfbfmin");
>>
>
>I would like to keep the bf16 stuff together.
>
>
>>      case INSN_CLASS_ZVKB:
>>        return riscv_subset_supports (rps, "zvkb");
>>      case INSN_CLASS_ZVKG:
>> @@ -2908,6 +2912,8 @@ riscv_multi_subset_supports_ext
>> (riscv_parse_subset_t *rps,
>>        return _("zvbb");
>>      case INSN_CLASS_ZVBC:
>>        return _("zvbc");
>> +    case INSN_CLASS_ZVFBFMIN:
>> +      return "zvfbfmin";
>>
>
>Likewise, keep the bf16 stuff together. 
According to the subsequent emails, this place will not be modified.

>
>
>>      case INSN_CLASS_ZVKB:
>>        return _("zvkb");
>>      case INSN_CLASS_ZVKG:
>> diff --git a/gas/NEWS b/gas/NEWS
>> index b88c54fc5c3..2c75966d0ce 100644
>> --- a/gas/NEWS
>> +++ b/gas/NEWS
>> @@ -1,5 +1,7 @@
>>  -*- text -*-
>>
>> +* Add support for RISC-V Zvfbfmin extension with version 1.0.
>> +
>>  * Add support for RISC-V Zfbfmin extension with version 1.0.
>>
>>  * In x86 Intel syntax undue mnemonic suffixes are now warned about.  This
>> is
>> diff --git a/gas/testsuite/gas/riscv/march-help.l
>> b/gas/testsuite/gas/riscv/march-help.l
>> index 9deaa841622..1a2ac1eaa08 100644
>> --- a/gas/testsuite/gas/riscv/march-help.l
>> +++ b/gas/testsuite/gas/riscv/march-help.l
>> @@ -59,6 +59,7 @@ All available -march extensions for RISC-V:
>>         zvbb                                    1.0
>>         zvbc                                    1.0
>>         zvfh                                    1.0
>> +       zvfbfmin                                1.0
>>         zvfhmin                                 1.0
>>         zvkb                                    1.0
>>         zvkg                                    1.0
>> diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
>> b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
>> new file mode 100644
>> index 00000000000..b52e19d30be
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
>> @@ -0,0 +1,12 @@
>> +#as: -march=rv32i_zvfbfmin
>> +#objdump: -d
>> +
>> +.*:[   ]+file format .*
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[      ]+[0-9a-f]+:[   ]+4a8e9257[     ]+vfncvtbf16.f.f.w[
>>  ]+v4,v8
>> +[      ]+[0-9a-f]+:[   ]+488e9257[     ]+vfncvtbf16.f.f.w[
>>  ]+v4,v8,v0.t
>> +[      ]+[0-9a-f]+:[   ]+4a869257[     ]+vfwcvtbf16.f.f.v[
>>  ]+v4,v8
>> +[      ]+[0-9a-f]+:[   ]+48869257[     ]+vfwcvtbf16.f.f.v[
>>  ]+v4,v8,v0.t
>> diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
>> b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
>> new file mode 100644
>> index 00000000000..9a4493d84d1
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
>> @@ -0,0 +1,7 @@
>> +target:
>> +       # vfncvtbf16.f.f.w
>> +       vfncvtbf16.f.f.w v4, v8
>> +       vfncvtbf16.f.f.w v4, v8, v0.t
>> +       # vfwcvtbf16.f.f.v
>> +       vfwcvtbf16.f.f.v v4, v8
>> +       vfwcvtbf16.f.f.v v4, v8, v0.t
>> diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
>> b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
>> new file mode 100644
>> index 00000000000..ce973812fe1
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
>> @@ -0,0 +1,12 @@
>> +#as: -march=rv64iv_zvfbfmin
>> +#objdump: -d
>> +
>> +.*:[   ]+file format .*
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[      ]+[0-9a-f]+:[   ]+4a8e9257[     ]+vfncvtbf16.f.f.w[     ]+v4,v8
>> +[      ]+[0-9a-f]+:[   ]+488e9257[     ]+vfncvtbf16.f.f.w[
>>  ]+v4,v8,v0.t
>> +[      ]+[0-9a-f]+:[   ]+4a869257[     ]+vfwcvtbf16.f.f.v[     ]+v4,v8
>> +[      ]+[0-9a-f]+:[   ]+48869257[     ]+vfwcvtbf16.f.f.v[
>>  ]+v4,v8,v0.t
>> diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
>> b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
>> new file mode 100644
>> index 00000000000..9a4493d84d1
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
>> @@ -0,0 +1,7 @@
>> +target:
>> +       # vfncvtbf16.f.f.w
>> +       vfncvtbf16.f.f.w v4, v8
>> +       vfncvtbf16.f.f.w v4, v8, v0.t
>> +       # vfwcvtbf16.f.f.v
>> +       vfwcvtbf16.f.f.v v4, v8
>> +       vfwcvtbf16.f.f.v v4, v8, v0.t
>>
>
>If rv32 and rv64 have the same encodings, then no need to add two test
>cases for them, just one zvfbfmin.s/d is enough. 
Fixed.

>
>
>> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> index 26d60bc585e..32b971fb2b3 100644
>> --- a/include/opcode/riscv-opc.h
>> +++ b/include/opcode/riscv-opc.h
>> @@ -2370,6 +2370,11 @@
>>  #define MASK_FCVT_BF16_S 0xfff0007f
>>  #define MATCH_FCVT_S_BF16 0x40600053
>>  #define MASK_FCVT_S_BF16 0xfff0007f
>> +/* Zvfbfmin intructions.  */
>> +#define MATCH_VFNCVTBF16_F_F_W 0x480e9057
>> +#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
>> +#define MATCH_VFWCVTBF16_F_F_V 0x48069057
>> +#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
>>  /* Vendor-specific (CORE-V) Xcvmac instructions.  */
>>  #define MATCH_CV_MAC       0x9000302b
>>  #define MASK_CV_MAC        0xfe00707f
>> @@ -3920,6 +3925,9 @@ DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
>>  /* Zfbfmin instructions.  */
>>  DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
>>  DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
>> +/* Zvfbfmin instructions.  */
>> +DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W,
>> MASK_VFNCVTBF16_F_F_W)
>> +DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V,
>> MASK_VFWCVTBF16_F_F_V)
>>  /* Zvbb/Zvkb instructions.  */
>>  DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
>>  DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>> index 0e58dbe3d03..4d21b6c3926 100644
>> --- a/include/opcode/riscv.h
>> +++ b/include/opcode/riscv.h
>> @@ -471,6 +471,7 @@ enum riscv_insn_class
>>    INSN_CLASS_ZVEF,
>>    INSN_CLASS_ZVBB,
>>    INSN_CLASS_ZVBC,
>> +  INSN_CLASS_ZVFBFMIN,
>>
>
>Likewise, keep the bf16 stuff together. 
Likewise, according to the subsequent emails, this place will not be modified.

>
>
>>    INSN_CLASS_ZVKB,
>>    INSN_CLASS_ZVKG,
>>    INSN_CLASS_ZVKNED,
>> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>> index 9f99aa6c792..0a470aee7cc 100644
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -2041,6 +2041,10 @@ const struct riscv_opcode riscv_opcodes[] =
>>  {"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV,
>> MASK_VCLMULH_VV, match_opcode, 0},
>>  {"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX,
>> MASK_VCLMULH_VX, match_opcode, 0},
>>
>> +/* Zvfbfmin instructions.  */
>> +{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm",
>> MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
>> +{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm",
>> MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
>> +
>>
>
>Likewise, keep the bf16 stuff together. 
Likewise, according to the subsequent emails, this place will not be modified.

>
>
>>  /* Zvkg instructions.  */
>>  {"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV,
>> MASK_VGHSH_VV, match_opcode, 0},
>>  {"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV,
>> MASK_VGMUL_VV, match_opcode, 0},
>> --
>> 2.17.1
>>
>>
Thanks
Xiao Zeng

Xiao Zeng June 6, 2024, 6:23 a.m. UTC | #4

2024-06-06 10:49  Nelson Chu <nelson@rivosinc.com> wrote:
>
>On Thu, Jun 6, 2024 at 10:33 AM Nelson Chu <nelson@rivosinc.com> wrote:
>
>>      case INSN_CLASS_ZVBC:
>>>        return riscv_subset_supports (rps, "zvbc");
>>> +    case INSN_CLASS_ZVFBFMIN:
>>> +      return riscv_subset_supports (rps, "zvfbfmin");
>>>
>>
>> I would like to keep the bf16 stuff together.
>>
>
>I just noticed that since zfh and zvfh are not placed together, it should
>be fine that zvfbfmin is placed with zvfh.  
Good.

>Alphabetical order here is not
>important since parser will handle it.  It would be good if the related
>stuff was put together, so that it is easier to maintain.
>
>Nelson
Thanks
Xiao Zeng

diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index d9709a232e6..3d303f02b58 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1192,6 +1192,7 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"v", "zve64d",	check_implicit_always},
   {"v", "zvl128b",	check_implicit_always},
   {"zabha", "a",	check_implicit_always},
+  {"zvfbfmin", "zve32f",	check_implicit_always},
   {"zvfh", "zvfhmin",	check_implicit_always},
   {"zvfh", "zfhmin",	check_implicit_always},
   {"zvfhmin", "zve32f",	check_implicit_always},
@@ -1394,6 +1395,7 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvfbfmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2644,6 +2646,8 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_ZVBC:
       return riscv_subset_supports (rps, "zvbc");
+    case INSN_CLASS_ZVFBFMIN:
+      return riscv_subset_supports (rps, "zvfbfmin");
     case INSN_CLASS_ZVKB:
       return riscv_subset_supports (rps, "zvkb");
     case INSN_CLASS_ZVKG:
@@ -2908,6 +2912,8 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvbb");
     case INSN_CLASS_ZVBC:
       return _("zvbc");
+    case INSN_CLASS_ZVFBFMIN:
+      return "zvfbfmin";
     case INSN_CLASS_ZVKB:
       return _("zvkb");
     case INSN_CLASS_ZVKG:
diff --git a/gas/NEWS b/gas/NEWS
index b88c54fc5c3..2c75966d0ce 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@ 
 -*- text -*-
 
+* Add support for RISC-V Zvfbfmin extension with version 1.0.
+
 * Add support for RISC-V Zfbfmin extension with version 1.0.
 
 * In x86 Intel syntax undue mnemonic suffixes are now warned about.  This is
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 9deaa841622..1a2ac1eaa08 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -59,6 +59,7 @@  All available -march extensions for RISC-V:
 	zvbb                                    1.0
 	zvbc                                    1.0
 	zvfh                                    1.0
+	zvfbfmin                                1.0
 	zvfhmin                                 1.0
 	zvkb                                    1.0
 	zvkg                                    1.0
diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.d b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
new file mode 100644
index 00000000000..b52e19d30be
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.d
@@ -0,0 +1,12 @@ 
+#as: -march=rv32i_zvfbfmin
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+4a8e9257[ 	]+vfncvtbf16.f.f.w[ 		]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+488e9257[ 	]+vfncvtbf16.f.f.w[ 		]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a869257[ 	]+vfwcvtbf16.f.f.v[ 		]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48869257[ 	]+vfwcvtbf16.f.f.v[ 		]+v4,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv32.s b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
new file mode 100644
index 00000000000..9a4493d84d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin-rv32.s
@@ -0,0 +1,7 @@ 
+target:
+	# vfncvtbf16.f.f.w
+	vfncvtbf16.f.f.w v4, v8
+	vfncvtbf16.f.f.w v4, v8, v0.t
+	# vfwcvtbf16.f.f.v
+	vfwcvtbf16.f.f.v v4, v8
+	vfwcvtbf16.f.f.v v4, v8, v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.d b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
new file mode 100644
index 00000000000..ce973812fe1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.d
@@ -0,0 +1,12 @@ 
+#as: -march=rv64iv_zvfbfmin
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+4a8e9257[ 	]+vfncvtbf16.f.f.w[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+488e9257[ 	]+vfncvtbf16.f.f.w[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+4a869257[ 	]+vfwcvtbf16.f.f.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+48869257[ 	]+vfwcvtbf16.f.f.v[ 	]+v4,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/zvfbfmin-rv64.s b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
new file mode 100644
index 00000000000..9a4493d84d1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvfbfmin-rv64.s
@@ -0,0 +1,7 @@ 
+target:
+	# vfncvtbf16.f.f.w
+	vfncvtbf16.f.f.w v4, v8
+	vfncvtbf16.f.f.w v4, v8, v0.t
+	# vfwcvtbf16.f.f.v
+	vfwcvtbf16.f.f.v v4, v8
+	vfwcvtbf16.f.f.v v4, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 26d60bc585e..32b971fb2b3 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2370,6 +2370,11 @@ 
 #define MASK_FCVT_BF16_S 0xfff0007f
 #define MATCH_FCVT_S_BF16 0x40600053
 #define MASK_FCVT_S_BF16 0xfff0007f
+/* Zvfbfmin intructions.  */
+#define MATCH_VFNCVTBF16_F_F_W 0x480e9057
+#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
+#define MATCH_VFWCVTBF16_F_F_V 0x48069057
+#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
 /* Vendor-specific (CORE-V) Xcvmac instructions.  */
 #define MATCH_CV_MAC       0x9000302b
 #define MASK_CV_MAC        0xfe00707f
@@ -3920,6 +3925,9 @@  DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
 /* Zfbfmin instructions.  */
 DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
 DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
+/* Zvfbfmin instructions.  */
+DECLARE_INSN(VFNCVTBF16_F_F_W, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
+DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
 /* Zvbb/Zvkb instructions.  */
 DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
 DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 0e58dbe3d03..4d21b6c3926 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -471,6 +471,7 @@  enum riscv_insn_class
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
+  INSN_CLASS_ZVFBFMIN,
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 9f99aa6c792..0a470aee7cc 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2041,6 +2041,10 @@  const struct riscv_opcode riscv_opcodes[] =
 {"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
 {"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
 
+/* Zvfbfmin instructions.  */
+{"vfncvtbf16.f.f.w", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W, match_opcode, 0},
+{"vfwcvtbf16.f.f.v", 0, INSN_CLASS_ZVFBFMIN, "Vd,VtVm", MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V, match_opcode, 0},
+
 /* Zvkg instructions.  */
 {"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
 {"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},