[PING,1/3] RISC-V: Add support for Zfbfmin extension
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Commit Message
This implements the Zfbfmin extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts>
1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and
FMV.H.X instructions as defined in the Zfh extension.
2 The Zfhmin extension includes the following instructions from the Zfh
extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc>
3 Zfhmin extension depend on 'F'.
4 Simply put, just make Zfbfmin dependent on Zfhmin.
Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and
FMV.H.X instructions an independent extension to achieve precise dependency
relationships for the Zfbfmin.
5 For relevant information in gcc, please refer to:
<https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zfbfmin.d: New test.
* testsuite/gas/riscv/zfbfmin.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define.
(MASK_FCVT_BF16_S): Ditto.
(MATCH_FCVT_S_BF16): Ditto.
(MASK_FCVT_S_BF16): Ditto.
(DECLARE_INSN): New declarations for Zfbfmin.
* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN.
opcodes/ChangeLog:
* riscv-opc.c: Add Zfbfmin instructions.
---
bfd/elfxx-riscv.c | 6 ++++++
gas/NEWS | 2 ++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++
gas/testsuite/gas/riscv/zfbfmin.s | 6 ++++++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 5 +++++
8 files changed, 40 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s
Comments
On Wed, Jun 5, 2024 at 9:30 AM Xiao Zeng <zengxiao@eswincomputing.com>
wrote:
> This implements the Zfbfmin extension, as of version 1.0.
>
> View detailed information in:
> <
> https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts
> >
>
> 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and
> FMV.H.X instructions as defined in the Zfh extension.
>
> 2 The Zfhmin extension includes the following instructions from the Zfh
> extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in:
> <https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc>
>
> 3 Zfhmin extension depend on 'F'.
>
> 4 Simply put, just make Zfbfmin dependent on Zfhmin.
>
> Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and
> FMV.H.X instructions an independent extension to achieve precise dependency
> relationships for the Zfbfmin.
>
> 5 For relevant information in gcc, please refer to:
> <
> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31
> >
>
> bfd/ChangeLog:
>
> * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin.
> (riscv_multi_subset_supports_ext): Ditto.
>
> gas/ChangeLog:
>
> * NEWS: Updated.
> * testsuite/gas/riscv/march-help.l: Ditto.
> * testsuite/gas/riscv/zfbfmin.d: New test.
> * testsuite/gas/riscv/zfbfmin.s: New test.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define.
> (MASK_FCVT_BF16_S): Ditto.
> (MATCH_FCVT_S_BF16): Ditto.
> (MASK_FCVT_S_BF16): Ditto.
> (DECLARE_INSN): New declarations for Zfbfmin.
> * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN.
>
> opcodes/ChangeLog:
>
> * riscv-opc.c: Add Zfbfmin instructions.
> ---
> bfd/elfxx-riscv.c | 6 ++++++
> gas/NEWS | 2 ++
> gas/testsuite/gas/riscv/march-help.l | 1 +
> gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++
> gas/testsuite/gas/riscv/zfbfmin.s | 6 ++++++
> include/opcode/riscv-opc.h | 8 ++++++++
> include/opcode/riscv.h | 1 +
> opcodes/riscv-opc.c | 5 +++++
> 8 files changed, 40 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
> create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index dfacb87eda0..d9709a232e6 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1224,6 +1224,7 @@ static struct riscv_implicit_subset
> riscv_implicit_subsets[] =
> {"zcf", "f", check_implicit_always},
> {"zfa", "f", check_implicit_always},
> {"d", "f", check_implicit_always},
> + {"zfbfmin", "zfhmin", check_implicit_always},
> {"zfh", "zfhmin", check_implicit_always},
> {"zfhmin", "f", check_implicit_always},
> {"f", "zicsr", check_implicit_always},
> @@ -1360,6 +1361,7 @@ static struct riscv_supported_ext
> riscv_supported_std_z_ext[] =
> {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> @@ -2561,6 +2563,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
> case INSN_CLASS_Q_INX:
> return (riscv_subset_supports (rps, "q")
> || riscv_subset_supports (rps, "zqinx"));
> + case INSN_CLASS_ZFBFMIN:
> + return riscv_subset_supports (rps, "zfbfmin");
>
Placed before INSN_CLASS_ZFA like the following change?
> case INSN_CLASS_ZFH_INX:
> return (riscv_subset_supports (rps, "zfh")
> || riscv_subset_supports (rps, "zhinx"));
> @@ -2827,6 +2831,8 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
> return "zhinxmin";
> else
> return _("zfhmin' and `q', or `zhinxmin' and `zqinx");
> + case INSN_CLASS_ZFBFMIN:
> + return "zfbfmin";
> case INSN_CLASS_ZFA:
> return "zfa";
> case INSN_CLASS_D_AND_ZFA:
> diff --git a/gas/NEWS b/gas/NEWS
> index e51c3bbba6d..b88c54fc5c3 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
> -*- text -*-
>
> +* Add support for RISC-V Zfbfmin extension with version 1.0.
> +
>
Added after "Add support for RISC-V Zcmp extension with version 1.0."
> * In x86 Intel syntax undue mnemonic suffixes are now warned about. This
> is
> a first step towards rejecting their use where unjustified.
>
> diff --git a/gas/testsuite/gas/riscv/march-help.l
> b/gas/testsuite/gas/riscv/march-help.l
> index c5754837e05..9deaa841622 100644
> --- a/gas/testsuite/gas/riscv/march-help.l
> +++ b/gas/testsuite/gas/riscv/march-help.l
> @@ -26,6 +26,7 @@ All available -march extensions for RISC-V:
> zalrsc 1.0
> zawrs 1.0
> zfa 1.0
> + zfbfmin 1.0
> zfh 1.0
> zfhmin 1.0
> zfinx 1.0
> diff --git a/gas/testsuite/gas/riscv/zfbfmin.d
> b/gas/testsuite/gas/riscv/zfbfmin.d
> new file mode 100644
> index 00000000000..7cacc0bd684
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfbfmin.d
> @@ -0,0 +1,11 @@
> +#as: -march=rv64i_zfbfmin
> +#objdump: -d
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt.bf16.s[ ]+fa0,fa1
> +[ ]+[0-9a-f]+:[ ]+44858553[ ]+fcvt.bf16.s[ ]+fa0,fa1,rne
> +[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt.s.bf16[ ]+fa0,fa1
> diff --git a/gas/testsuite/gas/riscv/zfbfmin.s
> b/gas/testsuite/gas/riscv/zfbfmin.s
> new file mode 100644
> index 00000000000..c9a9af3e394
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfbfmin.s
> @@ -0,0 +1,6 @@
> +target:
> + # fcvt.bf16.s
> + fcvt.bf16.s fa0, fa1
> + fcvt.bf16.s fa0, fa1, rne
> + # fcvt.s.bf16
> + fcvt.s.bf16 fa0, fa1
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index ae14e14d427..26d60bc585e 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2365,6 +2365,11 @@
> #define MASK_WRS_NTO 0xffffffff
> #define MATCH_WRS_STO 0x01d00073
> #define MASK_WRS_STO 0xffffffff
> +/* Zfbfmin intructions. */
> +#define MATCH_FCVT_BF16_S 0x44800053
> +#define MASK_FCVT_BF16_S 0xfff0007f
> +#define MATCH_FCVT_S_BF16 0x40600053
> +#define MASK_FCVT_S_BF16 0xfff0007f
> /* Vendor-specific (CORE-V) Xcvmac instructions. */
> #define MATCH_CV_MAC 0x9000302b
> #define MASK_CV_MAC 0xfe00707f
> @@ -3912,6 +3917,9 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL,
> MASK_C_NTL_ALL)
> /* Zawrs instructions. */
> DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
> DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
> +/* Zfbfmin instructions. */
> +DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
> +DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
> /* Zvbb/Zvkb instructions. */
> DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
> DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 5f516a1026e..0e58dbe3d03 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -447,6 +447,7 @@ enum riscv_insn_class
> INSN_CLASS_ZFHMIN_AND_D_INX,
> INSN_CLASS_ZFHMIN_AND_Q_INX,
> INSN_CLASS_ZFA,
> + INSN_CLASS_ZFBFMIN,
>
Likewise, before ZFA
> INSN_CLASS_D_AND_ZFA,
> INSN_CLASS_Q_AND_ZFA,
> INSN_CLASS_ZFH_AND_ZFA,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 1ef4eaddf4d..9f99aa6c792 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1132,6 +1132,11 @@ const struct riscv_opcode riscv_opcodes[] =
> {"fltq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLTQ_H,
> MASK_FLTQ_H, match_opcode, 0 },
> {"fleq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLEQ_H,
> MASK_FLEQ_H, match_opcode, 0 },
>
> +/* Zfbfmin instructions. */
> +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S",
> MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
> +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S,
> MASK_FCVT_BF16_S, match_opcode, 0 },
> +{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16,
> MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
>
1. MATCH_FCVT_S_BF16|MASK_RM, MASK_FCVT_S_BF16, looks like you put it
backwards?
2. The fcvt.s.bf16 with "D,S,m"?
3. Moved between half-precision floating-point instruction subset and
single-precision
floating-point instruction subset?
+
> /* Zbb or zbkb instructions. */
> {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ,
> match_opcode, 0 },
> {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ,
> match_opcode, 0 },
> --
> 2.17.1
>
>
2024-06-06 10:26 Nelson Chu <nelson@rivosinc.com> wrote:
>
>On Wed, Jun 5, 2024 at 9:30 AM Xiao Zeng <zengxiao@eswincomputing.com>
>wrote:
>
>> This implements the Zfbfmin extension, as of version 1.0.
>>
>> View detailed information in:
>> <
>> https://github.com/riscv/riscv-isa-manual/blob/main/src/bfloat16.adoc#zfbfmin---scalar-bf16-converts
>> >
>>
>> 1 The Zfbfmin extension depend on 'F', and the FLH, FSH, FMV.X.H, and
>> FMV.H.X instructions as defined in the Zfh extension.
>>
>> 2 The Zfhmin extension includes the following instructions from the Zfh
>> extension: FLH, FSH, FMV.X.H, FMV.H.X... View detailed information in:
>> <https://github.com/riscv/riscv-isa-manual/blob/main/src/zfh.adoc>
>>
>> 3 Zfhmin extension depend on 'F'.
>>
>> 4 Simply put, just make Zfbfmin dependent on Zfhmin.
>>
>> Perhaps in the future, we could propose making the FLH, FSH, FMV.X.H, and
>> FMV.H.X instructions an independent extension to achieve precise dependency
>> relationships for the Zfbfmin.
>>
>> 5 For relevant information in gcc, please refer to:
>> <
>> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=35224ead63732a3550ba4b1332c06e9dc7999c31
>> >
>>
>> bfd/ChangeLog:
>>
>> * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zfbfmin.
>> (riscv_multi_subset_supports_ext): Ditto.
>>
>> gas/ChangeLog:
>>
>> * NEWS: Updated.
>> * testsuite/gas/riscv/march-help.l: Ditto.
>> * testsuite/gas/riscv/zfbfmin.d: New test.
>> * testsuite/gas/riscv/zfbfmin.s: New test.
>>
>> include/ChangeLog:
>>
>> * opcode/riscv-opc.h (MATCH_FCVT_BF16_S): Define.
>> (MASK_FCVT_BF16_S): Ditto.
>> (MATCH_FCVT_S_BF16): Ditto.
>> (MASK_FCVT_S_BF16): Ditto.
>> (DECLARE_INSN): New declarations for Zfbfmin.
>> * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZFBFMIN.
>>
>> opcodes/ChangeLog:
>>
>> * riscv-opc.c: Add Zfbfmin instructions.
>> ---
>> bfd/elfxx-riscv.c | 6 ++++++
>> gas/NEWS | 2 ++
>> gas/testsuite/gas/riscv/march-help.l | 1 +
>> gas/testsuite/gas/riscv/zfbfmin.d | 11 +++++++++++
>> gas/testsuite/gas/riscv/zfbfmin.s | 6 ++++++
>> include/opcode/riscv-opc.h | 8 ++++++++
>> include/opcode/riscv.h | 1 +
>> opcodes/riscv-opc.c | 5 +++++
>> 8 files changed, 40 insertions(+)
>> create mode 100644 gas/testsuite/gas/riscv/zfbfmin.d
>> create mode 100644 gas/testsuite/gas/riscv/zfbfmin.s
>>
>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index dfacb87eda0..d9709a232e6 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1224,6 +1224,7 @@ static struct riscv_implicit_subset
>> riscv_implicit_subsets[] =
>> {"zcf", "f", check_implicit_always},
>> {"zfa", "f", check_implicit_always},
>> {"d", "f", check_implicit_always},
>> + {"zfbfmin", "zfhmin", check_implicit_always},
>> {"zfh", "zfhmin", check_implicit_always},
>> {"zfhmin", "f", check_implicit_always},
>> {"f", "zicsr", check_implicit_always},
>> @@ -1360,6 +1361,7 @@ static struct riscv_supported_ext
>> riscv_supported_std_z_ext[] =
>> {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
>> @@ -2561,6 +2563,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
>> *rps,
>> case INSN_CLASS_Q_INX:
>> return (riscv_subset_supports (rps, "q")
>> || riscv_subset_supports (rps, "zqinx"));
>> + case INSN_CLASS_ZFBFMIN:
>> + return riscv_subset_supports (rps, "zfbfmin");
>>
>
>Placed before INSN_CLASS_ZFA like the following change?
Fixed.
>
>
>> case INSN_CLASS_ZFH_INX:
>> return (riscv_subset_supports (rps, "zfh")
>> || riscv_subset_supports (rps, "zhinx"));
>> @@ -2827,6 +2831,8 @@ riscv_multi_subset_supports_ext
>> (riscv_parse_subset_t *rps,
>> return "zhinxmin";
>> else
>> return _("zfhmin' and `q', or `zhinxmin' and `zqinx");
>> + case INSN_CLASS_ZFBFMIN:
>> + return "zfbfmin";
>> case INSN_CLASS_ZFA:
>> return "zfa";
>> case INSN_CLASS_D_AND_ZFA:
>> diff --git a/gas/NEWS b/gas/NEWS
>> index e51c3bbba6d..b88c54fc5c3 100644
>> --- a/gas/NEWS
>> +++ b/gas/NEWS
>> @@ -1,5 +1,7 @@
>> -*- text -*-
>>
>> +* Add support for RISC-V Zfbfmin extension with version 1.0.
>> +
>>
>
>Added after "Add support for RISC-V Zcmp extension with version 1.0."
Fixed.
>
>
>> * In x86 Intel syntax undue mnemonic suffixes are now warned about. This
>> is
>> a first step towards rejecting their use where unjustified.
>>
>> diff --git a/gas/testsuite/gas/riscv/march-help.l
>> b/gas/testsuite/gas/riscv/march-help.l
>> index c5754837e05..9deaa841622 100644
>> --- a/gas/testsuite/gas/riscv/march-help.l
>> +++ b/gas/testsuite/gas/riscv/march-help.l
>> @@ -26,6 +26,7 @@ All available -march extensions for RISC-V:
>> zalrsc 1.0
>> zawrs 1.0
>> zfa 1.0
>> + zfbfmin 1.0
>> zfh 1.0
>> zfhmin 1.0
>> zfinx 1.0
>> diff --git a/gas/testsuite/gas/riscv/zfbfmin.d
>> b/gas/testsuite/gas/riscv/zfbfmin.d
>> new file mode 100644
>> index 00000000000..7cacc0bd684
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zfbfmin.d
>> @@ -0,0 +1,11 @@
>> +#as: -march=rv64i_zfbfmin
>> +#objdump: -d
>> +
>> +.*:[ ]+file format .*
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt.bf16.s[ ]+fa0,fa1
>> +[ ]+[0-9a-f]+:[ ]+44858553[ ]+fcvt.bf16.s[ ]+fa0,fa1,rne
>> +[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt.s.bf16[ ]+fa0,fa1
>> diff --git a/gas/testsuite/gas/riscv/zfbfmin.s
>> b/gas/testsuite/gas/riscv/zfbfmin.s
>> new file mode 100644
>> index 00000000000..c9a9af3e394
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zfbfmin.s
>> @@ -0,0 +1,6 @@
>> +target:
>> + # fcvt.bf16.s
>> + fcvt.bf16.s fa0, fa1
>> + fcvt.bf16.s fa0, fa1, rne
>> + # fcvt.s.bf16
>> + fcvt.s.bf16 fa0, fa1
>> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
>> index ae14e14d427..26d60bc585e 100644
>> --- a/include/opcode/riscv-opc.h
>> +++ b/include/opcode/riscv-opc.h
>> @@ -2365,6 +2365,11 @@
>> #define MASK_WRS_NTO 0xffffffff
>> #define MATCH_WRS_STO 0x01d00073
>> #define MASK_WRS_STO 0xffffffff
>> +/* Zfbfmin intructions. */
>> +#define MATCH_FCVT_BF16_S 0x44800053
>> +#define MASK_FCVT_BF16_S 0xfff0007f
>> +#define MATCH_FCVT_S_BF16 0x40600053
>> +#define MASK_FCVT_S_BF16 0xfff0007f
>> /* Vendor-specific (CORE-V) Xcvmac instructions. */
>> #define MATCH_CV_MAC 0x9000302b
>> #define MASK_CV_MAC 0xfe00707f
>> @@ -3912,6 +3917,9 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL,
>> MASK_C_NTL_ALL)
>> /* Zawrs instructions. */
>> DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
>> DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
>> +/* Zfbfmin instructions. */
>> +DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
>> +DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
>> /* Zvbb/Zvkb instructions. */
>> DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
>> DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
>> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
>> index 5f516a1026e..0e58dbe3d03 100644
>> --- a/include/opcode/riscv.h
>> +++ b/include/opcode/riscv.h
>> @@ -447,6 +447,7 @@ enum riscv_insn_class
>> INSN_CLASS_ZFHMIN_AND_D_INX,
>> INSN_CLASS_ZFHMIN_AND_Q_INX,
>> INSN_CLASS_ZFA,
>> + INSN_CLASS_ZFBFMIN,
>>
>
>Likewise, before ZFA
Fixed.
>
>
>> INSN_CLASS_D_AND_ZFA,
>> INSN_CLASS_Q_AND_ZFA,
>> INSN_CLASS_ZFH_AND_ZFA,
>> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
>> index 1ef4eaddf4d..9f99aa6c792 100644
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -1132,6 +1132,11 @@ const struct riscv_opcode riscv_opcodes[] =
>> {"fltq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLTQ_H,
>> MASK_FLTQ_H, match_opcode, 0 },
>> {"fleq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLEQ_H,
>> MASK_FLEQ_H, match_opcode, 0 },
>>
>> +/* Zfbfmin instructions. */
>> +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S",
>> MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
>> +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S,
>> MASK_FCVT_BF16_S, match_opcode, 0 },
>> +{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16,
>> MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
>>
>
>1. MATCH_FCVT_S_BF16|MASK_RM, MASK_FCVT_S_BF16, looks like you put it
>backwards?
Do you seem to have read it backwards? Of course, it could also be my problem.
If there is any further information, please feel free to ping me at any time.
fcvt.bf16.s(single-precision -> bf16 ) is similar to fcvt.h.s(single-precision -> hf16 ):
-------------------------------------------------------------------------------------------------------------------------------------------
{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 },
-------------------------------------------------------------------------------------------------------------------------------------------
>2. The fcvt.s.bf16 with "D,S,m"?
fcvt.s.bf16(bf16 -> single-precision) is similar to fcvt.s.h(hf16 -> single-precision):
-------------------------------------------------------------------------------------------------------------------------------------------
{"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
-------------------------------------------------------------------------------------------------------------------------------------------
>3. Moved between half-precision floating-point instruction subset and
>single-precision
>floating-point instruction subset?
Fixed.
>
>+
>> /* Zbb or zbkb instructions. */
>> {"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ,
>> match_opcode, 0 },
>> {"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ,
>> match_opcode, 0 },
>> --
>> 2.17.1
>>
>>
Thanks
Xiao Zeng
On Thu, Jun 6, 2024 at 2:12 PM Xiao Zeng <zengxiao@eswincomputing.com>
wrote:
> 2024-06-06 10:26 Nelson Chu <nelson@rivosinc.com> wrote:
> >1. MATCH_FCVT_S_BF16|MASK_RM, MASK_FCVT_S_BF16, looks like you put it
> >backwards?
> Do you seem to have read it backwards? Of course, it could also be my
> problem.
> If there is any further information, please feel free to ping me at any
> time.
>
> fcvt.bf16.s(single-precision -> bf16 ) is similar to
> fcvt.h.s(single-precision -> hf16 ):
>
> -------------------------------------------------------------------------------------------------------------------------------------------
> {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S",
> MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
> {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S,m", MATCH_FCVT_H_S,
> MASK_FCVT_H_S, match_opcode, 0 },
>
> {"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM,
> MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
> {"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S,
> MASK_FCVT_BF16_S, match_opcode, 0 },
>
> -------------------------------------------------------------------------------------------------------------------------------------------
>
I am saying the fcvt.s.bf16, not fcvt.bf16.s. I thought it should be
{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S",
MATCH_FCVT_S_BF16|MASK_RM, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
Since the spec still reserve rm operand,
https://github.com/riscv/riscv-bfloat16/blob/main/doc/insns/fcvt_S_BF16.adoc
But in fact you are right, I just remember that half to single/double
precision, single to double precision don't need to care about the rounding
mode, so your patch is right, I am confused and forgot this at first.
> >2. The fcvt.s.bf16 with "D,S,m"?
> fcvt.s.bf16(bf16 -> single-precision) is similar to fcvt.s.h(hf16 ->
> single-precision):
>
> -------------------------------------------------------------------------------------------------------------------------------------------
> {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H,
> MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
> {"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16,
> MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
>
> -------------------------------------------------------------------------------------------------------------------------------------------
>
Forgot what I left in the previous comment, you are right.
Please send the fixed three patches again if you have time, so I can commit
them.
Thanks
Nelson
@@ -1224,6 +1224,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zcf", "f", check_implicit_always},
{"zfa", "f", check_implicit_always},
{"d", "f", check_implicit_always},
+ {"zfbfmin", "zfhmin", check_implicit_always},
{"zfh", "zfhmin", check_implicit_always},
{"zfhmin", "f", check_implicit_always},
{"f", "zicsr", check_implicit_always},
@@ -1360,6 +1361,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2561,6 +2563,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_Q_INX:
return (riscv_subset_supports (rps, "q")
|| riscv_subset_supports (rps, "zqinx"));
+ case INSN_CLASS_ZFBFMIN:
+ return riscv_subset_supports (rps, "zfbfmin");
case INSN_CLASS_ZFH_INX:
return (riscv_subset_supports (rps, "zfh")
|| riscv_subset_supports (rps, "zhinx"));
@@ -2827,6 +2831,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "zhinxmin";
else
return _("zfhmin' and `q', or `zhinxmin' and `zqinx");
+ case INSN_CLASS_ZFBFMIN:
+ return "zfbfmin";
case INSN_CLASS_ZFA:
return "zfa";
case INSN_CLASS_D_AND_ZFA:
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for RISC-V Zfbfmin extension with version 1.0.
+
* In x86 Intel syntax undue mnemonic suffixes are now warned about. This is
a first step towards rejecting their use where unjustified.
@@ -26,6 +26,7 @@ All available -march extensions for RISC-V:
zalrsc 1.0
zawrs 1.0
zfa 1.0
+ zfbfmin 1.0
zfh 1.0
zfhmin 1.0
zfinx 1.0
new file mode 100644
@@ -0,0 +1,11 @@
+#as: -march=rv64i_zfbfmin
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+4485f553[ ]+fcvt.bf16.s[ ]+fa0,fa1
+[ ]+[0-9a-f]+:[ ]+44858553[ ]+fcvt.bf16.s[ ]+fa0,fa1,rne
+[ ]+[0-9a-f]+:[ ]+40658553[ ]+fcvt.s.bf16[ ]+fa0,fa1
new file mode 100644
@@ -0,0 +1,6 @@
+target:
+ # fcvt.bf16.s
+ fcvt.bf16.s fa0, fa1
+ fcvt.bf16.s fa0, fa1, rne
+ # fcvt.s.bf16
+ fcvt.s.bf16 fa0, fa1
@@ -2365,6 +2365,11 @@
#define MASK_WRS_NTO 0xffffffff
#define MATCH_WRS_STO 0x01d00073
#define MASK_WRS_STO 0xffffffff
+/* Zfbfmin intructions. */
+#define MATCH_FCVT_BF16_S 0x44800053
+#define MASK_FCVT_BF16_S 0xfff0007f
+#define MATCH_FCVT_S_BF16 0x40600053
+#define MASK_FCVT_S_BF16 0xfff0007f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -3912,6 +3917,9 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL)
/* Zawrs instructions. */
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
+/* Zfbfmin instructions. */
+DECLARE_INSN(FCVT_BF16_S, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
+DECLARE_INSN(FCVT_S_BF16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
/* Zvbb/Zvkb instructions. */
DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
@@ -447,6 +447,7 @@ enum riscv_insn_class
INSN_CLASS_ZFHMIN_AND_D_INX,
INSN_CLASS_ZFHMIN_AND_Q_INX,
INSN_CLASS_ZFA,
+ INSN_CLASS_ZFBFMIN,
INSN_CLASS_D_AND_ZFA,
INSN_CLASS_Q_AND_ZFA,
INSN_CLASS_ZFH_AND_ZFA,
@@ -1132,6 +1132,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"fltq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLTQ_H, MASK_FLTQ_H, match_opcode, 0 },
{"fleq.h", 0, INSN_CLASS_ZFH_AND_ZFA, "d,S,T", MATCH_FLEQ_H, MASK_FLEQ_H, match_opcode, 0 },
+/* Zfbfmin instructions. */
+{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
+{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 },
+{"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
+
/* Zbb or zbkb instructions. */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },