diff mbox series

[v1,4-R/7] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands (regenerated files).

Message ID 20240522100439.1050296-8-srinath.parvathaneni@arm.com
State Superseded
Headers
Series [v1,4-R/7] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands (regenerated files). |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 fail Patch failed to apply

Commit Message

srinath May 22, 2024, 10:04 a.m. UTC 
  Hi,

This patch includes the regenerated files for
[PATCH v2 4/7][Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.

Regards,
Srinath.
---
 opcodes/aarch64-asm-2.c | 11 ++++-------
 opcodes/aarch64-dis-2.c |  6 +-----
 opcodes/aarch64-opc-2.c |  3 ---
 3 files changed, 5 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 8a4ac3e81c3..6c56ced0a02 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -930,9 +930,6 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 232:
     case 234:
     case 251:
-    case 297:
-    case 298:
-    case 299:
       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
     case 235:
     case 236:
@@ -988,12 +985,12 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 293:
     case 294:
       return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
+    case 297:
+    case 298:
+    case 299:
     case 300:
-    case 301:
-    case 302:
-    case 303:
       return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
-    case 304:
+    case 301:
       return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index b82f3731d98..6dc36d5beba 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -33894,13 +33894,9 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 297:
     case 298:
     case 299:
-      return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
     case 300:
-    case 301:
-    case 302:
-    case 303:
       return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
-    case 304:
+    case 301:
       return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
     default: assert (0); abort ();
     }
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 97b7fb9a8ea..11fbaf43f79 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -321,9 +321,6 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 2 SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 3 SVE vector registers"},
-  {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zt4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of 4 SVE vector registers"},
   {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with post-incrementing by ammount of loaded bytes"},
   {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with pre-incrementing with write-back by ammount of stored bytes"},
   {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with post-incrementing by ammount of loaded bytes"},