diff mbox series

[v1,7-R/7] aarch64: Fix FEAT_B16B16 sve2 instruction constraints (regenerated files).

Message ID 20240522100439.1050296-12-srinath.parvathaneni@arm.com
State Superseded
Headers
Series [v1,7-R/7] aarch64: Fix FEAT_B16B16 sve2 instruction constraints (regenerated files). |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 fail Testing failed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

srinath May 22, 2024, 10:04 a.m. UTC 
  Hi,

This patch includes the regenerated files for
[PATCH v1 7/7][Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints.

Regards,
Srinath.
---
 opcodes/aarch64-dis-2.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 6dc36d5beba..7df0920bbd6 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -17126,7 +17126,7 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                                              10987654321098765432109876543210
                                                              011001x00x1xxxxx000x10xxxxxxxxxx
                                                              bfmla.  */
-                                                          return 3294;
+                                                          return 3291;
                                                         }
                                                     }
                                                   else
@@ -17145,7 +17145,7 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                                              10987654321098765432109876543210
                                                              011001x00x1xxxxx000x11xxxxxxxxxx
                                                              bfmls.  */
-                                                          return 3295;
+                                                          return 3292;
                                                         }
                                                     }
                                                 }
@@ -32891,16 +32891,16 @@  aarch64_find_next_opcode (const aarch64_opcode *opcode)
     case 1696: return NULL;		/* ldff1b --> NULL.  */
     case 1714: value = 1715; break;	/* ldff1h --> ldff1h.  */
     case 1715: return NULL;		/* ldff1h --> NULL.  */
-    case 2474: value = 3291; break;	/* fclamp --> bfclamp.  */
-    case 3291: return NULL;		/* bfclamp --> NULL.  */
+    case 2474: value = 3290; break;	/* fclamp --> bfclamp.  */
+    case 3290: return NULL;		/* bfclamp --> NULL.  */
     case 1788: value = 1789; break;	/* ldr --> ldr.  */
     case 1789: return NULL;		/* ldr --> NULL.  */
-    case 1444: value = 3290; break;	/* fadd --> bfadd.  */
-    case 3290: return NULL;		/* bfadd --> NULL.  */
-    case 1511: value = 3292; break;	/* fmul --> bfmul.  */
-    case 3292: return NULL;		/* bfmul --> NULL.  */
-    case 1537: value = 3293; break;	/* fsub --> bfsub.  */
-    case 3293: return NULL;		/* bfsub --> NULL.  */
+    case 1444: value = 3293; break;	/* fadd --> bfadd.  */
+    case 3293: return NULL;		/* bfadd --> NULL.  */
+    case 1511: value = 3294; break;	/* fmul --> bfmul.  */
+    case 3294: return NULL;		/* bfmul --> NULL.  */
+    case 1537: value = 3295; break;	/* fsub --> bfsub.  */
+    case 3295: return NULL;		/* bfsub --> NULL.  */
     case 1502: value = 3286; break;	/* fmla --> bfmla.  */
     case 3286: return NULL;		/* bfmla --> NULL.  */
     case 2007: value = 2008; break;	/* str --> str.  */