diff mbox series

[V5,14/16] opcodes: i386-reg.tbl: Add a comment to reflect dependency on ordering

Message ID 20240111074820.2677826-15-indu.bhagat@oracle.com
State New
Headers
Series Experimental support for synthesizing CFI for hand-written asm |

Commit Message

Indu Bhagat Jan. 11, 2024, 7:48 a.m. UTC 
  [New in V3. No changes since V3]

The ginsn representation keeps the DWARF register number of the
operands.  The API ginsn_dw2_regnum relies on the the relative ordering
of these register entries in the table.  Add a comment to make it clear.

opcodes/
	* i386-reg.tbl: Add a comment.
---
 opcodes/i386-reg.tbl | 3 +++
 1 file changed, 3 insertions(+)

Comments

Jan Beulich Jan. 11, 2024, 7:59 a.m. UTC | #1 
On 11.01.2024 08:48, Indu Bhagat wrote:
> [New in V3. No changes since V3]
> 
> The ginsn representation keeps the DWARF register number of the
> operands.  The API ginsn_dw2_regnum relies on the the relative ordering
> of these register entries in the table.  Add a comment to make it clear.
> 
> opcodes/
> 	* i386-reg.tbl: Add a comment.

Okay (not sure if I said so on an earlier version already). This is fine
to go in at any time.

Jan
diff mbox series

Patch

diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index 5b80ee6026e..f92315392b8 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -18,6 +18,9 @@ 
 // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
 // 02110-1301, USA.
 
+// The code in gas backend for SCFI relies on the relative ordering
+// of 8 bit / 16 bit / 32 bit / 64 bit regs
+
 // 8 bit regs
 al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
 cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval