diff mbox series

[09/12] aarch64: Add xs variants of tlbip operands

Message ID 20240103011739.2444792-10-victor.donascimento@arm.com
State Committed
Headers
Series aarch64: Add Armv9.4-A support for the d128 extension |

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Context Check Description
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_binutils_check--master-aarch64 fail Testing failed
linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed

Commit Message

Victor Do Nascimento Jan. 3, 2024, 1:17 a.m. UTC 
  The 2020 Architecture Extensions to the Arm A-profile architecture
added FEAT_XS, the XS attribute feature, giving cores the ability to
identify devices which can be subject to long response delays. TLB
invalidate (TLBI) operations and barriers can also be annotated with
this attribute[1].

With the introduction of the 128-bit translation tables with the
Armv8.9-a/Armv9.4-a Translation Hardening Extension, a series of new
TLB invalidate operations are introduced which make use of this
extension.  These are added to aarch64_sys_regs_tlbi[] for use
with the `tlbip' insn.

[1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2020
---
 opcodes/aarch64-opc.c | 124 ++++++++++++++++++++++++++++++++++++++++++
 opcodes/aarch64-opc.h |   1 +
 2 files changed, 125 insertions(+)
diff mbox series

Patch

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 38a377110de..4380c294ff8 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4919,6 +4919,67 @@  const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
     { "paallos",    CPENS (6, C8, C1, 4), 0},
     { "paall",      CPENS (6, C8, C7, 4), 0},
 
+    { "vae1osnxs",      CPENS (0, C9, C1, 1), F_HASXT | F_ARCHEXT },
+    { "vaae1osnxs",     CPENS (0, C9, C1, 3), F_HASXT | F_ARCHEXT },
+    { "vale1osnxs",     CPENS (0, C9, C1, 5), F_HASXT | F_ARCHEXT },
+    { "vaale1osnxs",    CPENS (0, C9, C1, 7), F_HASXT | F_ARCHEXT },
+    { "rvae1isnxs",     CPENS (0, C9, C2, 1), F_HASXT | F_ARCHEXT },
+    { "rvaae1isnxs",    CPENS (0, C9, C2, 3), F_HASXT | F_ARCHEXT },
+    { "rvale1isnxs",    CPENS (0, C9, C2, 5), F_HASXT | F_ARCHEXT },
+    { "rvaale1isnxs",   CPENS (0, C9, C2, 7), F_HASXT | F_ARCHEXT },
+    { "vae1isnxs",      CPENS (0, C9, C3, 1), F_HASXT },
+    { "vaae1isnxs",     CPENS (0, C9, C3, 3), F_HASXT },
+    { "vale1isnxs",     CPENS (0, C9, C3, 5), F_HASXT },
+    { "vaale1isnxs",    CPENS (0, C9, C3, 7), F_HASXT },
+    { "rvae1osnxs",     CPENS (0, C9, C5, 1), F_HASXT | F_ARCHEXT },
+    { "rvaae1osnxs",    CPENS (0, C9, C5, 3), F_HASXT | F_ARCHEXT },
+    { "rvale1osnxs",    CPENS (0, C9, C5, 5), F_HASXT | F_ARCHEXT },
+    { "rvaale1osnxs",   CPENS (0, C9, C5, 7), F_HASXT | F_ARCHEXT },
+    { "rvae1nxs",       CPENS (0, C9, C6, 1), F_HASXT | F_ARCHEXT },
+    { "rvaae1nxs",      CPENS (0, C9, C6, 3), F_HASXT | F_ARCHEXT },
+    { "rvale1nxs",      CPENS (0, C9, C6, 5), F_HASXT | F_ARCHEXT },
+    { "rvaale1nxs",     CPENS (0, C9, C6, 7), F_HASXT | F_ARCHEXT },
+    { "vae1nxs",        CPENS (0, C9, C7, 1), F_HASXT },
+    { "vaae1nxs",       CPENS (0, C9, C7, 3), F_HASXT },
+    { "vale1nxs",       CPENS (0, C9, C7, 5), F_HASXT },
+    { "vaale1nxs",      CPENS (0, C9, C7, 7), F_HASXT },
+    { "ipas2e1isnxs",   CPENS (4, C9, C0, 1), F_HASXT },
+    { "ripas2e1isnxs",  CPENS (4, C9, C0, 2), F_HASXT | F_ARCHEXT },
+    { "ipas2le1isnxs",  CPENS (4, C9, C0, 5), F_HASXT },
+    { "ripas2le1isnxs", CPENS (4, C9, C0, 6), F_HASXT | F_ARCHEXT },
+    { "vae2osnxs",      CPENS (4, C9, C1, 1), F_HASXT | F_ARCHEXT },
+    { "vale2osnxs",     CPENS (4, C9, C1, 5), F_HASXT | F_ARCHEXT },
+    { "rvae2isnxs",     CPENS (4, C9, C2, 1), F_HASXT | F_ARCHEXT },
+    { "rvale2isnxs",    CPENS (4, C9, C2, 5), F_HASXT | F_ARCHEXT },
+    { "vae2isnxs",      CPENS (4, C9, C3, 1), F_HASXT },
+    { "vale2isnxs",     CPENS (4, C9, C3, 5), F_HASXT },
+    { "ipas2e1osnxs",   CPENS (4, C9, C4, 0), F_HASXT | F_ARCHEXT },
+    { "ipas2e1nxs",     CPENS (4, C9, C4, 1), F_HASXT },
+    { "ripas2e1nxs",    CPENS (4, C9, C4, 2), F_HASXT | F_ARCHEXT },
+    { "ripas2e1osnxs",  CPENS (4, C9, C4, 3), F_HASXT | F_ARCHEXT },
+    { "ipas2le1osnxs",  CPENS (4, C9, C4, 4), F_HASXT | F_ARCHEXT },
+    { "ipas2le1nxs",    CPENS (4, C9, C4, 5), F_HASXT },
+    { "ripas2le1nxs",   CPENS (4, C9, C4, 6), F_HASXT | F_ARCHEXT },
+    { "ripas2le1osnxs", CPENS (4, C9, C4, 7), F_HASXT | F_ARCHEXT },
+    { "rvae2osnxs",     CPENS (4, C9, C5, 1), F_HASXT | F_ARCHEXT },
+    { "rvale2osnxs",    CPENS (4, C9, C5, 5), F_HASXT | F_ARCHEXT },
+    { "rvae2nxs",       CPENS (4, C9, C6, 1), F_HASXT | F_ARCHEXT },
+    { "rvale2nxs",      CPENS (4, C9, C6, 5), F_HASXT | F_ARCHEXT },
+    { "vae2nxs",        CPENS (4, C9, C7, 1), F_HASXT },
+    { "vale2nxs",       CPENS (4, C9, C7, 5), F_HASXT },
+    { "vae3osnxs",      CPENS (6, C9, C1, 1), F_HASXT | F_ARCHEXT },
+    { "vale3osnxs",     CPENS (6, C9, C1, 5), F_HASXT | F_ARCHEXT },
+    { "rvae3isnxs",     CPENS (6, C9, C2, 1), F_HASXT | F_ARCHEXT },
+    { "rvale3isnxs",    CPENS (6, C9, C2, 5), F_HASXT | F_ARCHEXT },
+    { "vae3isnxs",      CPENS (6, C9, C3, 1), F_HASXT },
+    { "vale3isnxs",     CPENS (6, C9, C3, 5), F_HASXT },
+    { "rvae3osnxs",     CPENS (6, C9, C5, 1), F_HASXT | F_ARCHEXT },
+    { "rvale3osnxs",    CPENS (6, C9, C5, 5), F_HASXT | F_ARCHEXT },
+    { "rvae3nxs",       CPENS (6, C9, C6, 1), F_HASXT | F_ARCHEXT },
+    { "rvale3nxs",      CPENS (6, C9, C6, 5), F_HASXT | F_ARCHEXT },
+    { "vae3nxs",        CPENS (6, C9, C7, 1), F_HASXT },
+    { "vale3nxs",       CPENS (6, C9, C7, 5), F_HASXT },
+
     { 0,       CPENS(0,0,0,0), 0 }
 };
 
@@ -5043,6 +5104,69 @@  aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
       && AARCH64_CPU_HAS_FEATURE (features, MEMTAG))
     return true;
 
+  if ((reg_value == CPENS (0, C9, C1, 1)
+       || reg_value == CPENS (0, C9, C1, 3)
+       || reg_value == CPENS (0, C9, C1, 5)
+       || reg_value == CPENS (0, C9, C1, 7)
+       || reg_value == CPENS (0, C9, C2, 1)
+       || reg_value == CPENS (0, C9, C2, 3)
+       || reg_value == CPENS (0, C9, C2, 5)
+       || reg_value == CPENS (0, C9, C2, 7)
+       || reg_value == CPENS (0, C9, C3, 1)
+       || reg_value == CPENS (0, C9, C3, 3)
+       || reg_value == CPENS (0, C9, C3, 5)
+       || reg_value == CPENS (0, C9, C3, 7)
+       || reg_value == CPENS (0, C9, C5, 1)
+       || reg_value == CPENS (0, C9, C5, 3)
+       || reg_value == CPENS (0, C9, C5, 5)
+       || reg_value == CPENS (0, C9, C5, 7)
+       || reg_value == CPENS (0, C9, C6, 1)
+       || reg_value == CPENS (0, C9, C6, 3)
+       || reg_value == CPENS (0, C9, C6, 5)
+       || reg_value == CPENS (0, C9, C6, 7)
+       || reg_value == CPENS (0, C9, C7, 1)
+       || reg_value == CPENS (0, C9, C7, 3)
+       || reg_value == CPENS (0, C9, C7, 5)
+       || reg_value == CPENS (0, C9, C7, 7)
+       || reg_value == CPENS (4, C9, C0, 1)
+       || reg_value == CPENS (4, C9, C0, 2)
+       || reg_value == CPENS (4, C9, C0, 5)
+       || reg_value == CPENS (4, C9, C0, 6)
+       || reg_value == CPENS (4, C9, C1, 1)
+       || reg_value == CPENS (4, C9, C1, 5)
+       || reg_value == CPENS (4, C9, C2, 1)
+       || reg_value == CPENS (4, C9, C2, 5)
+       || reg_value == CPENS (4, C9, C3, 1)
+       || reg_value == CPENS (4, C9, C3, 5)
+       || reg_value == CPENS (4, C9, C4, 0)
+       || reg_value == CPENS (4, C9, C4, 1)
+       || reg_value == CPENS (4, C9, C4, 2)
+       || reg_value == CPENS (4, C9, C4, 3)
+       || reg_value == CPENS (4, C9, C4, 4)
+       || reg_value == CPENS (4, C9, C4, 5)
+       || reg_value == CPENS (4, C9, C4, 6)
+       || reg_value == CPENS (4, C9, C4, 7)
+       || reg_value == CPENS (4, C9, C5, 1)
+       || reg_value == CPENS (4, C9, C5, 5)
+       || reg_value == CPENS (4, C9, C6, 1)
+       || reg_value == CPENS (4, C9, C6, 5)
+       || reg_value == CPENS (4, C9, C7, 1)
+       || reg_value == CPENS (4, C9, C7, 5)
+       || reg_value == CPENS (6, C9, C1, 1)
+       || reg_value == CPENS (6, C9, C1, 5)
+       || reg_value == CPENS (6, C9, C2, 1)
+       || reg_value == CPENS (6, C9, C2, 5)
+       || reg_value == CPENS (6, C9, C3, 1)
+       || reg_value == CPENS (6, C9, C3, 5)
+       || reg_value == CPENS (6, C9, C5, 1)
+       || reg_value == CPENS (6, C9, C5, 5)
+       || reg_value == CPENS (6, C9, C6, 1)
+       || reg_value == CPENS (6, C9, C6, 5)
+       || reg_value == CPENS (6, C9, C7, 1)
+       || reg_value == CPENS (6, C9, C7, 5))
+      && AARCH64_CPU_HAS_FEATURE (features, D128))
+    return true;
+
   /* AT S1E1RP, AT S1E1WP.  Values are from aarch64_sys_regs_at.  */
   if ((reg_value == CPENS (0, C7, C9, 0)
        || reg_value == CPENS (0, C7, C9, 1))
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index cf217e86376..fde0a2e2c12 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -300,6 +300,7 @@  verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 #undef F_REG_128
 #define F_REG_128	(1 << 7) /* System regsister implementable as 128-bit wide.  */
 
+
 /* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
    Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
    In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below