@@ -3901,7 +3901,8 @@ is_apx_evex_encoding (void)
static INLINE bool
is_apx_rex2_encoding (void)
{
- return i.rex2 || i.rex2_encoding;
+ return i.rex2 || i.rex2_encoding
+ || i.tm.opcode_modifier.operandconstraint == REX2_REQUIRED;
}
static unsigned int
new file mode 100644
@@ -0,0 +1,14 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 APX_F pushp popp insns (Intel disassembly)
+#source: x86-64-apx-pushp-popp.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*d5 08 50[ ]+pushp rax
+\s*[a-f0-9]+:\s*d5 19 57[ ]+pushp r31
+\s*[a-f0-9]+:\s*d5 08 58[ ]+popp rax
+\s*[a-f0-9]+:\s*d5 19 5f[ ]+popp r31
new file mode 100644
@@ -0,0 +1,5 @@
+.* Assembler messages:
+.*:4: Error: operand size mismatch for `pushp'
+.*:5: Error: operand size mismatch for `popp'
+.*:6: Error: operand size mismatch for `pushp'
+.*:7: Error: operand size mismatch for `popp'
new file mode 100644
@@ -0,0 +1,7 @@
+# Check bytecode of APX_F pushp popp instructions with illegal instructions.
+
+ .text
+ pushp %eax
+ popp %eax
+ pushp (%rax)
+ popp (%rax)
new file mode 100644
@@ -0,0 +1,14 @@
+#as:
+#objdump: -dw
+#name: x86_64 APX_F pushp popp insns
+#source: x86-64-apx-pushp-popp.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*d5 08 50[ ]+pushp %rax
+\s*[a-f0-9]+:\s*d5 19 57[ ]+pushp %r31
+\s*[a-f0-9]+:\s*d5 08 58[ ]+popp %rax
+\s*[a-f0-9]+:\s*d5 19 5f[ ]+popp %r31
new file mode 100644
@@ -0,0 +1,8 @@
+# Check 64bit APX_F pushp popp instructions
+
+ .text
+ _start:
+ pushp %rax
+ pushp %r31
+ popp %rax
+ popp %r31
@@ -348,6 +348,9 @@ run_dump_test "x86-64-avx512dq-rcigrne"
run_dump_test "x86-64-apx-push2pop2"
run_dump_test "x86-64-apx-push2pop2-intel"
run_list_test "x86-64-apx-push2pop2-inval"
+run_dump_test "x86-64-apx-pushp-popp"
+run_dump_test "x86-64-apx-pushp-popp-intel"
+run_list_test "x86-64-apx-pushp-popp-inval"
run_dump_test "x86-64-avx512dq-rcigru-intel"
run_dump_test "x86-64-avx512dq-rcigru"
run_dump_test "x86-64-avx512dq-rcigrz-intel"
@@ -303,6 +303,9 @@ struct dis_private {
/* M0 in rex2 prefix represents map0 or map1. */
#define REX2_M 0x8
+/* {rex2} is not printed when the REX2_SPECIAL is set. */
+#define REX2_SPECIAL 16
+
/* Flags stored in PREFIXES. */
#define PREFIX_REPZ 1
#define PREFIX_REPNZ 2
@@ -1931,23 +1934,23 @@ static const struct dis386 dis386[] = {
{ "dec{S|}", { RMeSI }, 0 },
{ "dec{S|}", { RMeDI }, 0 },
/* 50 */
- { "push{!P|}", { RMrAX }, 0 },
- { "push{!P|}", { RMrCX }, 0 },
- { "push{!P|}", { RMrDX }, 0 },
- { "push{!P|}", { RMrBX }, 0 },
- { "push{!P|}", { RMrSP }, 0 },
- { "push{!P|}", { RMrBP }, 0 },
- { "push{!P|}", { RMrSI }, 0 },
- { "push{!P|}", { RMrDI }, 0 },
+ { "push!P", { RMrAX }, 0 },
+ { "push!P", { RMrCX }, 0 },
+ { "push!P", { RMrDX }, 0 },
+ { "push!P", { RMrBX }, 0 },
+ { "push!P", { RMrSP }, 0 },
+ { "push!P", { RMrBP }, 0 },
+ { "push!P", { RMrSI }, 0 },
+ { "push!P", { RMrDI }, 0 },
/* 58 */
- { "pop{!P|}", { RMrAX }, 0 },
- { "pop{!P|}", { RMrCX }, 0 },
- { "pop{!P|}", { RMrDX }, 0 },
- { "pop{!P|}", { RMrBX }, 0 },
- { "pop{!P|}", { RMrSP }, 0 },
- { "pop{!P|}", { RMrBP }, 0 },
- { "pop{!P|}", { RMrSI }, 0 },
- { "pop{!P|}", { RMrDI }, 0 },
+ { "pop!P", { RMrAX }, 0 },
+ { "pop!P", { RMrCX }, 0 },
+ { "pop!P", { RMrDX }, 0 },
+ { "pop!P", { RMrBX }, 0 },
+ { "pop!P", { RMrSP }, 0 },
+ { "pop!P", { RMrBP }, 0 },
+ { "pop!P", { RMrSI }, 0 },
+ { "pop!P", { RMrDI }, 0 },
/* 60 */
{ X86_64_TABLE (X86_64_60) },
{ X86_64_TABLE (X86_64_61) },
@@ -9790,9 +9793,10 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
/* Check if the REX2 prefix is used. */
if (ins.last_rex2_prefix >= 0
- && ((ins.rex2 & 0x7) ^ (ins.rex2_used & 0x7)) == 0
- && (ins.rex ^ ins.rex_used) == 0
- && (ins.rex2 & 0x7))
+ && ((ins.rex2 & REX2_SPECIAL)
+ || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
+ && (ins.rex ^ ins.rex_used) == 0
+ && (ins.rex2 & 7))))
ins.all_prefixes[ins.last_rex2_prefix] = 0;
/* Check if the SEG prefix is used. */
@@ -10639,6 +10643,19 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
case 'P':
if (l == 0)
{
+ if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
+ {
+ /* For pushp and popp, p is printed and do not print {rex2}
+ for them. */
+ *ins->obufp++ = 'p';
+ ins->rex2 |= REX2_SPECIAL;
+ break;
+ }
+
+ /* For "!P" print nothing else in Intel syntax. */
+ if (!cond && ins->intel_syntax)
+ break;
+
if ((ins->modrm.mod == 3 || !cond)
&& !(sizeflag & SUFFIX_ALWAYS))
break;
@@ -579,6 +579,8 @@ enum
/* Instrucion requires that destination must be distinct from source
registers. */
#define DISTINCT_DEST 9
+ /* Instrucion requires REX2 prefix. */
+#define REX2_REQUIRED 10
OperandConstraint,
/* instruction ignores operand size prefix and in Intel mode ignores
mnemonic size suffix check. */
@@ -85,6 +85,7 @@
#define RegKludge OperandConstraint=REG_KLUDGE
#define SwapSources OperandConstraint=SWAP_SOURCES
#define Ugh OperandConstraint=UGH
+#define Rex2 OperandConstraint=REX2_REQUIRED
#define ATTSyntax Dialect=ATT_SYNTAX
#define ATTMnemonic Dialect=ATT_MNEMONIC
@@ -232,6 +233,7 @@ push, 0x68, i186&No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 }
push, 0x6, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
// In 64bit mode, the operand size is implicitly 64bit.
push, 0x50, x64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
+pushp, 0x50, APX_F, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Rex2, { Reg64 }
push, 0xff/6, x64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Unspecified|BaseIndex }
push, 0x6a, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S }
push, 0x68, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S }
@@ -245,6 +247,7 @@ pop, 0x8f/0, No64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Unsp
pop, 0x7, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
// In 64bit mode, the operand size is implicitly 64bit.
pop, 0x58, x64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
+popp, 0x58, APX_F, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Rex2, { Reg64 }
pop, 0x8f/0, x64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Unspecified|BaseIndex }
pop, 0xfa1, x64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }