diff mbox series

[v1,3/5] LoongArch: opcodes: Add support for tls le relax.

Message ID 20231201090730.20521-4-changjiachen@stu.xupt.edu.cn
State New
Headers
Series LoongArch tls le model linker relaxation support. |

Commit Message

changjiachen Dec. 1, 2023, 9:07 a.m. UTC 
  Add new opcode for tls le relax.

	opcode/ChangeLog:

	* loongarch-opc.c: Add new loongarch opcode.
---
 opcodes/loongarch-opc.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Xi Ruoyao Dec. 1, 2023, 9:47 a.m. UTC | #1 
On Fri, 2023-12-01 at 17:07 +0800, changjiachen wrote:
> +  { 0x00108000, 0xffff8000,	"add.d",	"r0:5,r5:5,r10:5,s10:5",	0,			0,	0,	0 },

Let's not do this.  This allows wrongly written assembly code like
"add.d $r12,$r12,$r12,114" undetected.

If you just want a relocation you can always emit it with a .reloc
directive.
diff mbox series

Patch

diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index 82b88bdad2a..e9ced5383e5 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -399,6 +399,7 @@  static struct loongarch_opcode loongarch_fix_opcodes[] =
   { 0x000c0000, 0xfffc0000,	"bytepick.d",	"r0:5,r5:5,r10:5,u15:3",	0,			0,	0,	0 },
   { 0x00100000, 0xffff8000,	"add.w",	"r0:5,r5:5,r10:5",		0,			0,	0,	0 },
   { 0x00108000, 0xffff8000,	"add.d",	"r0:5,r5:5,r10:5",		0,			0,	0,	0 },
+  { 0x00108000, 0xffff8000,	"add.d",	"r0:5,r5:5,r10:5,s10:5",	0,			0,	0,	0 },
   { 0x00110000, 0xffff8000,	"sub.w",	"r0:5,r5:5,r10:5",		0,			0,	0,	0 },
   { 0x00118000, 0xffff8000,	"sub.d",	"r0:5,r5:5,r10:5",		0,			0,	0,	0 },
   { 0x00120000, 0xffff8000,	"slt",		"r0:5,r5:5,r10:5",		0,			0,	0,	0 },