diff mbox series

[12/12] RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension

Message ID 20231110073514.2142-1-jinma@linux.alibaba.com
State New
Headers
Series [01/12] RISC-V: Add T-Head VECTOR vendor extension. |

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Commit Message

Jin Ma Nov. 10, 2023, 7:35 a.m. UTC 
  T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds permutation instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	permutation instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMVXS): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
---
 gas/testsuite/gas/riscv/x-thead-vector.d | 30 +++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector.s | 38 ++++++++++++++++++++++++
 include/opcode/riscv-opc.h               | 30 +++++++++++++++++++
 opcodes/riscv-opc.c                      | 15 ++++++++++
 4 files changed, 113 insertions(+)
diff mbox series

Patch

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 8a43fe38b8b..885baf73490 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -778,3 +778,33 @@  Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+58812257[ 	]+th.vmsof.m[ 	]+v4,v8,v0.t
 [ 	]+[0-9a-f]+:[ 	]+58882257[ 	]+th.viota.m[ 	]+v4,v8,v0.t
 [ 	]+[0-9a-f]+:[ 	]+5808a257[ 	]+th.vid.v[ 	]+v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+32c02557[ 	]+th.vmv.x.s[ 	]+a0,v12
+[ 	]+[0-9a-f]+:[ 	]+32c62557[ 	]+th.vext.x.v[ 	]+a0,v12,a2
+[ 	]+[0-9a-f]+:[ 	]+36056257[ 	]+th.vmv.s.x[ 	]+v4,a0
+[ 	]+[0-9a-f]+:[ 	]+32801557[ 	]+th.vfmv.f.s[ 	]+fa0,v8
+[ 	]+[0-9a-f]+:[ 	]+3605d257[ 	]+th.vfmv.s.f[ 	]+v4,fa1
+[ 	]+[0-9a-f]+:[ 	]+3a85c257[ 	]+th.vslideup.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3a803257[ 	]+th.vslideup.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+3a8fb257[ 	]+th.vslideup.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+3e85c257[ 	]+th.vslidedown.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3e803257[ 	]+th.vslidedown.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+3e8fb257[ 	]+th.vslidedown.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+3885c257[ 	]+th.vslideup.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+38803257[ 	]+th.vslideup.vi[ 	]+v4,v8,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+388fb257[ 	]+th.vslideup.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c85c257[ 	]+th.vslidedown.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c803257[ 	]+th.vslidedown.vi[ 	]+v4,v8,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c8fb257[ 	]+th.vslidedown.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3a85e257[ 	]+th.vslide1up.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3e85e257[ 	]+th.vslide1down.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3885e257[ 	]+th.vslide1up.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c85e257[ 	]+th.vslide1down.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+32860257[ 	]+th.vrgather.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+3285c257[ 	]+th.vrgather.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+32803257[ 	]+th.vrgather.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+328fb257[ 	]+th.vrgather.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+30860257[ 	]+th.vrgather.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3085c257[ 	]+th.vrgather.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+th.vrgather.vi[ 	]+v4,v8,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+th.vrgather.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+th.vcompress.vm[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index f23de9f7154..d7171057388 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -818,3 +818,41 @@ 
 	th.vmsof.m v4, v8, v0.t
 	th.viota.m v4, v8, v0.t
 	th.vid.v v4, v0.t
+
+	# Alias
+	th.vmv.x.s a0, v12
+
+	th.vext.x.v a0, v12, a2
+	th.vmv.s.x v4, a0
+
+	th.vfmv.f.s fa0, v8
+	th.vfmv.s.f v4, fa1
+
+	th.vslideup.vx v4, v8, a1
+	th.vslideup.vi v4, v8, 0
+	th.vslideup.vi v4, v8, 31
+	th.vslidedown.vx v4, v8, a1
+	th.vslidedown.vi v4, v8, 0
+	th.vslidedown.vi v4, v8, 31
+	th.vslideup.vx v4, v8, a1, v0.t
+	th.vslideup.vi v4, v8, 0, v0.t
+	th.vslideup.vi v4, v8, 31, v0.t
+	th.vslidedown.vx v4, v8, a1, v0.t
+	th.vslidedown.vi v4, v8, 0, v0.t
+	th.vslidedown.vi v4, v8, 31, v0.t
+
+	th.vslide1up.vx v4, v8, a1
+	th.vslide1down.vx v4, v8, a1
+	th.vslide1up.vx v4, v8, a1, v0.t
+	th.vslide1down.vx v4, v8, a1, v0.t
+
+	th.vrgather.vv v4, v8, v12
+	th.vrgather.vx v4, v8, a1
+	th.vrgather.vi v4, v8, 0
+	th.vrgather.vi v4, v8, 31
+	th.vrgather.vv v4, v8, v12, v0.t
+	th.vrgather.vx v4, v8, a1, v0.t
+	th.vrgather.vi v4, v8, 0, v0.t
+	th.vrgather.vi v4, v8, 31, v0.t
+
+	th.vcompress.vm v4, v8, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9da64bf1a74..3b7f01a145c 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -3901,6 +3901,36 @@ 
 #define MASK_TH_VIOTAM   0xfc0ff07f
 #define MATCH_TH_VIDV     0x5808a057
 #define MASK_TH_VIDV      0xfdfff07f
+#define MATCH_TH_VMVXS    0x32002057
+#define MASK_TH_VMVXS     0xfe0ff07f
+#define MATCH_TH_VEXTXV   0x32002057
+#define MASK_TH_VEXTXV    0xfe00707f
+#define MATCH_TH_VMVSX    0x36006057
+#define MASK_TH_VMVSX     0xfff0707f
+#define MATCH_TH_VFMVFS   0x32001057
+#define MASK_TH_VFMVFS    0xfe0ff07f
+#define MATCH_TH_VFMVSF   0x36005057
+#define MASK_TH_VFMVSF    0xfff0707f
+#define MATCH_TH_VSLIDEUPVX   0x38004057
+#define MASK_TH_VSLIDEUPVX    0xfc00707f
+#define MATCH_TH_VSLIDEUPVI   0x38003057
+#define MASK_TH_VSLIDEUPVI    0xfc00707f
+#define MATCH_TH_VSLIDEDOWNVX 0x3c004057
+#define MASK_TH_VSLIDEDOWNVX  0xfc00707f
+#define MATCH_TH_VSLIDEDOWNVI 0x3c003057
+#define MASK_TH_VSLIDEDOWNVI  0xfc00707f
+#define MATCH_TH_VSLIDE1UPVX   0x38006057
+#define MASK_TH_VSLIDE1UPVX    0xfc00707f
+#define MATCH_TH_VSLIDE1DOWNVX 0x3c006057
+#define MASK_TH_VSLIDE1DOWNVX  0xfc00707f
+#define MATCH_TH_VRGATHERVV   0x30000057
+#define MASK_TH_VRGATHERVV    0xfc00707f
+#define MATCH_TH_VRGATHERVX   0x30004057
+#define MASK_TH_VRGATHERVX    0xfc00707f
+#define MATCH_TH_VRGATHERVI   0x30003057
+#define MASK_TH_VRGATHERVI    0xfc00707f
+#define MATCH_TH_VCOMPRESSV   0x5e002057
+#define MASK_TH_VCOMPRESSV    0xfe00707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index fab3f7c6c39..933018842e1 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2879,6 +2879,21 @@  const struct riscv_opcode riscv_opcodes[] =
 {"th.vmsof.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, MASK_TH_VMSOFM, match_opcode, 0},
 {"th.viota.m",    0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, MASK_TH_VIOTAM, match_opcode, 0},
 {"th.vid.v",      0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_TH_VIDV, match_opcode, 0},
+{"th.vmv.x.s",    0, INSN_CLASS_XTHEADVECTOR, "d,Vt", MATCH_TH_VMVXS, MASK_TH_VMVXS, match_opcode, INSN_ALIAS},
+{"th.vext.x.v",   0, INSN_CLASS_XTHEADVECTOR, "d,Vt,s", MATCH_TH_VEXTXV, MASK_TH_VEXTXV, match_opcode, 0},
+{"th.vmv.s.x",    0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVSX, MASK_TH_VMVSX, match_opcode, 0},
+{"th.vfmv.f.s",   0, INSN_CLASS_XTHEADVECTOR, "D,Vt", MATCH_TH_VFMVFS, MASK_TH_VFMVFS, match_opcode, 0},
+{"th.vfmv.s.f",   0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_TH_VFMVSF, MASK_TH_VFMVSF, match_opcode, 0},
+{"th.vslideup.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLIDEUPVX, MASK_TH_VSLIDEUPVX, match_opcode, 0},
+{"th.vslideup.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSLIDEUPVI, MASK_TH_VSLIDEUPVI, match_opcode, 0},
+{"th.vslidedown.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLIDEDOWNVX, MASK_TH_VSLIDEDOWNVX, match_opcode, 0},
+{"th.vslidedown.vi",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSLIDEDOWNVI, MASK_TH_VSLIDEDOWNVI, match_opcode, 0},
+{"th.vslide1up.vx",0 ,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLIDE1UPVX, MASK_TH_VSLIDE1UPVX, match_opcode, 0},
+{"th.vslide1down.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLIDE1DOWNVX, MASK_TH_VSLIDE1DOWNVX, match_opcode, 0},
+{"th.vrgather.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VRGATHERVV, MASK_TH_VRGATHERVV, match_opcode, 0},
+{"th.vrgather.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VRGATHERVX, MASK_TH_VRGATHERVX, match_opcode, 0},
+{"th.vrgather.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VRGATHERVI, MASK_TH_VRGATHERVI, match_opcode, 0},
+{"th.vcompress.vm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_TH_VCOMPRESSV, MASK_TH_VCOMPRESSV, match_opcode, 0},
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },