@@ -142,3 +142,325 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+03057207[ ]+th.vleff.v[ ]+v4,\(a0\)
[ ]+[0-9a-f]+:[ ]+03057207[ ]+th.vleff.v[ ]+v4,\(a0\)
[ ]+[0-9a-f]+:[ ]+01057207[ ]+th.vleff.v[ ]+v4,\(a0\),v0.t
+[ ]+[0-9a-f]+:[ ]+02860257[ ]+th.vadd.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+0285c257[ ]+th.vadd.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+0287b257[ ]+th.vadd.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+02883257[ ]+th.vadd.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+00860257[ ]+th.vadd.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+0085c257[ ]+th.vadd.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+0087b257[ ]+th.vadd.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+00883257[ ]+th.vadd.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+0a860257[ ]+th.vsub.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+0a85c257[ ]+th.vsub.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+0e85c257[ ]+th.vrsub.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+0e87b257[ ]+th.vrsub.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+0e883257[ ]+th.vrsub.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+08860257[ ]+th.vsub.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+0885c257[ ]+th.vsub.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+0c85c257[ ]+th.vrsub.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+0c87b257[ ]+th.vrsub.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+0c883257[ ]+th.vrsub.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+c6806257[ ]+th.vwcvt.x.x.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+c2806257[ ]+th.vwcvtu.x.x.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+c4806257[ ]+th.vwcvt.x.x.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+c0806257[ ]+th.vwcvtu.x.x.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+c2862257[ ]+th.vwaddu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+c285e257[ ]+th.vwaddu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+c0862257[ ]+th.vwaddu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c085e257[ ]+th.vwaddu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+ca862257[ ]+th.vwsubu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+ca85e257[ ]+th.vwsubu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+c8862257[ ]+th.vwsubu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c885e257[ ]+th.vwsubu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+c6862257[ ]+th.vwadd.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+c685e257[ ]+th.vwadd.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+c4862257[ ]+th.vwadd.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+c485e257[ ]+th.vwadd.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+ce862257[ ]+th.vwsub.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+ce85e257[ ]+th.vwsub.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+cc862257[ ]+th.vwsub.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+cc85e257[ ]+th.vwsub.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+d2862257[ ]+th.vwaddu.wv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+d285e257[ ]+th.vwaddu.wx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+d0862257[ ]+th.vwaddu.wv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+d085e257[ ]+th.vwaddu.wx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+da862257[ ]+th.vwsubu.wv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+da85e257[ ]+th.vwsubu.wx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+d8862257[ ]+th.vwsubu.wv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+d885e257[ ]+th.vwsubu.wx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+d6862257[ ]+th.vwadd.wv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+d685e257[ ]+th.vwadd.wx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+d4862257[ ]+th.vwadd.wv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+d485e257[ ]+th.vwadd.wx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+de862257[ ]+th.vwsub.wv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+de85e257[ ]+th.vwsub.wx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+dc862257[ ]+th.vwsub.wv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+dc85e257[ ]+th.vwsub.wx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+42860257[ ]+th.vadc.vvm[ ]+v4,v8,v12,v0
+[ ]+[0-9a-f]+:[ ]+4285c257[ ]+th.vadc.vxm[ ]+v4,v8,a1,v0
+[ ]+[0-9a-f]+:[ ]+4287b257[ ]+th.vadc.vim[ ]+v4,v8,15,v0
+[ ]+[0-9a-f]+:[ ]+42883257[ ]+th.vadc.vim[ ]+v4,v8,-16,v0
+[ ]+[0-9a-f]+:[ ]+46860257[ ]+th.vmadc.vvm[ ]+v4,v8,v12,v0
+[ ]+[0-9a-f]+:[ ]+4685c257[ ]+th.vmadc.vxm[ ]+v4,v8,a1,v0
+[ ]+[0-9a-f]+:[ ]+4687b257[ ]+th.vmadc.vim[ ]+v4,v8,15,v0
+[ ]+[0-9a-f]+:[ ]+46883257[ ]+th.vmadc.vim[ ]+v4,v8,-16,v0
+[ ]+[0-9a-f]+:[ ]+4a860257[ ]+th.vsbc.vvm[ ]+v4,v8,v12,v0
+[ ]+[0-9a-f]+:[ ]+4a85c257[ ]+th.vsbc.vxm[ ]+v4,v8,a1,v0
+[ ]+[0-9a-f]+:[ ]+4e860257[ ]+th.vmsbc.vvm[ ]+v4,v8,v12,v0
+[ ]+[0-9a-f]+:[ ]+4e85c257[ ]+th.vmsbc.vxm[ ]+v4,v8,a1,v0
+[ ]+[0-9a-f]+:[ ]+2e8fb257[ ]+th.vnot.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+2c8fb257[ ]+th.vnot.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+26860257[ ]+th.vand.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+2685c257[ ]+th.vand.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+2687b257[ ]+th.vand.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+26883257[ ]+th.vand.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+24860257[ ]+th.vand.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+2485c257[ ]+th.vand.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+2487b257[ ]+th.vand.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+24883257[ ]+th.vand.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+2a860257[ ]+th.vor.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+2a85c257[ ]+th.vor.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+2a87b257[ ]+th.vor.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+2a883257[ ]+th.vor.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+28860257[ ]+th.vor.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+2885c257[ ]+th.vor.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+2887b257[ ]+th.vor.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+28883257[ ]+th.vor.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+2e860257[ ]+th.vxor.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+2e85c257[ ]+th.vxor.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+2e87b257[ ]+th.vxor.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+2e883257[ ]+th.vxor.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+2c860257[ ]+th.vxor.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+2c85c257[ ]+th.vxor.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+2c87b257[ ]+th.vxor.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+2c883257[ ]+th.vxor.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+96860257[ ]+th.vsll.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+9685c257[ ]+th.vsll.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+9680b257[ ]+th.vsll.vi[ ]+v4,v8,1
+[ ]+[0-9a-f]+:[ ]+968fb257[ ]+th.vsll.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+94860257[ ]+th.vsll.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+9485c257[ ]+th.vsll.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+9480b257[ ]+th.vsll.vi[ ]+v4,v8,1,v0.t
+[ ]+[0-9a-f]+:[ ]+948fb257[ ]+th.vsll.vi[ ]+v4,v8,31,v0.t
+[ ]+[0-9a-f]+:[ ]+a2860257[ ]+th.vsrl.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+a285c257[ ]+th.vsrl.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+a280b257[ ]+th.vsrl.vi[ ]+v4,v8,1
+[ ]+[0-9a-f]+:[ ]+a28fb257[ ]+th.vsrl.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+a0860257[ ]+th.vsrl.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+a085c257[ ]+th.vsrl.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+a080b257[ ]+th.vsrl.vi[ ]+v4,v8,1,v0.t
+[ ]+[0-9a-f]+:[ ]+a08fb257[ ]+th.vsrl.vi[ ]+v4,v8,31,v0.t
+[ ]+[0-9a-f]+:[ ]+a6860257[ ]+th.vsra.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+a685c257[ ]+th.vsra.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+a680b257[ ]+th.vsra.vi[ ]+v4,v8,1
+[ ]+[0-9a-f]+:[ ]+a68fb257[ ]+th.vsra.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+a4860257[ ]+th.vsra.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+a485c257[ ]+th.vsra.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+a480b257[ ]+th.vsra.vi[ ]+v4,v8,1,v0.t
+[ ]+[0-9a-f]+:[ ]+a48fb257[ ]+th.vsra.vi[ ]+v4,v8,31,v0.t
+[ ]+[0-9a-f]+:[ ]+b2860257[ ]+th.vnsrl.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+b285c257[ ]+th.vnsrl.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+b280b257[ ]+th.vnsrl.vi[ ]+v4,v8,1
+[ ]+[0-9a-f]+:[ ]+b28fb257[ ]+th.vnsrl.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+b0860257[ ]+th.vnsrl.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+b085c257[ ]+th.vnsrl.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+b080b257[ ]+th.vnsrl.vi[ ]+v4,v8,1,v0.t
+[ ]+[0-9a-f]+:[ ]+b08fb257[ ]+th.vnsrl.vi[ ]+v4,v8,31,v0.t
+[ ]+[0-9a-f]+:[ ]+b6860257[ ]+th.vnsra.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+b685c257[ ]+th.vnsra.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+b680b257[ ]+th.vnsra.vi[ ]+v4,v8,1
+[ ]+[0-9a-f]+:[ ]+b68fb257[ ]+th.vnsra.vi[ ]+v4,v8,31
+[ ]+[0-9a-f]+:[ ]+b4860257[ ]+th.vnsra.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+b485c257[ ]+th.vnsra.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+b480b257[ ]+th.vnsra.vi[ ]+v4,v8,1,v0.t
+[ ]+[0-9a-f]+:[ ]+b48fb257[ ]+th.vnsra.vi[ ]+v4,v8,31,v0.t
+[ ]+[0-9a-f]+:[ ]+6ec40257[ ]+th.vmslt.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+6ac40257[ ]+th.vmsltu.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+76c40257[ ]+th.vmsle.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+72c40257[ ]+th.vmsleu.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+6cc40257[ ]+th.vmslt.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+68c40257[ ]+th.vmsltu.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+74c40257[ ]+th.vmsle.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+70c40257[ ]+th.vmsleu.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+7687b257[ ]+th.vmsle.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+76883257[ ]+th.vmsle.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+7287b257[ ]+th.vmsleu.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+72883257[ ]+th.vmsleu.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+7e87b257[ ]+th.vmsgt.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+7e883257[ ]+th.vmsgt.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+7a87b257[ ]+th.vmsgtu.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+7a883257[ ]+th.vmsgtu.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+7487b257[ ]+th.vmsle.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+74883257[ ]+th.vmsle.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+7087b257[ ]+th.vmsleu.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+70883257[ ]+th.vmsleu.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+7c87b257[ ]+th.vmsgt.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+7c883257[ ]+th.vmsgt.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+7887b257[ ]+th.vmsgtu.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+78883257[ ]+th.vmsgtu.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+th.vmslt.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+76422257[ ]+th.vmnot.m[ ]+v4,v4
+[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+th.vmsltu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+76422257[ ]+th.vmnot.m[ ]+v4,v4
+[ ]+[0-9a-f]+:[ ]+6cc64457[ ]+th.vmslt.vx[ ]+v8,v12,a2,v0.t
+[ ]+[0-9a-f]+:[ ]+6e802457[ ]+th.vmxor.mm[ ]+v8,v8,v0
+[ ]+[0-9a-f]+:[ ]+68c64457[ ]+th.vmsltu.vx[ ]+v8,v12,a2,v0.t
+[ ]+[0-9a-f]+:[ ]+6e802457[ ]+th.vmxor.mm[ ]+v8,v8,v0
+[ ]+[0-9a-f]+:[ ]+6e85c657[ ]+th.vmslt.vx[ ]+v12,v8,a1
+[ ]+[0-9a-f]+:[ ]+62062657[ ]+th.vmandnot.mm[ ]+v12,v0,v12
+[ ]+[0-9a-f]+:[ ]+62402257[ ]+th.vmandnot.mm[ ]+v4,v4,v0
+[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+th.vmor.mm[ ]+v4,v12,v4
+[ ]+[0-9a-f]+:[ ]+6a85c657[ ]+th.vmsltu.vx[ ]+v12,v8,a1
+[ ]+[0-9a-f]+:[ ]+62062657[ ]+th.vmandnot.mm[ ]+v12,v0,v12
+[ ]+[0-9a-f]+:[ ]+62402257[ ]+th.vmandnot.mm[ ]+v4,v4,v0
+[ ]+[0-9a-f]+:[ ]+6ac22257[ ]+th.vmor.mm[ ]+v4,v12,v4
+[ ]+[0-9a-f]+:[ ]+62860257[ ]+th.vmseq.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+6285c257[ ]+th.vmseq.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+6287b257[ ]+th.vmseq.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+62883257[ ]+th.vmseq.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+60860257[ ]+th.vmseq.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+6085c257[ ]+th.vmseq.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+6087b257[ ]+th.vmseq.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+60883257[ ]+th.vmseq.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+66860257[ ]+th.vmsne.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+6685c257[ ]+th.vmsne.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+6687b257[ ]+th.vmsne.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+66883257[ ]+th.vmsne.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+64860257[ ]+th.vmsne.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+6485c257[ ]+th.vmsne.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+6487b257[ ]+th.vmsne.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+64883257[ ]+th.vmsne.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+6a860257[ ]+th.vmsltu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+6a85c257[ ]+th.vmsltu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+68860257[ ]+th.vmsltu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+6885c257[ ]+th.vmsltu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+6e860257[ ]+th.vmslt.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+6e85c257[ ]+th.vmslt.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+6c860257[ ]+th.vmslt.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+6c85c257[ ]+th.vmslt.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+72860257[ ]+th.vmsleu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+7285c257[ ]+th.vmsleu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+7287b257[ ]+th.vmsleu.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+72883257[ ]+th.vmsleu.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+70860257[ ]+th.vmsleu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+7085c257[ ]+th.vmsleu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+7087b257[ ]+th.vmsleu.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+70883257[ ]+th.vmsleu.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+76860257[ ]+th.vmsle.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+7685c257[ ]+th.vmsle.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+7687b257[ ]+th.vmsle.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+76883257[ ]+th.vmsle.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+74860257[ ]+th.vmsle.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+7485c257[ ]+th.vmsle.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+7487b257[ ]+th.vmsle.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+74883257[ ]+th.vmsle.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+7a85c257[ ]+th.vmsgtu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+7a87b257[ ]+th.vmsgtu.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+7a883257[ ]+th.vmsgtu.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+7885c257[ ]+th.vmsgtu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+7887b257[ ]+th.vmsgtu.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+78883257[ ]+th.vmsgtu.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+7e85c257[ ]+th.vmsgt.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+7e87b257[ ]+th.vmsgt.vi[ ]+v4,v8,15
+[ ]+[0-9a-f]+:[ ]+7e883257[ ]+th.vmsgt.vi[ ]+v4,v8,-16
+[ ]+[0-9a-f]+:[ ]+7c85c257[ ]+th.vmsgt.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+7c87b257[ ]+th.vmsgt.vi[ ]+v4,v8,15,v0.t
+[ ]+[0-9a-f]+:[ ]+7c883257[ ]+th.vmsgt.vi[ ]+v4,v8,-16,v0.t
+[ ]+[0-9a-f]+:[ ]+12860257[ ]+th.vminu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+1285c257[ ]+th.vminu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+10860257[ ]+th.vminu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+1085c257[ ]+th.vminu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+16860257[ ]+th.vmin.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+1685c257[ ]+th.vmin.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+14860257[ ]+th.vmin.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+1485c257[ ]+th.vmin.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+1a860257[ ]+th.vmaxu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+1a85c257[ ]+th.vmaxu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+18860257[ ]+th.vmaxu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+1885c257[ ]+th.vmaxu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+1e860257[ ]+th.vmax.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+1e85c257[ ]+th.vmax.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+1c860257[ ]+th.vmax.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+1c85c257[ ]+th.vmax.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+96862257[ ]+th.vmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+9685e257[ ]+th.vmul.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+94862257[ ]+th.vmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+9485e257[ ]+th.vmul.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+9e862257[ ]+th.vmulh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+9e85e257[ ]+th.vmulh.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+9c862257[ ]+th.vmulh.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+9c85e257[ ]+th.vmulh.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+92862257[ ]+th.vmulhu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+9285e257[ ]+th.vmulhu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+90862257[ ]+th.vmulhu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+9085e257[ ]+th.vmulhu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+9a862257[ ]+th.vmulhsu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+9a85e257[ ]+th.vmulhsu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+98862257[ ]+th.vmulhsu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+9885e257[ ]+th.vmulhsu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+ee862257[ ]+th.vwmul.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+ee85e257[ ]+th.vwmul.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+ec862257[ ]+th.vwmul.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+ec85e257[ ]+th.vwmul.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+e2862257[ ]+th.vwmulu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+e285e257[ ]+th.vwmulu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+e0862257[ ]+th.vwmulu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+e085e257[ ]+th.vwmulu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+ea862257[ ]+th.vwmulsu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+ea85e257[ ]+th.vwmulsu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+e8862257[ ]+th.vwmulsu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+e885e257[ ]+th.vwmulsu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+b6862257[ ]+th.vmacc.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+b685e257[ ]+th.vmacc.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+b4862257[ ]+th.vmacc.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+b485e257[ ]+th.vmacc.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+be862257[ ]+th.vnmsac.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+be85e257[ ]+th.vnmsac.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+bc862257[ ]+th.vnmsac.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+bc85e257[ ]+th.vnmsac.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+a6862257[ ]+th.vmadd.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+a685e257[ ]+th.vmadd.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+a4862257[ ]+th.vmadd.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+a485e257[ ]+th.vmadd.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+ae862257[ ]+th.vnmsub.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+ae85e257[ ]+th.vnmsub.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+ac862257[ ]+th.vnmsub.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+ac85e257[ ]+th.vnmsub.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f2862257[ ]+th.vwmaccu.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+f285e257[ ]+th.vwmaccu.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+f0862257[ ]+th.vwmaccu.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f085e257[ ]+th.vwmaccu.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f6862257[ ]+th.vwmacc.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+f685e257[ ]+th.vwmacc.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+f4862257[ ]+th.vwmacc.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f485e257[ ]+th.vwmacc.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+fa862257[ ]+th.vwmaccsu.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+fa85e257[ ]+th.vwmaccsu.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+f8862257[ ]+th.vwmaccsu.vv[ ]+v4,v12,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+f885e257[ ]+th.vwmaccsu.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+fe85e257[ ]+th.vwmaccus.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+fc85e257[ ]+th.vwmaccus.vx[ ]+v4,a1,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+82862257[ ]+th.vdivu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+8285e257[ ]+th.vdivu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+80862257[ ]+th.vdivu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+8085e257[ ]+th.vdivu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+86862257[ ]+th.vdiv.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+8685e257[ ]+th.vdiv.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+84862257[ ]+th.vdiv.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+8485e257[ ]+th.vdiv.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+8a862257[ ]+th.vremu.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+8a85e257[ ]+th.vremu.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+88862257[ ]+th.vremu.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+8885e257[ ]+th.vremu.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+8e862257[ ]+th.vrem.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+8e85e257[ ]+th.vrem.vx[ ]+v4,v8,a1
+[ ]+[0-9a-f]+:[ ]+8c862257[ ]+th.vrem.vv[ ]+v4,v8,v12,v0.t
+[ ]+[0-9a-f]+:[ ]+8c85e257[ ]+th.vrem.vx[ ]+v4,v8,a1,v0.t
+[ ]+[0-9a-f]+:[ ]+5c860257[ ]+th.vmerge.vvm[ ]+v4,v8,v12,v0
+[ ]+[0-9a-f]+:[ ]+5c85c257[ ]+th.vmerge.vxm[ ]+v4,v8,a1,v0
+[ ]+[0-9a-f]+:[ ]+5c87b257[ ]+th.vmerge.vim[ ]+v4,v8,15,v0
+[ ]+[0-9a-f]+:[ ]+5c883257[ ]+th.vmerge.vim[ ]+v4,v8,-16,v0
+[ ]+[0-9a-f]+:[ ]+5e060457[ ]+th.vmv.v.v[ ]+v8,v12
+[ ]+[0-9a-f]+:[ ]+5e05c457[ ]+th.vmv.v.x[ ]+v8,a1
+[ ]+[0-9a-f]+:[ ]+5e07b457[ ]+th.vmv.v.i[ ]+v8,15
+[ ]+[0-9a-f]+:[ ]+5e083457[ ]+th.vmv.v.i[ ]+v8,-16
@@ -137,3 +137,338 @@
th.vleff.v v4, (a0)
th.vleff.v v4, 0(a0)
th.vleff.v v4, (a0), v0.t
+
+ th.vadd.vv v4, v8, v12
+ th.vadd.vx v4, v8, a1
+ th.vadd.vi v4, v8, 15
+ th.vadd.vi v4, v8, -16
+ th.vadd.vv v4, v8, v12, v0.t
+ th.vadd.vx v4, v8, a1, v0.t
+ th.vadd.vi v4, v8, 15, v0.t
+ th.vadd.vi v4, v8, -16, v0.t
+ th.vsub.vv v4, v8, v12
+ th.vsub.vx v4, v8, a1
+ th.vrsub.vx v4, v8, a1
+ th.vrsub.vi v4, v8, 15
+ th.vrsub.vi v4, v8, -16
+ th.vsub.vv v4, v8, v12, v0.t
+ th.vsub.vx v4, v8, a1, v0.t
+ th.vrsub.vx v4, v8, a1, v0.t
+ th.vrsub.vi v4, v8, 15, v0.t
+ th.vrsub.vi v4, v8, -16, v0.t
+
+ # Aliases
+ th.vwcvt.x.x.v v4, v8
+ th.vwcvtu.x.x.v v4, v8
+ th.vwcvt.x.x.v v4, v8, v0.t
+ th.vwcvtu.x.x.v v4, v8, v0.t
+
+ th.vwaddu.vv v4, v8, v12
+ th.vwaddu.vx v4, v8, a1
+ th.vwaddu.vv v4, v8, v12, v0.t
+ th.vwaddu.vx v4, v8, a1, v0.t
+ th.vwsubu.vv v4, v8, v12
+ th.vwsubu.vx v4, v8, a1
+ th.vwsubu.vv v4, v8, v12, v0.t
+ th.vwsubu.vx v4, v8, a1, v0.t
+ th.vwadd.vv v4, v8, v12
+ th.vwadd.vx v4, v8, a1
+ th.vwadd.vv v4, v8, v12, v0.t
+ th.vwadd.vx v4, v8, a1, v0.t
+ th.vwsub.vv v4, v8, v12
+ th.vwsub.vx v4, v8, a1
+ th.vwsub.vv v4, v8, v12, v0.t
+ th.vwsub.vx v4, v8, a1, v0.t
+ th.vwaddu.wv v4, v8, v12
+ th.vwaddu.wx v4, v8, a1
+ th.vwaddu.wv v4, v8, v12, v0.t
+ th.vwaddu.wx v4, v8, a1, v0.t
+ th.vwsubu.wv v4, v8, v12
+ th.vwsubu.wx v4, v8, a1
+ th.vwsubu.wv v4, v8, v12, v0.t
+ th.vwsubu.wx v4, v8, a1, v0.t
+ th.vwadd.wv v4, v8, v12
+ th.vwadd.wx v4, v8, a1
+ th.vwadd.wv v4, v8, v12, v0.t
+ th.vwadd.wx v4, v8, a1, v0.t
+ th.vwsub.wv v4, v8, v12
+ th.vwsub.wx v4, v8, a1
+ th.vwsub.wv v4, v8, v12, v0.t
+ th.vwsub.wx v4, v8, a1, v0.t
+
+ th.vadc.vvm v4, v8, v12, v0
+ th.vadc.vxm v4, v8, a1, v0
+ th.vadc.vim v4, v8, 15, v0
+ th.vadc.vim v4, v8, -16, v0
+ th.vmadc.vvm v4, v8, v12, v0
+ th.vmadc.vxm v4, v8, a1, v0
+ th.vmadc.vim v4, v8, 15, v0
+ th.vmadc.vim v4, v8, -16, v0
+ th.vsbc.vvm v4, v8, v12, v0
+ th.vsbc.vxm v4, v8, a1, v0
+ th.vmsbc.vvm v4, v8, v12, v0
+ th.vmsbc.vxm v4, v8, a1, v0
+
+ # Aliases
+ th.vnot.v v4, v8
+ th.vnot.v v4, v8, v0.t
+
+ th.vand.vv v4, v8, v12
+ th.vand.vx v4, v8, a1
+ th.vand.vi v4, v8, 15
+ th.vand.vi v4, v8, -16
+ th.vand.vv v4, v8, v12, v0.t
+ th.vand.vx v4, v8, a1, v0.t
+ th.vand.vi v4, v8, 15, v0.t
+ th.vand.vi v4, v8, -16, v0.t
+ th.vor.vv v4, v8, v12
+ th.vor.vx v4, v8, a1
+ th.vor.vi v4, v8, 15
+ th.vor.vi v4, v8, -16
+ th.vor.vv v4, v8, v12, v0.t
+ th.vor.vx v4, v8, a1, v0.t
+ th.vor.vi v4, v8, 15, v0.t
+ th.vor.vi v4, v8, -16, v0.t
+ th.vxor.vv v4, v8, v12
+ th.vxor.vx v4, v8, a1
+ th.vxor.vi v4, v8, 15
+ th.vxor.vi v4, v8, -16
+ th.vxor.vv v4, v8, v12, v0.t
+ th.vxor.vx v4, v8, a1, v0.t
+ th.vxor.vi v4, v8, 15, v0.t
+ th.vxor.vi v4, v8, -16, v0.t
+
+ th.vsll.vv v4, v8, v12
+ th.vsll.vx v4, v8, a1
+ th.vsll.vi v4, v8, 1
+ th.vsll.vi v4, v8, 31
+ th.vsll.vv v4, v8, v12, v0.t
+ th.vsll.vx v4, v8, a1, v0.t
+ th.vsll.vi v4, v8, 1, v0.t
+ th.vsll.vi v4, v8, 31, v0.t
+ th.vsrl.vv v4, v8, v12
+ th.vsrl.vx v4, v8, a1
+ th.vsrl.vi v4, v8, 1
+ th.vsrl.vi v4, v8, 31
+ th.vsrl.vv v4, v8, v12, v0.t
+ th.vsrl.vx v4, v8, a1, v0.t
+ th.vsrl.vi v4, v8, 1, v0.t
+ th.vsrl.vi v4, v8, 31, v0.t
+ th.vsra.vv v4, v8, v12
+ th.vsra.vx v4, v8, a1
+ th.vsra.vi v4, v8, 1
+ th.vsra.vi v4, v8, 31
+ th.vsra.vv v4, v8, v12, v0.t
+ th.vsra.vx v4, v8, a1, v0.t
+ th.vsra.vi v4, v8, 1, v0.t
+ th.vsra.vi v4, v8, 31, v0.t
+
+ th.vnsrl.vv v4, v8, v12
+ th.vnsrl.vx v4, v8, a1
+ th.vnsrl.vi v4, v8, 1
+ th.vnsrl.vi v4, v8, 31
+ th.vnsrl.vv v4, v8, v12, v0.t
+ th.vnsrl.vx v4, v8, a1, v0.t
+ th.vnsrl.vi v4, v8, 1, v0.t
+ th.vnsrl.vi v4, v8, 31, v0.t
+ th.vnsra.vv v4, v8, v12
+ th.vnsra.vx v4, v8, a1
+ th.vnsra.vi v4, v8, 1
+ th.vnsra.vi v4, v8, 31
+ th.vnsra.vv v4, v8, v12, v0.t
+ th.vnsra.vx v4, v8, a1, v0.t
+ th.vnsra.vi v4, v8, 1, v0.t
+ th.vnsra.vi v4, v8, 31, v0.t
+
+ # Aliases
+ th.vmsgt.vv v4, v8, v12
+ th.vmsgtu.vv v4, v8, v12
+ th.vmsge.vv v4, v8, v12
+ th.vmsgeu.vv v4, v8, v12
+ th.vmsgt.vv v4, v8, v12, v0.t
+ th.vmsgtu.vv v4, v8, v12, v0.t
+ th.vmsge.vv v4, v8, v12, v0.t
+ th.vmsgeu.vv v4, v8, v12, v0.t
+ th.vmslt.vi v4, v8, 16
+ th.vmslt.vi v4, v8, -15
+ th.vmsltu.vi v4, v8, 16
+ th.vmsltu.vi v4, v8, -15
+ th.vmsge.vi v4, v8, 16
+ th.vmsge.vi v4, v8, -15
+ th.vmsgeu.vi v4, v8, 16
+ th.vmsgeu.vi v4, v8, -15
+ th.vmslt.vi v4, v8, 16, v0.t
+ th.vmslt.vi v4, v8, -15, v0.t
+ th.vmsltu.vi v4, v8, 16, v0.t
+ th.vmsltu.vi v4, v8, -15, v0.t
+ th.vmsge.vi v4, v8, 16, v0.t
+ th.vmsge.vi v4, v8, -15, v0.t
+ th.vmsgeu.vi v4, v8, 16, v0.t
+ th.vmsgeu.vi v4, v8, -15, v0.t
+
+ # Macros
+ th.vmsge.vx v4, v8, a1
+ th.vmsgeu.vx v4, v8, a1
+ th.vmsge.vx v8, v12, a2, v0.t
+ th.vmsgeu.vx v8, v12, a2, v0.t
+ th.vmsge.vx v4, v8, a1, v0.t, v12
+ th.vmsgeu.vx v4, v8, a1, v0.t, v12
+
+ th.vmseq.vv v4, v8, v12
+ th.vmseq.vx v4, v8, a1
+ th.vmseq.vi v4, v8, 15
+ th.vmseq.vi v4, v8, -16
+ th.vmseq.vv v4, v8, v12, v0.t
+ th.vmseq.vx v4, v8, a1, v0.t
+ th.vmseq.vi v4, v8, 15, v0.t
+ th.vmseq.vi v4, v8, -16, v0.t
+ th.vmsne.vv v4, v8, v12
+ th.vmsne.vx v4, v8, a1
+ th.vmsne.vi v4, v8, 15
+ th.vmsne.vi v4, v8, -16
+ th.vmsne.vv v4, v8, v12, v0.t
+ th.vmsne.vx v4, v8, a1, v0.t
+ th.vmsne.vi v4, v8, 15, v0.t
+ th.vmsne.vi v4, v8, -16, v0.t
+ th.vmsltu.vv v4, v8, v12
+ th.vmsltu.vx v4, v8, a1
+ th.vmsltu.vv v4, v8, v12, v0.t
+ th.vmsltu.vx v4, v8, a1, v0.t
+ th.vmslt.vv v4, v8, v12
+ th.vmslt.vx v4, v8, a1
+ th.vmslt.vv v4, v8, v12, v0.t
+ th.vmslt.vx v4, v8, a1, v0.t
+ th.vmsleu.vv v4, v8, v12
+ th.vmsleu.vx v4, v8, a1
+ th.vmsleu.vi v4, v8, 15
+ th.vmsleu.vi v4, v8, -16
+ th.vmsleu.vv v4, v8, v12, v0.t
+ th.vmsleu.vx v4, v8, a1, v0.t
+ th.vmsleu.vi v4, v8, 15, v0.t
+ th.vmsleu.vi v4, v8, -16, v0.t
+ th.vmsle.vv v4, v8, v12
+ th.vmsle.vx v4, v8, a1
+ th.vmsle.vi v4, v8, 15
+ th.vmsle.vi v4, v8, -16
+ th.vmsle.vv v4, v8, v12, v0.t
+ th.vmsle.vx v4, v8, a1, v0.t
+ th.vmsle.vi v4, v8, 15, v0.t
+ th.vmsle.vi v4, v8, -16, v0.t
+ th.vmsgtu.vx v4, v8, a1
+ th.vmsgtu.vi v4, v8, 15
+ th.vmsgtu.vi v4, v8, -16
+ th.vmsgtu.vx v4, v8, a1, v0.t
+ th.vmsgtu.vi v4, v8, 15, v0.t
+ th.vmsgtu.vi v4, v8, -16, v0.t
+ th.vmsgt.vx v4, v8, a1
+ th.vmsgt.vi v4, v8, 15
+ th.vmsgt.vi v4, v8, -16
+ th.vmsgt.vx v4, v8, a1, v0.t
+ th.vmsgt.vi v4, v8, 15, v0.t
+ th.vmsgt.vi v4, v8, -16, v0.t
+
+ th.vminu.vv v4, v8, v12
+ th.vminu.vx v4, v8, a1
+ th.vminu.vv v4, v8, v12, v0.t
+ th.vminu.vx v4, v8, a1, v0.t
+ th.vmin.vv v4, v8, v12
+ th.vmin.vx v4, v8, a1
+ th.vmin.vv v4, v8, v12, v0.t
+ th.vmin.vx v4, v8, a1, v0.t
+ th.vmaxu.vv v4, v8, v12
+ th.vmaxu.vx v4, v8, a1
+ th.vmaxu.vv v4, v8, v12, v0.t
+ th.vmaxu.vx v4, v8, a1, v0.t
+ th.vmax.vv v4, v8, v12
+ th.vmax.vx v4, v8, a1
+ th.vmax.vv v4, v8, v12, v0.t
+ th.vmax.vx v4, v8, a1, v0.t
+
+ th.vmul.vv v4, v8, v12
+ th.vmul.vx v4, v8, a1
+ th.vmul.vv v4, v8, v12, v0.t
+ th.vmul.vx v4, v8, a1, v0.t
+ th.vmulh.vv v4, v8, v12
+ th.vmulh.vx v4, v8, a1
+ th.vmulh.vv v4, v8, v12, v0.t
+ th.vmulh.vx v4, v8, a1, v0.t
+ th.vmulhu.vv v4, v8, v12
+ th.vmulhu.vx v4, v8, a1
+ th.vmulhu.vv v4, v8, v12, v0.t
+ th.vmulhu.vx v4, v8, a1, v0.t
+ th.vmulhsu.vv v4, v8, v12
+ th.vmulhsu.vx v4, v8, a1
+ th.vmulhsu.vv v4, v8, v12, v0.t
+ th.vmulhsu.vx v4, v8, a1, v0.t
+
+ th.vwmul.vv v4, v8, v12
+ th.vwmul.vx v4, v8, a1
+ th.vwmul.vv v4, v8, v12, v0.t
+ th.vwmul.vx v4, v8, a1, v0.t
+ th.vwmulu.vv v4, v8, v12
+ th.vwmulu.vx v4, v8, a1
+ th.vwmulu.vv v4, v8, v12, v0.t
+ th.vwmulu.vx v4, v8, a1, v0.t
+ th.vwmulsu.vv v4, v8, v12
+ th.vwmulsu.vx v4, v8, a1
+ th.vwmulsu.vv v4, v8, v12, v0.t
+ th.vwmulsu.vx v4, v8, a1, v0.t
+
+ th.vmacc.vv v4, v12, v8
+ th.vmacc.vx v4, a1, v8
+ th.vmacc.vv v4, v12, v8, v0.t
+ th.vmacc.vx v4, a1, v8, v0.t
+ th.vnmsac.vv v4, v12, v8
+ th.vnmsac.vx v4, a1, v8
+ th.vnmsac.vv v4, v12, v8, v0.t
+ th.vnmsac.vx v4, a1, v8, v0.t
+ th.vmadd.vv v4, v12, v8
+ th.vmadd.vx v4, a1, v8
+ th.vmadd.vv v4, v12, v8, v0.t
+ th.vmadd.vx v4, a1, v8, v0.t
+ th.vnmsub.vv v4, v12, v8
+ th.vnmsub.vx v4, a1, v8
+ th.vnmsub.vv v4, v12, v8, v0.t
+ th.vnmsub.vx v4, a1, v8, v0.t
+
+ th.vwmaccu.vv v4, v12, v8
+ th.vwmaccu.vx v4, a1, v8
+ th.vwmaccu.vv v4, v12, v8, v0.t
+ th.vwmaccu.vx v4, a1, v8, v0.t
+ th.vwmacc.vv v4, v12, v8
+ th.vwmacc.vx v4, a1, v8
+ th.vwmacc.vv v4, v12, v8, v0.t
+ th.vwmacc.vx v4, a1, v8, v0.t
+ th.vwmaccsu.vv v4, v12, v8
+ th.vwmaccsu.vx v4, a1, v8
+ th.vwmaccsu.vv v4, v12, v8, v0.t
+ th.vwmaccsu.vx v4, a1, v8, v0.t
+ th.vwmaccus.vx v4, a1, v8
+ th.vwmaccus.vx v4, a1, v8, v0.t
+
+ th.vdivu.vv v4, v8, v12
+ th.vdivu.vx v4, v8, a1
+ th.vdivu.vv v4, v8, v12, v0.t
+ th.vdivu.vx v4, v8, a1, v0.t
+ th.vdiv.vv v4, v8, v12
+ th.vdiv.vx v4, v8, a1
+ th.vdiv.vv v4, v8, v12, v0.t
+ th.vdiv.vx v4, v8, a1, v0.t
+ th.vremu.vv v4, v8, v12
+ th.vremu.vx v4, v8, a1
+ th.vremu.vv v4, v8, v12, v0.t
+ th.vremu.vx v4, v8, a1, v0.t
+ th.vrem.vv v4, v8, v12
+ th.vrem.vx v4, v8, a1
+ th.vrem.vv v4, v8, v12, v0.t
+ th.vrem.vx v4, v8, a1, v0.t
+
+ th.vmerge.vvm v4, v8, v12, v0
+ th.vmerge.vxm v4, v8, a1, v0
+ th.vmerge.vim v4, v8, 15, v0
+ th.vmerge.vim v4, v8, -16, v0
+
+ th.vmv.v.v v8, v12
+ th.vmv.v.x v8, a1
+ th.vmv.v.i v8, 15
+ th.vmv.v.i v8, -16
@@ -3337,6 +3337,268 @@
#define MASK_TH_VAMOMAXUWV 0xf800707f
#define MATCH_TH_VAMOMAXUDV 0xe000702f
#define MASK_TH_VAMOMAXUDV 0xf800707f
+#define MATCH_TH_VADDVV 0x00000057
+#define MASK_TH_VADDVV 0xfc00707f
+#define MATCH_TH_VADDVX 0x00004057
+#define MASK_TH_VADDVX 0xfc00707f
+#define MATCH_TH_VADDVI 0x00003057
+#define MASK_TH_VADDVI 0xfc00707f
+#define MATCH_TH_VSUBVV 0x08000057
+#define MASK_TH_VSUBVV 0xfc00707f
+#define MATCH_TH_VSUBVX 0x08004057
+#define MASK_TH_VSUBVX 0xfc00707f
+#define MATCH_TH_VRSUBVX 0x0c004057
+#define MASK_TH_VRSUBVX 0xfc00707f
+#define MATCH_TH_VRSUBVI 0x0c003057
+#define MASK_TH_VRSUBVI 0xfc00707f
+#define MATCH_TH_VWCVTXXV 0xc4006057
+#define MASK_TH_VWCVTXXV 0xfc0ff07f
+#define MATCH_TH_VWCVTUXXV 0xc0006057
+#define MASK_TH_VWCVTUXXV 0xfc0ff07f
+#define MATCH_TH_VWADDVV 0xc4002057
+#define MASK_TH_VWADDVV 0xfc00707f
+#define MATCH_TH_VWADDVX 0xc4006057
+#define MASK_TH_VWADDVX 0xfc00707f
+#define MATCH_TH_VWSUBVV 0xcc002057
+#define MASK_TH_VWSUBVV 0xfc00707f
+#define MATCH_TH_VWSUBVX 0xcc006057
+#define MASK_TH_VWSUBVX 0xfc00707f
+#define MATCH_TH_VWADDWV 0xd4002057
+#define MASK_TH_VWADDWV 0xfc00707f
+#define MATCH_TH_VWADDWX 0xd4006057
+#define MASK_TH_VWADDWX 0xfc00707f
+#define MATCH_TH_VWSUBWV 0xdc002057
+#define MASK_TH_VWSUBWV 0xfc00707f
+#define MATCH_TH_VWSUBWX 0xdc006057
+#define MASK_TH_VWSUBWX 0xfc00707f
+#define MATCH_TH_VWADDUVV 0xc0002057
+#define MASK_TH_VWADDUVV 0xfc00707f
+#define MATCH_TH_VWADDUVX 0xc0006057
+#define MASK_TH_VWADDUVX 0xfc00707f
+#define MATCH_TH_VWSUBUVV 0xc8002057
+#define MASK_TH_VWSUBUVV 0xfc00707f
+#define MATCH_TH_VWSUBUVX 0xc8006057
+#define MASK_TH_VWSUBUVX 0xfc00707f
+#define MATCH_TH_VWADDUWV 0xd0002057
+#define MASK_TH_VWADDUWV 0xfc00707f
+#define MATCH_TH_VWADDUWX 0xd0006057
+#define MASK_TH_VWADDUWX 0xfc00707f
+#define MATCH_TH_VWSUBUWV 0xd8002057
+#define MASK_TH_VWSUBUWV 0xfc00707f
+#define MATCH_TH_VWSUBUWX 0xd8006057
+#define MASK_TH_VWSUBUWX 0xfc00707f
+#define MATCH_TH_VADCVVM 0x42000057
+#define MASK_TH_VADCVVM 0xfe00707f
+#define MATCH_TH_VADCVXM 0x42004057
+#define MASK_TH_VADCVXM 0xfe00707f
+#define MATCH_TH_VADCVIM 0x42003057
+#define MASK_TH_VADCVIM 0xfe00707f
+#define MATCH_TH_VMADCVVM 0x46000057
+#define MASK_TH_VMADCVVM 0xfe00707f
+#define MATCH_TH_VMADCVXM 0x46004057
+#define MASK_TH_VMADCVXM 0xfe00707f
+#define MATCH_TH_VMADCVIM 0x46003057
+#define MASK_TH_VMADCVIM 0xfe00707f
+#define MATCH_TH_VSBCVVM 0x4a000057
+#define MASK_TH_VSBCVVM 0xfe00707f
+#define MATCH_TH_VSBCVXM 0x4a004057
+#define MASK_TH_VSBCVXM 0xfe00707f
+#define MATCH_TH_VMSBCVVM 0x4e000057
+#define MASK_TH_VMSBCVVM 0xfe00707f
+#define MATCH_TH_VMSBCVXM 0x4e004057
+#define MASK_TH_VMSBCVXM 0xfe00707f
+#define MATCH_TH_VNOTV 0x2c0fb057
+#define MASK_TH_VNOTV 0xfc0ff07f
+#define MATCH_TH_VANDVV 0x24000057
+#define MASK_TH_VANDVV 0xfc00707f
+#define MATCH_TH_VANDVX 0x24004057
+#define MASK_TH_VANDVX 0xfc00707f
+#define MATCH_TH_VANDVI 0x24003057
+#define MASK_TH_VANDVI 0xfc00707f
+#define MATCH_TH_VORVV 0x28000057
+#define MASK_TH_VORVV 0xfc00707f
+#define MATCH_TH_VORVX 0x28004057
+#define MASK_TH_VORVX 0xfc00707f
+#define MATCH_TH_VORVI 0x28003057
+#define MASK_TH_VORVI 0xfc00707f
+#define MATCH_TH_VXORVV 0x2c000057
+#define MASK_TH_VXORVV 0xfc00707f
+#define MATCH_TH_VXORVX 0x2c004057
+#define MASK_TH_VXORVX 0xfc00707f
+#define MATCH_TH_VXORVI 0x2c003057
+#define MASK_TH_VXORVI 0xfc00707f
+#define MATCH_TH_VSLLVV 0x94000057
+#define MASK_TH_VSLLVV 0xfc00707f
+#define MATCH_TH_VSLLVX 0x94004057
+#define MASK_TH_VSLLVX 0xfc00707f
+#define MATCH_TH_VSLLVI 0x94003057
+#define MASK_TH_VSLLVI 0xfc00707f
+#define MATCH_TH_VSRLVV 0xa0000057
+#define MASK_TH_VSRLVV 0xfc00707f
+#define MATCH_TH_VSRLVX 0xa0004057
+#define MASK_TH_VSRLVX 0xfc00707f
+#define MATCH_TH_VSRLVI 0xa0003057
+#define MASK_TH_VSRLVI 0xfc00707f
+#define MATCH_TH_VSRAVV 0xa4000057
+#define MASK_TH_VSRAVV 0xfc00707f
+#define MATCH_TH_VSRAVX 0xa4004057
+#define MASK_TH_VSRAVX 0xfc00707f
+#define MATCH_TH_VSRAVI 0xa4003057
+#define MASK_TH_VSRAVI 0xfc00707f
+#define MATCH_TH_VNSRLVV 0xb0000057
+#define MASK_TH_VNSRLVV 0xfc00707f
+#define MATCH_TH_VNSRLVX 0xb0004057
+#define MASK_TH_VNSRLVX 0xfc00707f
+#define MATCH_TH_VNSRLVI 0xb0003057
+#define MASK_TH_VNSRLVI 0xfc00707f
+#define MATCH_TH_VNSRAVV 0xb4000057
+#define MASK_TH_VNSRAVV 0xfc00707f
+#define MATCH_TH_VNSRAVX 0xb4004057
+#define MASK_TH_VNSRAVX 0xfc00707f
+#define MATCH_TH_VNSRAVI 0xb4003057
+#define MASK_TH_VNSRAVI 0xfc00707f
+#define MATCH_TH_VMSEQVV 0x60000057
+#define MASK_TH_VMSEQVV 0xfc00707f
+#define MATCH_TH_VMSEQVX 0x60004057
+#define MASK_TH_VMSEQVX 0xfc00707f
+#define MATCH_TH_VMSEQVI 0x60003057
+#define MASK_TH_VMSEQVI 0xfc00707f
+#define MATCH_TH_VMSNEVV 0x64000057
+#define MASK_TH_VMSNEVV 0xfc00707f
+#define MATCH_TH_VMSNEVX 0x64004057
+#define MASK_TH_VMSNEVX 0xfc00707f
+#define MATCH_TH_VMSNEVI 0x64003057
+#define MASK_TH_VMSNEVI 0xfc00707f
+#define MATCH_TH_VMSLTVV 0x6c000057
+#define MASK_TH_VMSLTVV 0xfc00707f
+#define MATCH_TH_VMSLTVX 0x6c004057
+#define MASK_TH_VMSLTVX 0xfc00707f
+#define MATCH_TH_VMSLTUVV 0x68000057
+#define MASK_TH_VMSLTUVV 0xfc00707f
+#define MATCH_TH_VMSLTUVX 0x68004057
+#define MASK_TH_VMSLTUVX 0xfc00707f
+#define MATCH_TH_VMSLEVV 0x74000057
+#define MASK_TH_VMSLEVV 0xfc00707f
+#define MATCH_TH_VMSLEVX 0x74004057
+#define MASK_TH_VMSLEVX 0xfc00707f
+#define MATCH_TH_VMSLEVI 0x74003057
+#define MASK_TH_VMSLEVI 0xfc00707f
+#define MATCH_TH_VMSLEUVV 0x70000057
+#define MASK_TH_VMSLEUVV 0xfc00707f
+#define MATCH_TH_VMSLEUVX 0x70004057
+#define MASK_TH_VMSLEUVX 0xfc00707f
+#define MATCH_TH_VMSLEUVI 0x70003057
+#define MASK_TH_VMSLEUVI 0xfc00707f
+#define MATCH_TH_VMSGTVX 0x7c004057
+#define MASK_TH_VMSGTVX 0xfc00707f
+#define MATCH_TH_VMSGTVI 0x7c003057
+#define MASK_TH_VMSGTVI 0xfc00707f
+#define MATCH_TH_VMSGTUVX 0x78004057
+#define MASK_TH_VMSGTUVX 0xfc00707f
+#define MATCH_TH_VMSGTUVI 0x78003057
+#define MASK_TH_VMSGTUVI 0xfc00707f
+#define MATCH_TH_VMINVV 0x14000057
+#define MASK_TH_VMINVV 0xfc00707f
+#define MATCH_TH_VMINVX 0x14004057
+#define MASK_TH_VMINVX 0xfc00707f
+#define MATCH_TH_VMAXVV 0x1c000057
+#define MASK_TH_VMAXVV 0xfc00707f
+#define MATCH_TH_VMAXVX 0x1c004057
+#define MASK_TH_VMAXVX 0xfc00707f
+#define MATCH_TH_VMINUVV 0x10000057
+#define MASK_TH_VMINUVV 0xfc00707f
+#define MATCH_TH_VMINUVX 0x10004057
+#define MASK_TH_VMINUVX 0xfc00707f
+#define MATCH_TH_VMAXUVV 0x18000057
+#define MASK_TH_VMAXUVV 0xfc00707f
+#define MATCH_TH_VMAXUVX 0x18004057
+#define MASK_TH_VMAXUVX 0xfc00707f
+#define MATCH_TH_VMULVV 0x94002057
+#define MASK_TH_VMULVV 0xfc00707f
+#define MATCH_TH_VMULVX 0x94006057
+#define MASK_TH_VMULVX 0xfc00707f
+#define MATCH_TH_VMULHVV 0x9c002057
+#define MASK_TH_VMULHVV 0xfc00707f
+#define MATCH_TH_VMULHVX 0x9c006057
+#define MASK_TH_VMULHVX 0xfc00707f
+#define MATCH_TH_VMULHUVV 0x90002057
+#define MASK_TH_VMULHUVV 0xfc00707f
+#define MATCH_TH_VMULHUVX 0x90006057
+#define MASK_TH_VMULHUVX 0xfc00707f
+#define MATCH_TH_VMULHSUVV 0x98002057
+#define MASK_TH_VMULHSUVV 0xfc00707f
+#define MATCH_TH_VMULHSUVX 0x98006057
+#define MASK_TH_VMULHSUVX 0xfc00707f
+#define MATCH_TH_VWMULVV 0xec002057
+#define MASK_TH_VWMULVV 0xfc00707f
+#define MATCH_TH_VWMULVX 0xec006057
+#define MASK_TH_VWMULVX 0xfc00707f
+#define MATCH_TH_VWMULUVV 0xe0002057
+#define MASK_TH_VWMULUVV 0xfc00707f
+#define MATCH_TH_VWMULUVX 0xe0006057
+#define MASK_TH_VWMULUVX 0xfc00707f
+#define MATCH_TH_VWMULSUVV 0xe8002057
+#define MASK_TH_VWMULSUVV 0xfc00707f
+#define MATCH_TH_VWMULSUVX 0xe8006057
+#define MASK_TH_VWMULSUVX 0xfc00707f
+#define MATCH_TH_VMACCVV 0xb4002057
+#define MASK_TH_VMACCVV 0xfc00707f
+#define MATCH_TH_VMACCVX 0xb4006057
+#define MASK_TH_VMACCVX 0xfc00707f
+#define MATCH_TH_VNMSACVV 0xbc002057
+#define MASK_TH_VNMSACVV 0xfc00707f
+#define MATCH_TH_VNMSACVX 0xbc006057
+#define MASK_TH_VNMSACVX 0xfc00707f
+#define MATCH_TH_VMADDVV 0xa4002057
+#define MASK_TH_VMADDVV 0xfc00707f
+#define MATCH_TH_VMADDVX 0xa4006057
+#define MASK_TH_VMADDVX 0xfc00707f
+#define MATCH_TH_VNMSUBVV 0xac002057
+#define MASK_TH_VNMSUBVV 0xfc00707f
+#define MATCH_TH_VNMSUBVX 0xac006057
+#define MASK_TH_VNMSUBVX 0xfc00707f
+#define MATCH_TH_VWMACCUVV 0xf0002057
+#define MASK_TH_VWMACCUVV 0xfc00707f
+#define MATCH_TH_VWMACCUVX 0xf0006057
+#define MASK_TH_VWMACCUVX 0xfc00707f
+#define MATCH_TH_VWMACCVV 0xf4002057
+#define MASK_TH_VWMACCVV 0xfc00707f
+#define MATCH_TH_VWMACCVX 0xf4006057
+#define MASK_TH_VWMACCVX 0xfc00707f
+#define MATCH_TH_VWMACCSUVV 0xf8002057
+#define MASK_TH_VWMACCSUVV 0xfc00707f
+#define MATCH_TH_VWMACCSUVX 0xf8006057
+#define MASK_TH_VWMACCSUVX 0xfc00707f
+#define MATCH_TH_VWMACCUSVX 0xfc006057
+#define MASK_TH_VWMACCUSVX 0xfc00707f
+#define MATCH_TH_VDIVVV 0x84002057
+#define MASK_TH_VDIVVV 0xfc00707f
+#define MATCH_TH_VDIVVX 0x84006057
+#define MASK_TH_VDIVVX 0xfc00707f
+#define MATCH_TH_VDIVUVV 0x80002057
+#define MASK_TH_VDIVUVV 0xfc00707f
+#define MATCH_TH_VDIVUVX 0x80006057
+#define MASK_TH_VDIVUVX 0xfc00707f
+#define MATCH_TH_VREMVV 0x8c002057
+#define MASK_TH_VREMVV 0xfc00707f
+#define MATCH_TH_VREMVX 0x8c006057
+#define MASK_TH_VREMVX 0xfc00707f
+#define MATCH_TH_VREMUVV 0x88002057
+#define MASK_TH_VREMUVV 0xfc00707f
+#define MATCH_TH_VREMUVX 0x88006057
+#define MASK_TH_VREMUVX 0xfc00707f
+#define MATCH_TH_VMERGEVVM 0x5c000057
+#define MASK_TH_VMERGEVVM 0xfe00707f
+#define MATCH_TH_VMERGEVXM 0x5c004057
+#define MASK_TH_VMERGEVXM 0xfe00707f
+#define MATCH_TH_VMERGEVIM 0x5c003057
+#define MASK_TH_VMERGEVIM 0xfe00707f
+#define MATCH_TH_VMVVV 0x5e000057
+#define MASK_TH_VMVVV 0xfff0707f
+#define MATCH_TH_VMVVX 0x5e004057
+#define MASK_TH_VMVVX 0xfff0707f
+#define MATCH_TH_VMVVI 0x5e003057
+#define MASK_TH_VMVVI 0xfff0707f
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
#define MATCH_VT_MASKC 0x607b
#define MASK_VT_MASKC 0xfe00707f
@@ -2579,6 +2579,149 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.vamominud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF},
{"th.vamomaxuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF},
{"th.vamomaxud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF},
+{"th.vadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VADDVV, MASK_TH_VADDVV, match_opcode, 0 },
+{"th.vadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VADDVX, MASK_TH_VADDVX, match_opcode, 0 },
+{"th.vadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VADDVI, MASK_TH_VADDVI, match_opcode, 0 },
+{"th.vsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSUBVV, MASK_TH_VSUBVV, match_opcode, 0 },
+{"th.vsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSUBVX, MASK_TH_VSUBVX, match_opcode, 0 },
+{"th.vrsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VRSUBVX, MASK_TH_VRSUBVX, match_opcode, 0 },
+{"th.vrsub.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VRSUBVI, MASK_TH_VRSUBVI, match_opcode, 0 },
+{"th.vwcvt.x.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VWCVTXXV, MASK_TH_VWCVTXXV, match_opcode, INSN_ALIAS },
+{"th.vwcvtu.x.x.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VWCVTUXXV, MASK_TH_VWCVTUXXV, match_opcode, INSN_ALIAS },
+{"th.vwaddu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWADDUVV, MASK_TH_VWADDUVV, match_opcode, 0 },
+{"th.vwaddu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWADDUVX, MASK_TH_VWADDUVX, match_opcode, 0 },
+{"th.vwsubu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWSUBUVV, MASK_TH_VWSUBUVV, match_opcode, 0 },
+{"th.vwsubu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWSUBUVX, MASK_TH_VWSUBUVX, match_opcode, 0 },
+{"th.vwadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWADDVV, MASK_TH_VWADDVV, match_opcode, 0 },
+{"th.vwadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWADDVX, MASK_TH_VWADDVX, match_opcode, 0 },
+{"th.vwsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWSUBVV, MASK_TH_VWSUBVV, match_opcode, 0 },
+{"th.vwsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWSUBVX, MASK_TH_VWSUBVX, match_opcode, 0 },
+{"th.vwaddu.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWADDUWV, MASK_TH_VWADDUWV, match_opcode, 0 },
+{"th.vwaddu.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWADDUWX, MASK_TH_VWADDUWX, match_opcode, 0 },
+{"th.vwsubu.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWSUBUWV, MASK_TH_VWSUBUWV, match_opcode, 0 },
+{"th.vwsubu.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWSUBUWX, MASK_TH_VWSUBUWX, match_opcode, 0 },
+{"th.vwadd.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWADDWV, MASK_TH_VWADDWV, match_opcode, 0 },
+{"th.vwadd.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWADDWX, MASK_TH_VWADDWX, match_opcode, 0 },
+{"th.vwsub.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWSUBWV, MASK_TH_VWSUBWV, match_opcode, 0 },
+{"th.vwsub.wx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWSUBWX, MASK_TH_VWSUBWX, match_opcode, 0 },
+{"th.vadc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VADCVVM, MASK_TH_VADCVVM, match_opcode, 0 },
+{"th.vadc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VADCVXM, MASK_TH_VADCVXM, match_opcode, 0 },
+{"th.vadc.vim", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vi,V0", MATCH_TH_VADCVIM, MASK_TH_VADCVIM, match_opcode, 0 },
+{"th.vmadc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VMADCVVM, MASK_TH_VMADCVVM, match_opcode, 0 },
+{"th.vmadc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VMADCVXM, MASK_TH_VMADCVXM, match_opcode, 0 },
+{"th.vmadc.vim", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vi,V0", MATCH_TH_VMADCVIM, MASK_TH_VMADCVIM, match_opcode, 0 },
+{"th.vsbc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VSBCVVM, MASK_TH_VSBCVVM, match_opcode, 0 },
+{"th.vsbc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VSBCVXM, MASK_TH_VSBCVXM, match_opcode, 0 },
+{"th.vmsbc.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VMSBCVVM, MASK_TH_VMSBCVVM, match_opcode, 0 },
+{"th.vmsbc.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VMSBCVXM, MASK_TH_VMSBCVXM, match_opcode, 0 },
+{"th.vnot.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VNOTV, MASK_TH_VNOTV, match_opcode, INSN_ALIAS },
+{"th.vand.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VANDVV, MASK_TH_VANDVV, match_opcode, 0 },
+{"th.vand.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VANDVX, MASK_TH_VANDVX, match_opcode, 0 },
+{"th.vand.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VANDVI, MASK_TH_VANDVI, match_opcode, 0 },
+{"th.vor.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VORVV, MASK_TH_VORVV, match_opcode, 0 },
+{"th.vor.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VORVX, MASK_TH_VORVX, match_opcode, 0 },
+{"th.vor.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VORVI, MASK_TH_VORVI, match_opcode, 0 },
+{"th.vxor.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VXORVV, MASK_TH_VXORVV, match_opcode, 0 },
+{"th.vxor.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VXORVX, MASK_TH_VXORVX, match_opcode, 0 },
+{"th.vxor.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VXORVI, MASK_TH_VXORVI, match_opcode, 0 },
+{"th.vsll.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSLLVV, MASK_TH_VSLLVV, match_opcode, 0 },
+{"th.vsll.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSLLVX, MASK_TH_VSLLVX, match_opcode, 0 },
+{"th.vsll.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSLLVI, MASK_TH_VSLLVI, match_opcode, 0 },
+{"th.vsrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSRLVV, MASK_TH_VSRLVV, match_opcode, 0 },
+{"th.vsrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSRLVX, MASK_TH_VSRLVX, match_opcode, 0 },
+{"th.vsrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSRLVI, MASK_TH_VSRLVI, match_opcode, 0 },
+{"th.vsra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSRAVV, MASK_TH_VSRAVV, match_opcode, 0 },
+{"th.vsra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSRAVX, MASK_TH_VSRAVX, match_opcode, 0 },
+{"th.vsra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSRAVI, MASK_TH_VSRAVI, match_opcode, 0 },
+{"th.vnsrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNSRLVV, MASK_TH_VNSRLVV, match_opcode, 0 },
+{"th.vnsrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNSRLVX, MASK_TH_VNSRLVX, match_opcode, 0 },
+{"th.vnsrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNSRLVI, MASK_TH_VNSRLVI, match_opcode, 0 },
+{"th.vnsra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNSRAVV, MASK_TH_VNSRAVV, match_opcode, 0 },
+{"th.vnsra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNSRAVX, MASK_TH_VNSRAVX, match_opcode, 0 },
+{"th.vnsra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNSRAVI, MASK_TH_VNSRAVI, match_opcode, 0 },
+{"th.vmseq.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSEQVV, MASK_TH_VMSEQVV, match_opcode, 0 },
+{"th.vmseq.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSEQVX, MASK_TH_VMSEQVX, match_opcode, 0 },
+{"th.vmseq.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSEQVI, MASK_TH_VMSEQVI, match_opcode, 0 },
+{"th.vmsne.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSNEVV, MASK_TH_VMSNEVV, match_opcode, 0 },
+{"th.vmsne.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSNEVX, MASK_TH_VMSNEVX, match_opcode, 0 },
+{"th.vmsne.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSNEVI, MASK_TH_VMSNEVI, match_opcode, 0 },
+{"th.vmsltu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSLTUVV, MASK_TH_VMSLTUVV, match_opcode, 0 },
+{"th.vmsltu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSLTUVX, MASK_TH_VMSLTUVX, match_opcode, 0 },
+{"th.vmslt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSLTVV, MASK_TH_VMSLTVV, match_opcode, 0 },
+{"th.vmslt.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSLTVX, MASK_TH_VMSLTVX, match_opcode, 0 },
+{"th.vmsleu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSLEUVV, MASK_TH_VMSLEUVV, match_opcode, 0 },
+{"th.vmsleu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSLEUVX, MASK_TH_VMSLEUVX, match_opcode, 0 },
+{"th.vmsleu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSLEUVI, MASK_TH_VMSLEUVI, match_opcode, 0 },
+{"th.vmsle.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMSLEVV, MASK_TH_VMSLEVV, match_opcode, 0 },
+{"th.vmsle.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSLEVX, MASK_TH_VMSLEVX, match_opcode, 0 },
+{"th.vmsle.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSLEVI, MASK_TH_VMSLEVI, match_opcode, 0 },
+{"th.vmsgtu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSGTUVX, MASK_TH_VMSGTUVX, match_opcode, 0 },
+{"th.vmsgtu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSGTUVI, MASK_TH_VMSGTUVI, match_opcode, 0 },
+{"th.vmsgt.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMSGTVX, MASK_TH_VMSGTVX, match_opcode, 0 },
+{"th.vmsgt.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VMSGTVI, MASK_TH_VMSGTVI, match_opcode, 0 },
+{"th.vmsgt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMSLTVV, MASK_TH_VMSLTVV, match_opcode, INSN_ALIAS },
+{"th.vmsgtu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMSLTUVV, MASK_TH_VMSLTUVV, match_opcode, INSN_ALIAS },
+{"th.vmsge.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMSLEVV, MASK_TH_VMSLEVV, match_opcode, INSN_ALIAS },
+{"th.vmsgeu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMSLEUVV, MASK_TH_VMSLEUVV, match_opcode, INSN_ALIAS },
+{"th.vmslt.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_TH_VMSLEVI, MASK_TH_VMSLEVI, match_opcode, INSN_ALIAS },
+{"th.vmsltu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_TH_VMSLEUVI, MASK_TH_VMSLEUVI, match_opcode, INSN_ALIAS },
+{"th.vmsge.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_TH_VMSGTVI, MASK_TH_VMSGTVI, match_opcode, INSN_ALIAS },
+{"th.vmsgeu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VkVm", MATCH_TH_VMSGTUVI, MASK_TH_VMSGTUVI, match_opcode, INSN_ALIAS },
+{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 0, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsge.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 0, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", 1, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vmsgeu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,VM,VT", 1, (int) M_VMSGE, match_never, INSN_MACRO },
+{"th.vminu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMINUVV, MASK_TH_VMINUVV, match_opcode, 0},
+{"th.vminu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMINUVX, MASK_TH_VMINUVX, match_opcode, 0},
+{"th.vmin.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMINVV, MASK_TH_VMINVV, match_opcode, 0},
+{"th.vmin.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMINVX, MASK_TH_VMINVX, match_opcode, 0},
+{"th.vmaxu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMAXUVV, MASK_TH_VMAXUVV, match_opcode, 0},
+{"th.vmaxu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMAXUVX, MASK_TH_VMAXUVX, match_opcode, 0},
+{"th.vmax.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMAXVV, MASK_TH_VMAXVV, match_opcode, 0},
+{"th.vmax.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMAXVX, MASK_TH_VMAXVX, match_opcode, 0},
+{"th.vmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMULVV, MASK_TH_VMULVV, match_opcode, 0 },
+{"th.vmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMULVX, MASK_TH_VMULVX, match_opcode, 0 },
+{"th.vmulh.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMULHVV, MASK_TH_VMULHVV, match_opcode, 0 },
+{"th.vmulh.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMULHVX, MASK_TH_VMULHVX, match_opcode, 0 },
+{"th.vmulhu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMULHUVV, MASK_TH_VMULHUVV, match_opcode, 0 },
+{"th.vmulhu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMULHUVX, MASK_TH_VMULHUVX, match_opcode, 0 },
+{"th.vmulhsu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMULHSUVV, MASK_TH_VMULHSUVV, match_opcode, 0 },
+{"th.vmulhsu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VMULHSUVX, MASK_TH_VMULHSUVX, match_opcode, 0 },
+{"th.vwmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWMULVV, MASK_TH_VWMULVV, match_opcode, 0 },
+{"th.vwmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWMULVX, MASK_TH_VWMULVX, match_opcode, 0 },
+{"th.vwmulu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWMULUVV, MASK_TH_VWMULUVV, match_opcode, 0 },
+{"th.vwmulu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWMULUVX, MASK_TH_VWMULUVX, match_opcode, 0 },
+{"th.vwmulsu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWMULSUVV, MASK_TH_VWMULSUVV, match_opcode, 0 },
+{"th.vwmulsu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VWMULSUVX, MASK_TH_VWMULSUVX, match_opcode, 0 },
+{"th.vmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMACCVV, MASK_TH_VMACCVV, match_opcode, 0},
+{"th.vmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VMACCVX, MASK_TH_VMACCVX, match_opcode, 0},
+{"th.vnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VNMSACVV, MASK_TH_VNMSACVV, match_opcode, 0},
+{"th.vnmsac.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VNMSACVX, MASK_TH_VNMSACVX, match_opcode, 0},
+{"th.vmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMADDVV, MASK_TH_VMADDVV, match_opcode, 0},
+{"th.vmadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VMADDVX, MASK_TH_VMADDVX, match_opcode, 0},
+{"th.vnmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VNMSUBVV, MASK_TH_VNMSUBVV, match_opcode, 0},
+{"th.vnmsub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VNMSUBVX, MASK_TH_VNMSUBVX, match_opcode, 0},
+{"th.vwmaccu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWMACCUVV, MASK_TH_VWMACCUVV, match_opcode, 0},
+{"th.vwmaccu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWMACCUVX, MASK_TH_VWMACCUVX, match_opcode, 0},
+{"th.vwmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWMACCVV, MASK_TH_VWMACCVV, match_opcode, 0},
+{"th.vwmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWMACCVX, MASK_TH_VWMACCVX, match_opcode, 0},
+{"th.vwmaccsu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWMACCSUVV, MASK_TH_VWMACCSUVV, match_opcode, 0},
+{"th.vwmaccsu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWMACCSUVX, MASK_TH_VWMACCSUVX, match_opcode, 0},
+{"th.vwmaccus.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWMACCUSVX, MASK_TH_VWMACCUSVX, match_opcode, 0},
+{"th.vdivu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VDIVUVV, MASK_TH_VDIVUVV, match_opcode, 0 },
+{"th.vdivu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VDIVUVX, MASK_TH_VDIVUVX, match_opcode, 0 },
+{"th.vdiv.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VDIVVV, MASK_TH_VDIVVV, match_opcode, 0 },
+{"th.vdiv.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VDIVVX, MASK_TH_VDIVVX, match_opcode, 0 },
+{"th.vremu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREMUVV, MASK_TH_VREMUVV, match_opcode, 0 },
+{"th.vremu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VREMUVX, MASK_TH_VREMUVX, match_opcode, 0 },
+{"th.vrem.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREMVV, MASK_TH_VREMVV, match_opcode, 0 },
+{"th.vrem.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VREMVX, MASK_TH_VREMVX, match_opcode, 0 },
+{"th.vmerge.vvm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs,V0", MATCH_TH_VMERGEVVM, MASK_TH_VMERGEVVM, match_opcode, 0 },
+{"th.vmerge.vxm", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,s,V0", MATCH_TH_VMERGEVXM, MASK_TH_VMERGEVXM, match_opcode, 0 },
+{"th.vmerge.vim", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vi,V0", MATCH_TH_VMERGEVIM, MASK_TH_VMERGEVIM, match_opcode, 0 },
+{"th.vmv.v.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs", MATCH_TH_VMVVV, MASK_TH_VMVVV, match_opcode, 0 },
+{"th.vmv.v.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVVX, MASK_TH_VMVVX, match_opcode, 0 },
+{"th.vmv.v.i", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vi", MATCH_TH_VMVVI, MASK_TH_VMVVI, match_opcode, 0 },
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },