diff mbox series

[3/3] aarch64: Add LSE128 instructions

Message ID 20231106131301.2576862-4-victor.donascimento@arm.com
State Committed
Headers
Series aarch64: Add support for the Armv9.4-a LSE128 extension |

Checks

Context Check Description
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linaro-tcwg-bot/tcwg_binutils_check--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_binutils_build--master-aarch64 success Testing passed

Commit Message

Victor Do Nascimento Nov. 6, 2023, 1:12 p.m. UTC 
  Implement, together with the necessary tests, the following new LSE128
atomic instructions:

  * Atomic bit clear on quadword in memory (ldclrp{a|l|al});
  * Atomic bit set on quadword in memory (ldsetp{a|l|al});
  * Swap quadword in memory (swpp{a|l|al});

gas/ChangeLog:

	* testsuite/gas/aarch64/lse128-atomic.d: New.
	* testsuite/gas/aarch64/lse128-atomic.s: Likewise.

opcodes/ChangeLog:

	* aarch64-tbl.h (ldclrp): new _LSE128_INSN entry.
	(ldclrpa):  Likewise.
	(ldclrpal): Likewise.
	(ldclrpl): Likewise.
	(ldsetp): Likewise.
	(ldsetpa): Likewise.
	(ldsetpal): Likewise.
	(ldsetpl): Likewise.
	(swpp): Likewise.
	(swppa): Likewise.
	(swppal): Likewise.
	(swppl): Likewise.
---
 gas/testsuite/gas/aarch64/lse128-atomic.d | 32 ++++++++++++++++++++++
 gas/testsuite/gas/aarch64/lse128-atomic.s | 33 +++++++++++++++++++++++
 opcodes/aarch64-tbl.h                     | 13 +++++++++
 3 files changed, 78 insertions(+)
 create mode 100644 gas/testsuite/gas/aarch64/lse128-atomic.d
 create mode 100644 gas/testsuite/gas/aarch64/lse128-atomic.s
diff mbox series

Patch

diff --git a/gas/testsuite/gas/aarch64/lse128-atomic.d b/gas/testsuite/gas/aarch64/lse128-atomic.d
new file mode 100644
index 00000000000..bea83fe3642
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lse128-atomic.d
@@ -0,0 +1,32 @@ 
+#objdump: -dr
+#as:-march=armv9-a+lse128
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+   0:	19211040 	ldclrp	x0, x1, \[x2\]
+   4:	192313e2 	ldclrp	x2, x3, \[sp\]
+   8:	19a11040 	ldclrpa	x0, x1, \[x2\]
+   c:	19a313e2 	ldclrpa	x2, x3, \[sp\]
+  10:	19e11040 	ldclrpal	x0, x1, \[x2\]
+  14:	19e313e2 	ldclrpal	x2, x3, \[sp\]
+  18:	19611040 	ldclrpl	x0, x1, \[x2\]
+  1c:	196313e2 	ldclrpl	x2, x3, \[sp\]
+  20:	19213040 	ldsetp	x0, x1, \[x2\]
+  24:	192333e2 	ldsetp	x2, x3, \[sp\]
+  28:	19a13040 	ldsetpa	x0, x1, \[x2\]
+  2c:	19a333e2 	ldsetpa	x2, x3, \[sp\]
+  30:	19e13040 	ldsetpal	x0, x1, \[x2\]
+  34:	19e333e2 	ldsetpal	x2, x3, \[sp\]
+  38:	19613040 	ldsetpl	x0, x1, \[x2\]
+  3c:	196333e2 	ldsetpl	x2, x3, \[sp\]
+  40:	19218040 	swpp	x0, x1, \[x2\]
+  44:	192383e2 	swpp	x2, x3, \[sp\]
+  48:	19a18040 	swppa	x0, x1, \[x2\]
+  4c:	19a383e2 	swppa	x2, x3, \[sp\]
+  50:	19e18040 	swppal	x0, x1, \[x2\]
+  54:	19e383e2 	swppal	x2, x3, \[sp\]
+  58:	19618040 	swppl	x0, x1, \[x2\]
+  5c:	196383e2 	swppl	x2, x3, \[sp\]
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/lse128-atomic.s b/gas/testsuite/gas/aarch64/lse128-atomic.s
new file mode 100644
index 00000000000..802f1b76fc7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lse128-atomic.s
@@ -0,0 +1,33 @@ 
+/* lse128-atomic.s Test file For AArch64 LSE128 atomic instructions
+   encoding.
+
+   Copyright (C) 2014-2023 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the license, or
+   (at your option) any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+	.macro format_0 op
+	.irp suffix, , a, al, l
+		\op\suffix x0, x1, [x2]
+		\op\suffix x2, x3, [sp]
+	.endr
+	.endm
+
+func:
+	format_0 ldclrp
+	format_0 ldsetp
+	format_0 swpp
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 58787fbc4a9..74fd6695d81 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4101,6 +4101,19 @@  const struct aarch64_opcode aarch64_opcode_table[] =
   _LSE_INSN ("stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS),
   _LSE_INSN ("stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS),
   _LSE_INSN ("stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS),
+  /* LSE128 extension (atomic).  */
+  _LSE128_INSN ("ldclrp", 0x19201000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("ldclrpa", 0x19a01000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("ldclrpal", 0x19e01000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("ldclrpl", 0x19601000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("ldsetp", 0x19203000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("ldsetpa", 0x19a03000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("ldsetpal", 0x19e03000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("ldsetpl", 0x19603000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("swpp", 0x19208000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("swppa", 0x19a08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("swppal", 0x19e08000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
+  _LSE128_INSN ("swppl", 0x19608000, 0xffe0fc00, lse128_atomic, OP3 (LSE128_Rt, LSE128_Rt2, ADDR_SIMPLE), QL_X2NIL, 0),
   /* Move wide (immediate).  */
   CORE_INSN ("movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS),
   CORE_INSN ("mov",  0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV),