@@ -651,10 +651,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 122:
case 123:
case 124:
- case 182:
+ case 125:
case 183:
case 184:
case 185:
@@ -668,30 +667,31 @@ aarch64_insert_operand (const aarch64_operand *self,
case 193:
case 194:
case 195:
- case 210:
+ case 196:
case 211:
case 212:
case 213:
- case 222:
+ case 214:
case 223:
case 224:
case 225:
case 226:
- case 237:
- case 241:
- case 245:
- case 252:
- case 253:
- case 260:
- case 261:
+ case 227:
+ case 239:
+ case 243:
+ case 247:
+ case 254:
+ case 255:
case 262:
case 263:
+ case 264:
+ case 265:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
- case 118:
case 119:
- case 295:
+ case 120:
case 297:
+ case 299:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -705,18 +705,17 @@ aarch64_insert_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
- case 299:
- return aarch64_ins_reglane (self, info, code, inst, errors);
case 39:
+ case 301:
+ return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
- case 227:
+ case 42:
case 228:
- case 231:
- case 264:
- case 265:
- case 280:
- case 281:
+ case 229:
+ case 232:
+ case 266:
+ case 267:
case 282:
case 283:
case 284:
@@ -728,22 +727,23 @@ aarch64_insert_operand (const aarch64_operand *self,
case 290:
case 291:
case 292:
+ case 293:
+ case 294:
return aarch64_ins_simple_index (self, info, code, inst, errors);
- case 42:
- return aarch64_ins_reglist (self, info, code, inst, errors);
case 43:
- return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
+ return aarch64_ins_reglist (self, info, code, inst, errors);
case 44:
- return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
+ return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
case 45:
- return aarch64_ins_lut_reglist (self, info, code, inst, errors);
+ return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
case 46:
- return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
+ return aarch64_ins_lut_reglist (self, info, code, inst, errors);
case 47:
+ return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
case 48:
case 49:
case 50:
- case 60:
+ case 51:
case 61:
case 62:
case 63:
@@ -760,15 +760,15 @@ aarch64_insert_operand (const aarch64_operand *self,
case 74:
case 75:
case 76:
- case 88:
+ case 77:
case 89:
case 90:
case 91:
- case 117:
- case 121:
- case 179:
- case 181:
- case 202:
+ case 92:
+ case 118:
+ case 122:
+ case 180:
+ case 182:
case 203:
case 204:
case 205:
@@ -776,102 +776,102 @@ aarch64_insert_operand (const aarch64_operand *self,
case 207:
case 208:
case 209:
- case 266:
- case 293:
- case 294:
+ case 210:
+ case 268:
+ case 295:
case 296:
case 298:
- case 303:
- case 304:
+ case 300:
+ case 305:
+ case 306:
return aarch64_ins_imm (self, info, code, inst, errors);
- case 51:
case 52:
- return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
case 53:
+ return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
case 54:
case 55:
+ case 56:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
- case 59:
- case 169:
+ case 60:
+ case 170:
return aarch64_ins_fpimm (self, info, code, inst, errors);
- case 77:
- case 177:
- return aarch64_ins_limm (self, info, code, inst, errors);
case 78:
- return aarch64_ins_aimm (self, info, code, inst, errors);
+ case 178:
+ return aarch64_ins_limm (self, info, code, inst, errors);
case 79:
- return aarch64_ins_imm_half (self, info, code, inst, errors);
+ return aarch64_ins_aimm (self, info, code, inst, errors);
case 80:
+ return aarch64_ins_imm_half (self, info, code, inst, errors);
+ case 81:
return aarch64_ins_fbits (self, info, code, inst, errors);
- case 82:
case 83:
- case 174:
- return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 84:
- case 173:
case 175:
- return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
+ return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 85:
+ case 174:
+ case 176:
+ return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 86:
+ case 87:
return aarch64_ins_cond (self, info, code, inst, errors);
- case 92:
- case 101:
- return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 93:
- return aarch64_ins_addr_regoff (self, info, code, inst, errors);
+ case 102:
+ return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 94:
+ return aarch64_ins_addr_regoff (self, info, code, inst, errors);
case 95:
case 96:
- case 98:
- case 100:
- return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 97:
- return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
case 99:
+ case 101:
+ return aarch64_ins_addr_simm (self, info, code, inst, errors);
+ case 98:
+ return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
+ case 100:
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
- case 102:
- return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 103:
- return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
+ return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 104:
+ return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
case 105:
- return aarch64_ins_sysreg (self, info, code, inst, errors);
case 106:
- return aarch64_ins_pstatefield (self, info, code, inst, errors);
+ return aarch64_ins_sysreg (self, info, code, inst, errors);
case 107:
+ return aarch64_ins_pstatefield (self, info, code, inst, errors);
case 108:
case 109:
case 110:
case 111:
case 112:
- return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 113:
- case 115:
- return aarch64_ins_barrier (self, info, code, inst, errors);
+ return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 114:
- return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
case 116:
+ return aarch64_ins_barrier (self, info, code, inst, errors);
+ case 115:
+ return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
+ case 117:
return aarch64_ins_prfop (self, info, code, inst, errors);
- case 120:
+ case 121:
return aarch64_ins_hint (self, info, code, inst, errors);
- case 125:
case 126:
- return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 127:
+ return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 128:
case 129:
case 130:
- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 131:
- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 132:
- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 133:
+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 134:
case 135:
case 136:
- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 137:
+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 138:
case 139:
case 140:
@@ -886,8 +886,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 149:
case 150:
case 151:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 152:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 153:
case 154:
case 155:
@@ -895,116 +895,118 @@ aarch64_insert_operand (const aarch64_operand *self,
case 157:
case 158:
case 159:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 160:
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 161:
case 162:
case 163:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 164:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 165:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 166:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 167:
- return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 168:
+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ case 169:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
- case 170:
- return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 171:
- return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 172:
+ return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ case 173:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 176:
+ case 177:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 178:
+ case 179:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 180:
+ case 181:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 196:
case 197:
case 198:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 199:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 200:
case 201:
- case 279:
+ case 202:
+ case 281:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 214:
case 215:
case 216:
case 217:
- return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
case 218:
+ return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
case 219:
case 220:
case 221:
+ case 222:
return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
- case 229:
case 230:
- case 232:
+ case 231:
case 233:
case 234:
case 235:
case 236:
- return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 237:
case 238:
+ return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 240:
return aarch64_ins_sve_index_imm (self, info, code, inst, errors);
- case 239:
+ case 241:
return aarch64_ins_sve_index (self, info, code, inst, errors);
- case 240:
case 242:
- case 259:
- case 305:
- case 306:
+ case 244:
+ case 261:
case 307:
+ case 308:
+ case 309:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
- case 243:
- case 244:
+ case 245:
case 246:
- case 247:
case 248:
case 249:
- case 258:
- return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 250:
case 251:
+ case 260:
+ return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
+ case 252:
+ case 253:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
- case 254:
case 256:
- case 267:
+ case 258:
+ case 269:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
- case 255:
case 257:
+ case 259:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 268:
- case 269:
case 270:
case 271:
case 272:
case 273:
case 274:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 275:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 276:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 277:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 278:
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ case 279:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 280:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 300:
- case 301:
case 302:
+ case 303:
+ case 304:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 308:
- case 309:
case 310:
case 311:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 312:
+ case 313:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 314:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
@@ -17252,11 +17252,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0001xxxxx010xxxxxxxxxxxxx
- fdot. */
- return 2473;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0001xxxxx0100x0xxxxxxxxxx
+ fdot. */
+ return 2473;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0001xxxxx0100x1xxxxxxxxxx
+ fdot. */
+ return 3413;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0001xxxxx0101xxxxxxxxxxxx
+ fmlalb. */
+ return 3415;
+ }
}
else
{
@@ -17271,21 +17293,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0101xxxxx010xx0xxxxxxxxxx
- fmlalb. */
- return 2146;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx0100x0xxxxxxxxxx
+ fmlalb. */
+ return 2146;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx0100x1xxxxxxxxxx
+ fmlalt. */
+ return 2148;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0101xxxxx010xx1xxxxxxxxxx
+ 011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 2148;
+ return 3425;
}
}
else
@@ -17304,11 +17337,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0011xxxxx010xxxxxxxxxxxxx
- bfdot. */
- return 3066;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0011xxxxx010xx0xxxxxxxxxx
+ bfdot. */
+ return 3066;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0011xxxxx010xx1xxxxxxxxxx
+ fdot. */
+ return 3411;
+ }
}
else
{
@@ -17358,31 +17402,108 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x0001xxxxx1x0xxxxxxxxxxxxx
- fdot. */
- return 2474;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx100000xxxxxxxxxx
+ fdot. */
+ return 2474;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx100010xxxxxxxxxx
+ fmlallbb. */
+ return 3416;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1000x1xxxxxxxxxx
+ fdot. */
+ return 3412;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1100xxxxxxxxxxxx
+ fmlallbb. */
+ return 3417;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1x01xxxxxxxxxxxx
+ fmlallbt. */
+ return 3418;
+ }
}
else
{
if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0101xxxxx1x0xx0xxxxxxxxxx
- fmlalb. */
- return 2147;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx100000xxxxxxxxxx
+ fmlalb. */
+ return 2147;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx100010xxxxxxxxxx
+ fmlalb. */
+ return 3414;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx1000x1xxxxxxxxxx
+ fmlalt. */
+ return 2149;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx1100xxxxxxxxxxxx
+ fmlalltb. */
+ return 3421;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0101xxxxx1x0xx1xxxxxxxxxx
+ 011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 2149;
+ return 3424;
}
}
else
@@ -17399,31 +17520,64 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x0011xxxxx1x0xxxxxxxxxxxxx
- bfdot. */
- return 3065;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0011xxxxx100xx0xxxxxxxxxx
+ bfdot. */
+ return 3065;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0011xxxxx100xx1xxxxxxxxxx
+ fdot. */
+ return 3410;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0011xxxxx110xxxxxxxxxxxxx
+ fmlallbt. */
+ return 3419;
+ }
}
else
{
if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0111xxxxx1x0xx0xxxxxxxxxx
- bfmlalb. */
- return 3071;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0111xxxxx100xx0xxxxxxxxxx
+ bfmlalb. */
+ return 3071;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0111xxxxx100xx1xxxxxxxxxx
+ bfmlalt. */
+ return 3070;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0111xxxxx1x0xx1xxxxxxxxxx
- bfmlalt. */
- return 3070;
+ 011001x0111xxxxx110xxxxxxxxxxxxx
+ fmlalltt. */
+ return 3423;
}
}
else
@@ -17729,32 +17883,54 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 31) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0x01xxxxx101xx0xxxxxxxxxx
- fmlslb. */
- return 2151;
+ x11001x0001xxxxx1010xxxxxxxxxxxx
+ fmlalltb. */
+ return 3420;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0x01xxxxx101xx1xxxxxxxxxx
- fmlslt. */
- return 2153;
+ x11001x0001xxxxx1011xxxxxxxxxxxx
+ fmlalltt. */
+ return 3422;
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 111001x0x01xxxxx101xxxxxxxxxxxxx
- st1h. */
- return 1954;
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx101xx0xxxxxxxxxx
+ fmlslb. */
+ return 2151;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx101xx1xxxxxxxxxx
+ fmlslt. */
+ return 2153;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x0101xxxxx101xxxxxxxxxxxxx
+ st1h. */
+ return 1954;
+ }
}
}
else
@@ -25943,31 +26119,75 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 13) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110x00xxxxxxx0001xxxxxxxxxx
- dup. */
- return 149;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110x00xxxxxx00001xxxxxxxxxx
+ dup. */
+ return 149;
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxx00001xxxxxxxxxx
+ fmaxnm. */
+ return 292;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110110xxxxxx00001xxxxxxxxxx
+ fminnm. */
+ return 308;
+ }
+ }
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110010xxxxxxx0001xxxxxxxxxx
- fmaxnm. */
- return 292;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 00001110x00xxxxxx10001xxxxxxxxxx
+ fmlallbb. */
+ return 3402;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 01001110x00xxxxxx10001xxxxxxxxxx
+ fmlalltb. */
+ return 3404;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110110xxxxxxx0001xxxxxxxxxx
- fminnm. */
- return 308;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 00001110x10xxxxxx10001xxxxxxxxxx
+ fmlallbt. */
+ return 3403;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 01001110x10xxxxxx10001xxxxxxxxxx
+ fmlalltt. */
+ return 3405;
+ }
}
}
}
@@ -26176,37 +26396,81 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110x00xxxxxxx1111xxxxxxxxxx
- umov. */
- return 152;
- }
- else
+ if (((word >> 14) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 0x001110010xxxxxxx1111xxxxxxxxxx
- frecps. */
- return 304;
+ 0x001110x00xxxxxx01111xxxxxxxxxx
+ umov. */
+ return 152;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110110xxxxxxx1111xxxxxxxxxx
- frsqrts. */
- return 316;
- }
- }
- }
- }
- }
- }
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxx01111xxxxxxxxxx
+ frecps. */
+ return 304;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110110xxxxxx01111xxxxxxxxxx
+ frsqrts. */
+ return 316;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110x00xxxxxx11111xxxxxxxxxx
+ fdot. */
+ return 3394;
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxx11111xxxxxxxxxx
+ fdot. */
+ return 3396;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 00001110110xxxxxx11111xxxxxxxxxx
+ fmlalb. */
+ return 3398;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 01001110110xxxxxx11111xxxxxxxxxx
+ fmlalt. */
+ return 3399;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
}
else
{
@@ -31639,21 +31903,65 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0001111xxxxxxxx0000x0xxxxxxxxxx
- fmlal. */
- return 3013;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx00111100xxxxxx0000x0xxxxxxxxxx
+ fdot. */
+ return 3395;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x000111110xxxxxx0000x0xxxxxxxxxx
+ fmlal. */
+ return 3013;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100111110xxxxxx0000x0xxxxxxxxxx
+ fmlal. */
+ return 3017;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1001111xxxxxxxx0000x0xxxxxxxxxx
- fmlal. */
- return 3017;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx00111101xxxxxx0000x0xxxxxxxxxx
+ fdot. */
+ return 3397;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x000111111xxxxxx0000x0xxxxxxxxxx
+ fmlalb. */
+ return 3400;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100111111xxxxxx0000x0xxxxxxxxxx
+ fmlalt. */
+ return 3401;
+ }
+ }
}
}
else
@@ -32183,21 +32491,65 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0101111xxxxxxxx1000x0xxxxxxxxxx
- fmlal2. */
- return 3015;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x010111100xxxxxx1000x0xxxxxxxxxx
+ fmlallbb. */
+ return 3406;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x110111100xxxxxx1000x0xxxxxxxxxx
+ fmlalltb. */
+ return 3408;
+ }
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x010111110xxxxxx1000x0xxxxxxxxxx
+ fmlal2. */
+ return 3015;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x110111110xxxxxx1000x0xxxxxxxxxx
+ fmlal2. */
+ return 3019;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1101111xxxxxxxx1000x0xxxxxxxxxx
- fmlal2. */
- return 3019;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0101111x1xxxxxx1000x0xxxxxxxxxx
+ fmlallbt. */
+ return 3407;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1101111x1xxxxxx1000x0xxxxxxxxxx
+ fmlalltt. */
+ return 3409;
+ }
}
}
}
@@ -33648,10 +34000,9 @@ aarch64_extract_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 122:
case 123:
case 124:
- case 182:
+ case 125:
case 183:
case 184:
case 185:
@@ -33665,30 +34016,31 @@ aarch64_extract_operand (const aarch64_operand *self,
case 193:
case 194:
case 195:
- case 210:
+ case 196:
case 211:
case 212:
case 213:
- case 222:
+ case 214:
case 223:
case 224:
case 225:
case 226:
- case 237:
- case 241:
- case 245:
- case 252:
- case 253:
- case 260:
- case 261:
+ case 227:
+ case 239:
+ case 243:
+ case 247:
+ case 254:
+ case 255:
case 262:
case 263:
+ case 264:
+ case 265:
return aarch64_ext_regno (self, info, code, inst, errors);
case 6:
- case 118:
case 119:
- case 295:
+ case 120:
case 297:
+ case 299:
return aarch64_ext_none (self, info, code, inst, errors);
case 11:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -33707,18 +34059,17 @@ aarch64_extract_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
- case 299:
- return aarch64_ext_reglane (self, info, code, inst, errors);
case 39:
+ case 301:
+ return aarch64_ext_reglane (self, info, code, inst, errors);
case 40:
case 41:
- case 227:
+ case 42:
case 228:
- case 231:
- case 264:
- case 265:
- case 280:
- case 281:
+ case 229:
+ case 232:
+ case 266:
+ case 267:
case 282:
case 283:
case 284:
@@ -33730,22 +34081,23 @@ aarch64_extract_operand (const aarch64_operand *self,
case 290:
case 291:
case 292:
+ case 293:
+ case 294:
return aarch64_ext_simple_index (self, info, code, inst, errors);
- case 42:
- return aarch64_ext_reglist (self, info, code, inst, errors);
case 43:
- return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
+ return aarch64_ext_reglist (self, info, code, inst, errors);
case 44:
- return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
+ return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
case 45:
- return aarch64_ext_lut_reglist (self, info, code, inst, errors);
+ return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
case 46:
- return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
+ return aarch64_ext_lut_reglist (self, info, code, inst, errors);
case 47:
+ return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
case 48:
case 49:
case 50:
- case 60:
+ case 51:
case 61:
case 62:
case 63:
@@ -33762,16 +34114,16 @@ aarch64_extract_operand (const aarch64_operand *self,
case 74:
case 75:
case 76:
- case 87:
+ case 77:
case 88:
case 89:
case 90:
case 91:
- case 117:
- case 121:
- case 179:
- case 181:
- case 202:
+ case 92:
+ case 118:
+ case 122:
+ case 180:
+ case 182:
case 203:
case 204:
case 205:
@@ -33779,104 +34131,104 @@ aarch64_extract_operand (const aarch64_operand *self,
case 207:
case 208:
case 209:
- case 266:
- case 293:
- case 294:
+ case 210:
+ case 268:
+ case 295:
case 296:
case 298:
- case 303:
- case 304:
+ case 300:
+ case 305:
+ case 306:
return aarch64_ext_imm (self, info, code, inst, errors);
- case 51:
case 52:
- return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
case 53:
+ return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
case 54:
case 55:
- return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
case 56:
+ return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
+ case 57:
return aarch64_ext_shll_imm (self, info, code, inst, errors);
- case 59:
- case 169:
+ case 60:
+ case 170:
return aarch64_ext_fpimm (self, info, code, inst, errors);
- case 77:
- case 177:
- return aarch64_ext_limm (self, info, code, inst, errors);
case 78:
- return aarch64_ext_aimm (self, info, code, inst, errors);
+ case 178:
+ return aarch64_ext_limm (self, info, code, inst, errors);
case 79:
- return aarch64_ext_imm_half (self, info, code, inst, errors);
+ return aarch64_ext_aimm (self, info, code, inst, errors);
case 80:
+ return aarch64_ext_imm_half (self, info, code, inst, errors);
+ case 81:
return aarch64_ext_fbits (self, info, code, inst, errors);
- case 82:
case 83:
- case 174:
- return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 84:
- case 173:
case 175:
- return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
+ return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
case 85:
+ case 174:
+ case 176:
+ return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
case 86:
+ case 87:
return aarch64_ext_cond (self, info, code, inst, errors);
- case 92:
- case 101:
- return aarch64_ext_addr_simple (self, info, code, inst, errors);
case 93:
- return aarch64_ext_addr_regoff (self, info, code, inst, errors);
+ case 102:
+ return aarch64_ext_addr_simple (self, info, code, inst, errors);
case 94:
+ return aarch64_ext_addr_regoff (self, info, code, inst, errors);
case 95:
case 96:
- case 98:
- case 100:
- return aarch64_ext_addr_simm (self, info, code, inst, errors);
case 97:
- return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
case 99:
+ case 101:
+ return aarch64_ext_addr_simm (self, info, code, inst, errors);
+ case 98:
+ return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
+ case 100:
return aarch64_ext_addr_uimm12 (self, info, code, inst, errors);
- case 102:
- return aarch64_ext_addr_offset (self, info, code, inst, errors);
case 103:
- return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
+ return aarch64_ext_addr_offset (self, info, code, inst, errors);
case 104:
+ return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
case 105:
- return aarch64_ext_sysreg (self, info, code, inst, errors);
case 106:
- return aarch64_ext_pstatefield (self, info, code, inst, errors);
+ return aarch64_ext_sysreg (self, info, code, inst, errors);
case 107:
+ return aarch64_ext_pstatefield (self, info, code, inst, errors);
case 108:
case 109:
case 110:
case 111:
case 112:
- return aarch64_ext_sysins_op (self, info, code, inst, errors);
case 113:
- case 115:
- return aarch64_ext_barrier (self, info, code, inst, errors);
+ return aarch64_ext_sysins_op (self, info, code, inst, errors);
case 114:
- return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors);
case 116:
+ return aarch64_ext_barrier (self, info, code, inst, errors);
+ case 115:
+ return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors);
+ case 117:
return aarch64_ext_prfop (self, info, code, inst, errors);
- case 120:
+ case 121:
return aarch64_ext_hint (self, info, code, inst, errors);
- case 125:
case 126:
- return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
case 127:
+ return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
case 128:
case 129:
case 130:
- return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 131:
- return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 132:
- return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 133:
+ return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 134:
case 135:
case 136:
- return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
case 137:
+ return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
case 138:
case 139:
case 140:
@@ -33891,8 +34243,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 149:
case 150:
case 151:
- return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
case 152:
+ return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
case 153:
case 154:
case 155:
@@ -33900,117 +34252,119 @@ aarch64_extract_operand (const aarch64_operand *self,
case 157:
case 158:
case 159:
- return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
case 160:
+ return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
case 161:
case 162:
case 163:
- return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
case 164:
- return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
case 165:
- return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
case 166:
- return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 167:
- return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 168:
+ return aarch64_ext_sve_aimm (self, info, code, inst, errors);
+ case 169:
return aarch64_ext_sve_asimm (self, info, code, inst, errors);
- case 170:
- return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
case 171:
- return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
case 172:
+ return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
+ case 173:
return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
- case 176:
+ case 177:
return aarch64_ext_inv_limm (self, info, code, inst, errors);
- case 178:
+ case 179:
return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
- case 180:
+ case 181:
return aarch64_ext_sve_scale (self, info, code, inst, errors);
- case 196:
case 197:
case 198:
- return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 199:
+ return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 200:
case 201:
- case 279:
+ case 202:
+ case 281:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
- case 214:
case 215:
case 216:
case 217:
- return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
case 218:
+ return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors);
case 219:
case 220:
case 221:
+ case 222:
return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors);
- case 229:
case 230:
- case 232:
+ case 231:
case 233:
case 234:
case 235:
case 236:
- return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
+ case 237:
case 238:
+ return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
+ case 240:
return aarch64_ext_sve_index_imm (self, info, code, inst, errors);
- case 239:
+ case 241:
return aarch64_ext_sve_index (self, info, code, inst, errors);
- case 240:
case 242:
- case 259:
- return aarch64_ext_sve_reglist (self, info, code, inst, errors);
- case 243:
case 244:
+ case 261:
+ return aarch64_ext_sve_reglist (self, info, code, inst, errors);
+ case 245:
case 246:
- case 247:
case 248:
case 249:
- case 258:
- return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
case 250:
case 251:
+ case 260:
+ return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
+ case 252:
+ case 253:
return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
- case 254:
case 256:
- case 267:
+ case 258:
+ case 269:
return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
- case 255:
case 257:
+ case 259:
return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 268:
- case 269:
case 270:
case 271:
case 272:
case 273:
case 274:
- return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 275:
- return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 276:
- return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
case 277:
- return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 278:
+ return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ case 279:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 280:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
- case 300:
- case 301:
case 302:
+ case 303:
+ case 304:
return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
- case 305:
- case 306:
case 307:
- return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
case 308:
case 309:
+ return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors);
case 310:
case 311:
- return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 312:
+ case 313:
+ return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 314:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
@@ -63,6 +63,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"},
+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V7"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm1_14}, "a SIMD vector without a type qualifier encoding a bit index"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm2_13}, "a SIMD vector without a type qualifier encoding a bit index"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm3_12}, "a SIMD vector without a type qualifier encoding a bit index"},
@@ -258,6 +259,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_imm4", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5, FLD_SVE_imm4}, "an 4bit indexed SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},