x86: simplify VexVVVV_SRC2 handling for the XOP case
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Commit Message
As already suggested during review, rather than having an extra
conditional in build_modrm_byte() (a code path used for quite a few
more insns, including even certain GPR ones), adjust the attribute in
the installed template to properly describe things with operands
swapped.
---
I think we could even omit the conditional in match_template(), as all
other insns where XOP.W / VEX.W controls operand order are Src1VVVV
anyway. Opinions?
Comments
> As already suggested during review, rather than having an extra conditional in
> build_modrm_byte() (a code path used for quite a few more insns, including
> even certain GPR ones), adjust the attribute in the installed template to
> properly describe things with operands swapped.
Agreed, putting special handlings together makes it easier to understand.
> ---
> I think we could even omit the conditional in match_template(), as all other
> insns where XOP.W / VEX.W controls operand order are Src1VVVV anyway.
> Opinions?
>
Yes, since we change i.tm.opcode_modifier.vexw, i.tm.opcode_modifier.vexvvvv should also be changed together without any conditions.
Lili.
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -9255,6 +9255,10 @@ match_template (char mnem_suffix)
> flipping VEX.W. */
> i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1;
>
> + /* In 3-operand insns XOP.W changes which operand goes into XOP.vvvv.
> */
> + if (i.tm.opcode_modifier.vexvvvv == VexVVVV_SRC2)
> + i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
> +
> swap_first_2:
> j = i.tm.operand_types[0].bitfield.imm8;
> i.tm.operand_types[j] = operand_types[j + 1]; @@ -10441,15 +10445,8
> @@ build_modrm_byte (void)
> {
> /* VEX.vvvv encodes the last source register operand. */
> case VexVVVV_SRC2:
> - if (source != op)
> - {
> - v = source++;
> - break;
> - }
> - /* For vprot*, vpshl*, and vpsha*, XOP.W controls the swapping of src1
> - and src2, and it requires fall through when the operands are swapped.
> - */
> - /* Fall through. */
> + v = source++;
> + break;
> /* VEX.vvvv encodes the first source register operand. */
> case VexVVVV_SRC1:
> v = dest - 1;
@@ -9255,6 +9255,10 @@ match_template (char mnem_suffix)
flipping VEX.W. */
i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1;
+ /* In 3-operand insns XOP.W changes which operand goes into XOP.vvvv. */
+ if (i.tm.opcode_modifier.vexvvvv == VexVVVV_SRC2)
+ i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
+
swap_first_2:
j = i.tm.operand_types[0].bitfield.imm8;
i.tm.operand_types[j] = operand_types[j + 1];
@@ -10441,15 +10445,8 @@ build_modrm_byte (void)
{
/* VEX.vvvv encodes the last source register operand. */
case VexVVVV_SRC2:
- if (source != op)
- {
- v = source++;
- break;
- }
- /* For vprot*, vpshl*, and vpsha*, XOP.W controls the swapping of src1
- and src2, and it requires fall through when the operands are swapped.
- */
- /* Fall through. */
+ v = source++;
+ break;
/* VEX.vvvv encodes the first source register operand. */
case VexVVVV_SRC1:
v = dest - 1;