mbox series

[v3,0/11] aarch64: Fix the FEAT_SVE2p1 related issues.

Message ID 20240621113654.2079200-1-srinath.parvathaneni@arm.com
Headers
Series aarch64: Fix the FEAT_SVE2p1 related issues. |

Message

Srinath Parvathaneni June 21, 2024, 11:36 a.m. UTC 
  Hi,

The FEAT_SVE2p1 related issues were reported here [1] and I have posted
few patches to fix those issues [2].

This patch series is the re-spin of those patches in [2], splitting them and
also addresssing other issues like adding extra tests for FEAT_SVE2p1
instructions and fix FEAT_B16B16 sve2 instruction constraints.

[1] https://sourceware.org/pipermail/binutils/2024-February/132408.html
[2] https://sourceware.org/pipermail/binutils/2024-February/132636.html

Version v1 - > v2:

Srinath Parvathaneni (11):
[PATCH v1 1/11][Binutils] aarch64: Enable mandatory feature bits for v9.4-A.
   Enables FEAT_SVE2p1 for Armv9.4-A architecture by default.

[PATCH v2 2/11][Binutils] aarch64: Fix sve2p1 dupq instruction operands.
   Fixes the syntax of sve2p1 "dupq" instruction.
  
   Changes from v1 - > v2:
   Version1 of this patch is posted here:
   https://sourceware.org/pipermail/binutils/2024-February/132636.html

   - This patch addresses the comment to split dupq and extq instruction fixes
     to separate patches (4/11).
   - Enabling FEAT_SVE2p1 for Armv9.4-A architecture by default is moved to
     separate patch (1/11).
   - insert_all_fields_after/extract_all_fields_after is used instead of
     insert_fields/extract_fields to avoid access code changes.
   - case sve_index1: is removed.
   - aarch64_ext_sve_index_imm and -aarch64_ins_sve_index_imm functions are
     removed.
  
[PATCH v1 3/11][Binutils] aarch64: Fix sve2p1 dupq instruction operands (regenerated
    files).
   Auto generated opcode/aarch64-*-2.c files after fixing sve2p1 "dupq" instruction.

[PATCH v1 4/11][Binutils] aarch64: Fix sve2p1 extq instruction operands.
   Fixes the syntax of sve2p1 "extq" instruction.

[PATCH v1 5/11][Binutils] aarch64: Fix sve2p1 extq instruction operands (regenerated
    files).
   Auto generated opcode/aarch64-*-2.c files after fixing sve2p1 "extq" instruction.

[PATCH v2 6/11][Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.
   Fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q.
 
   Changes from v1->v2:
   Version1 of this patch is posted here:
   https://sourceware.org/pipermail/binutils/2024-February/132637.html

   - Added tests for the non-wrapping sequence of registers and shorter form.
   - For the above mentioned forms, the following is the preferred disassembly.
     For all the above form of instructions the hyphenated form is preferred for
     disassembly if there are more than one register in the list, and the
     register numbers are monotonically increasing in increments of one.

[PATCH v1 7/11][Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands
    (regenerated files).
   Auto generated opcode/aarch64-*-2.c files after fixing sve2p1 "ld[1-4]q/st[1-4]q"
   instruction.

[PATCH v1 8/11][BINUTILS] aarch64: Fix the wrong constraint used for sve2p1 instructions.
   As per the spec following instruction does not immediately preceded in program order by a
   MOVPRFX instruction and the issue is fixed in this patch.

   List of instructions updated: addqv, andqv, smaxqv, sminqv, umaxqv, uminqv,
                                 eorqv, faddqv, fmaxnmqv,fmaxqv, fminnmqv and fminqv.

[PATCH v1 9/11][Binutils] aarch64: Add extra tests for sve2p1 min max instructions.
    This patch adds some extra tests for the sve2p1 "addqv, andqv, smaxqv,
    sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv and
    fminqv" instructions.

[PATCH v1 10/11][Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
   This patch adds missing contraints to FEAT_B16B16 sve2 instructions
   bfclamp, bfmla and bfmls and add negative tests for all the bfloat
   instructions.

[PATCH v1 11/11][Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints
    (regenerated files).
   Auto generated opcode/aarch64-*-2.c files after fixing FEAT_B16B16 sve2 instructions.

Version v2 - > v3:

Srinath Parvathaneni (11):
[PATCH v2 1/11][Binutils] aarch64: Enable mandatory feature bits for v9.4-A.
   No changes.

[PATCH v3 2/11][Binutils] aarch64: Fix sve2p1 dupq instruction operands.
   Fixes the syntax of sve2p1 "dupq" instruction.
  
   Changes from v2 - > v3:
   > While moving (and extending) these into a separate testcase may be fine, the
     removal from sve2p1-1-bad.l is not accompanied by a similar addition elsewhere.
     Is that intentional / desirable?
   - Reverted the sve2p1-bad.l changes, also update sve2p1-1.d accordingly.
  
[PATCH v3 3/11][Binutils] aarch64: Fix sve2p1 dupq instruction operands (regenerated
    files).
   Update Auto generated files.

[PATCH v3 4/11][Binutils] aarch64: Fix sve2p1 extq instruction operands.
   Fixes the syntax of sve2p1 "extq" instruction.

   Changes from v2 - > v3:
   > Since here you remove the sole user of SVE_Zm_imm4, shouldn't that operand
     type then also be purged (much like you did in patch 2)?
   - Removed AARCH64_OPND_SVE_Zm_imm4 operand, also reverted the sve2p1-bad.l changes
     and updated sve2p1-1.d accordingly.

[PATCH v3 5/11][Binutils] aarch64: Fix sve2p1 extq instruction operands (regenerated
    files).
   Update Auto generated files.

[PATCH v3 6/11][Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands.
   Fixes encoding and syntax for sve2p1 instructions ld[1-4]q/st[1-4]q.
 
   Changes from v2->v3:
  > +.*:    c41fa000         ld1q    {z0.q}, p0/z, \[z0.d, xzr\]
    The specification for this says
    LD1Q { <Zt>.Q }, <Pg>/Z, [<Zn>.D{, <Xm>}]
    and further says that Xm defaults to Xzr when omitted.  So I would have thought the
    preferred disassembly for this case would be to omit the zero register,
    giving ld1q    {z0.q}, p0/z, [z0.d] as the output.
  - Since {, <Xm>} is optional, I have dropped the index from the disassembly in both
    of the following cases.
    ld1q    {z0.q}, p0/z, [z0.d, xzr]
    ld1q    {z0.q}, p0/z, [z0.d]
    And for both the above cases, the disassembly is as below:
    ld1q    {z0.q}, p0/z, [z0.d]

  > On a related note, I think we need a parsing test for the omitted argument as well, so:
    +ld1q { Z0.Q }, P0/Z, [Z0.D, xzr]
    +ld1q { Z0.Q }, P0/Z, [Z0.D]
  - Added the mentioned tests.

  > A similar issue for disassembly with this case:
    +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  #0, MUL VL]
    and the other (ld3q/ld4q) cases.
  - When immediate is zero, following is the preferred disassembly
    (even for ld3q/ld4q and st2q/st3q/st4q),:
    ld2q {Z0.Q, Z1.Q}, p0/Z, [x0] 

  > When the immediate is 0, we should also test
    +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0]
    (we do disassemble to this form, I see)
  - Added the requested test.

  > +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  x30, LSL  #4]
    I think it would be better to test for
    +ld2q {Z0.Q, Z1.Q}, p0/Z, [x0,  xzr, LSL  #4]
    Here as that tests all the bits of the Rm field.
  - Well this change is dropped as the current behavior is current,
    but I have made changes to the 3rd operand in ld[2-4]q/st[2-4]q instructions:
    For ld2q replaced SVE_ADDR_RR_LSL2 with SVE_ADDR_RX_LSL2
    For ld3q replaced SVE_ADDR_RR_LSL3 with SVE_ADDR_RX_LSL3
    For ld4q replaced SVE_ADDR_RR_LSL4 with SVE_ADDR_RX_LSL4 (created a new operand in this case)
    For st2q replaced SVE_ADDR_RR_LSL2 with SVE_ADDR_RX_LSL2
    For st3q replaced SVE_ADDR_RR_LSL3 with SVE_ADDR_RX_LSL3
    For st4q replaced SVE_ADDR_RR_LSL4 with SVE_ADDR_RX_LSL4
    This change is made so that "xzr" as index is rejected by the assembler
    and also added relevant negative tests.

[PATCH v3 7/11][Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands
    (regenerated files).
   Update Auto generated files.

[PATCH v1 8/11][BINUTILS] aarch64: Fix the wrong constraint used for sve2p1 instructions.
   No changes.

[PATCH v1 9/11][Binutils] aarch64: Add extra tests for sve2p1 min max instructions.
   No changes.

[PATCH v3 10/11][Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints.
   This patch adds missing contraints to FEAT_B16B16 sve2 instructions
   bfclamp, bfmla and bfmls and add negative tests for all the bfloat
   instructions.

   Changes from v2->v3:
   > It doesn't seem right to me that a test that is supposedly checking for invalid operand
     combinations would be reporting unsupported instructions.  Perhaps these should be in a
     separate test with different command-line options?
   - The negative testcase bfloat16-invalid.* tests that the instructions fail with
     "selected processor does not support" error in case of +b16b16 flag is not being passed.
     But for that error message to be triggered we need use instruction with valid operands.
     These tests are  modified so that "selected processor does not support" is generated by the
     assembler.

   - Also bfloat16-invalid.* testcases are renamed to bfloat16-1-invalid.l, bfloat16-1-invalid.s
     and bfloat16-1-invalid.d to maintain consistency in the testsuite.

   - bfloat16-2-invalid.* testcase includes the wrong operands bfloat16 tests.

[PATCH v3 11/11][Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints
    (regenerated files).
   Update Auto generated files.

Regards,
Srinath

 gas/config/tc-aarch64.c                       |   6 +-
 .../gas/aarch64/bfloat16-1-invalid.d          |   4 +
 .../gas/aarch64/bfloat16-1-invalid.l          |  11 +
 .../gas/aarch64/bfloat16-1-invalid.s          |  10 +
 gas/testsuite/gas/aarch64/bfloat16-1.d        |   6 +
 gas/testsuite/gas/aarch64/bfloat16-1.s        |   7 +-
 .../gas/aarch64/bfloat16-2-invalid.d          |   4 +
 .../gas/aarch64/bfloat16-2-invalid.l          | 265 ++++++++++++++++++
 .../gas/aarch64/bfloat16-2-invalid.s          | 147 ++++++++++
 gas/testsuite/gas/aarch64/bfloat16-bad.l      |   3 +
 gas/testsuite/gas/aarch64/bfloat16-invalid.d  |   4 -
 gas/testsuite/gas/aarch64/bfloat16-invalid.l  |   8 -
 gas/testsuite/gas/aarch64/bfloat16-invalid.s  |  13 -
 gas/testsuite/gas/aarch64/illegal-sve2.l      |  52 ++--
 gas/testsuite/gas/aarch64/sme-5-illegal.l     |   8 +-
 gas/testsuite/gas/aarch64/sme-6-illegal.l     |   8 +-
 gas/testsuite/gas/aarch64/sve2.d              |  76 ++---
 gas/testsuite/gas/aarch64/sve2p1-1-bad.d      |   2 +-
 gas/testsuite/gas/aarch64/sve2p1-1-bad.l      | 177 ++++++------
 gas/testsuite/gas/aarch64/sve2p1-1-invalid.d  |   4 +
 gas/testsuite/gas/aarch64/sve2p1-1-invalid.l  | 101 +++++++
 gas/testsuite/gas/aarch64/sve2p1-1-invalid.s  |  26 ++
 gas/testsuite/gas/aarch64/sve2p1-1.d          | 193 ++++++-------
 gas/testsuite/gas/aarch64/sve2p1-1.s          | 178 ++++++------
 gas/testsuite/gas/aarch64/sve2p1-2-bad.d      |   4 +
 gas/testsuite/gas/aarch64/sve2p1-2-bad.l      |   2 +
 gas/testsuite/gas/aarch64/sve2p1-2-invalid.d  |   3 +
 gas/testsuite/gas/aarch64/sve2p1-2-invalid.l  |  47 ++++
 gas/testsuite/gas/aarch64/sve2p1-2-invalid.s  |  10 +
 gas/testsuite/gas/aarch64/sve2p1-2.d          |  34 +++
 gas/testsuite/gas/aarch64/sve2p1-2.s          |  28 ++
 gas/testsuite/gas/aarch64/sve2p1-3-bad.d      |   3 +
 gas/testsuite/gas/aarch64/sve2p1-3-bad.l      | 208 ++++++++++++++
 gas/testsuite/gas/aarch64/sve2p1-3-bad.s      |  59 ++++
 gas/testsuite/gas/aarch64/sve2p1-3-invalid.d  |   3 +
 gas/testsuite/gas/aarch64/sve2p1-3-invalid.l  |  17 ++
 gas/testsuite/gas/aarch64/sve2p1-3-invalid.s  |  16 ++
 gas/testsuite/gas/aarch64/sve2p1-3.d          |  20 ++
 gas/testsuite/gas/aarch64/sve2p1-3.s          |  12 +
 gas/testsuite/gas/aarch64/sve2p1-4-invalid.d  |   3 +
 gas/testsuite/gas/aarch64/sve2p1-4-invalid.l  | 122 ++++++++
 gas/testsuite/gas/aarch64/sve2p1-4-invalid.s  | 125 +++++++++
 gas/testsuite/gas/aarch64/sve2p1-4.d          | 152 ++++++++++
 gas/testsuite/gas/aarch64/sve2p1-4.s          | 155 ++++++++++
 gas/testsuite/gas/aarch64/sve2p1-nosve2.s     |   1 +
 include/opcode/aarch64.h                      |  11 +-
 opcodes/aarch64-asm-2.c                       | 153 +++++-----
 opcodes/aarch64-asm.c                         |  19 +-
 opcodes/aarch64-asm.h                         |   1 -
 opcodes/aarch64-dis-2.c                       | 170 ++++++-----
 opcodes/aarch64-dis.c                         |  36 +--
 opcodes/aarch64-dis.h                         |   1 -
 opcodes/aarch64-opc-2.c                       |  10 +-
 opcodes/aarch64-opc.c                         |  91 +++---
 opcodes/aarch64-tbl.h                         | 133 +++++----
 55 files changed, 2249 insertions(+), 713 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/bfloat16-1-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/bfloat16-1-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/bfloat16-1-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/bfloat16-2-invalid.s
 delete mode 100644 gas/testsuite/gas/aarch64/bfloat16-invalid.d
 delete mode 100644 gas/testsuite/gas/aarch64/bfloat16-invalid.l
 delete mode 100644 gas/testsuite/gas/aarch64/bfloat16-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-1-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-1-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-1-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-bad.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-bad.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-2.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-bad.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-bad.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-bad.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-3.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.l
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4-invalid.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4.d
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-4.s
 create mode 100644 gas/testsuite/gas/aarch64/sve2p1-nosve2.s