mbox series

[0/2] Support APX zero-upper

Message ID 20240515063158.3960697-1-lili.cui@intel.com
Headers
Series Support APX zero-upper |

Message

Cui, Lili May 15, 2024, 6:31 a.m. UTC 
  A bug was found when adding operand %ah to an invalid test case, so patch 1/2 was added to fix it. And made the following changes to the old patch.

 1. Removed two redundant judgment codes in zu.
 2. Added various types of register sizes in invalid test cases (found a bug about AH/BH/CH/DH).
 3. Removed IMUL_Fixup and added a macros 'ZU' for imul and setcc in EVEX format.
 4. Added VexWIG to EVEX format setzu/set to remove an ugly judgement.
 5. Added more test cases for imulzu and setzu.

*** BLURB HERE ***

Cui, Lili (2):
  Add check for 8-bit old registers in EVEX format
  Support APX zero-upper

 gas/config/tc-i386.c                         |  17 ++-
 gas/testsuite/gas/i386/x86-64-apx-inval.l    |   3 +
 gas/testsuite/gas/i386/x86-64-apx-inval.s    |   2 +
 gas/testsuite/gas/i386/x86-64-apx-zu-intel.d |  78 +++++++++++++
 gas/testsuite/gas/i386/x86-64-apx-zu-inval.l |  25 +++++
 gas/testsuite/gas/i386/x86-64-apx-zu-inval.s |  28 +++++
 gas/testsuite/gas/i386/x86-64-apx-zu.d       |  78 +++++++++++++
 gas/testsuite/gas/i386/x86-64-apx-zu.s       |  73 ++++++++++++
 gas/testsuite/gas/i386/x86-64.exp            |   3 +
 opcodes/i386-dis-evex-prefix.h               | 112 +++++++++++++++++++
 opcodes/i386-dis-evex.h                      |  36 +++---
 opcodes/i386-dis.c                           |  35 ++++++
 opcodes/i386-gen.c                           |   1 +
 opcodes/i386-opc.h                           |   4 +
 opcodes/i386-opc.tbl                         |   6 +
 15 files changed, 481 insertions(+), 20 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-zu-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-zu-inval.l
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-zu-inval.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-zu.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-apx-zu.s