diff mbox series

[v3] RISC-V: Minimal support for svvptc extension.

Message ID 20241122051346.11171-1-chendongyan@isrc.iscas.ac.cn
State Committed
Commit e4f4b2dc08b6720acab563db48fd4b0427d2b0c6
Headers
Series [v3] RISC-V: Minimal support for svvptc extension. |

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Commit Message

chendongyan Nov. 22, 2024, 5:13 a.m. UTC 
  This patch support svvptc extension[1].
To enable GCC to recognize and process svvptc extension correctly at compile time.

[1] https://github.com/riscv/riscv-svvptc

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: New extension.
	* common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto.
	* config/riscv/riscv.opt: New mask.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-44.c: New test.

add svvptc testsuite
---
 gcc/common/config/riscv/riscv-common.cc       | 2 ++
 gcc/common/config/riscv/riscv-ext-bitmask.def | 1 +
 gcc/config/riscv/riscv.opt                    | 2 ++
 gcc/testsuite/gcc.target/riscv/arch-44.c      | 5 +++++
 4 files changed, 10 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-44.c

Comments

Kito Cheng Nov. 22, 2024, 5:41 a.m. UTC | #1 
LGTM, will commit to trunk once I pass the local test :)

On Fri, Nov 22, 2024 at 1:15 PM Dongyan Chen
<chendongyan@isrc.iscas.ac.cn> wrote:
>
> This patch support svvptc extension[1].
> To enable GCC to recognize and process svvptc extension correctly at compile time.
>
> [1] https://github.com/riscv/riscv-svvptc
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.cc: New extension.
>         * common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto.
>         * config/riscv/riscv.opt: New mask.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/arch-44.c: New test.
>
> add svvptc testsuite
> ---
>  gcc/common/config/riscv/riscv-common.cc       | 2 ++
>  gcc/common/config/riscv/riscv-ext-bitmask.def | 1 +
>  gcc/config/riscv/riscv.opt                    | 2 ++
>  gcc/testsuite/gcc.target/riscv/arch-44.c      | 5 +++++
>  4 files changed, 10 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-44.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
> index b0e49eb82c0..199b449a22f 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -405,6 +405,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"svvptc",  ISA_SPEC_CLASS_NONE, 1, 0},
>
>    {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
>    {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1720,6 +1721,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>
>    RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL),
>    RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
> +  RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC),
>
>    RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO),
>
> diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def b/gcc/common/config/riscv/riscv-ext-bitmask.def
> index ca5df1740f3..a733533df98 100644
> --- a/gcc/common/config/riscv/riscv-ext-bitmask.def
> +++ b/gcc/common/config/riscv/riscv-ext-bitmask.def
> @@ -79,5 +79,6 @@ RISCV_EXT_BITMASK ("zcd",             1,  4)
>  RISCV_EXT_BITMASK ("zcf",              1,  5)
>  RISCV_EXT_BITMASK ("zcmop",            1,  6)
>  RISCV_EXT_BITMASK ("zawrs",            1,  7)
> +RISCV_EXT_BITMASK ("svvptc",           1,  8)
>
>  #undef RISCV_EXT_BITMASK
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index ab9d6e82723..b9e980e30f5 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -466,6 +466,8 @@ Mask(SVINVAL) Var(riscv_sv_subext)
>
>  Mask(SVNAPOT) Var(riscv_sv_subext)
>
> +Mask(SVVPTC) Var(riscv_sv_subext)
> +
>  TargetVariable
>  int riscv_ztso_subext
>
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-44.c b/gcc/testsuite/gcc.target/riscv/arch-44.c
> new file mode 100644
> index 00000000000..80dc19a7083
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-44.c
> @@ -0,0 +1,5 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_svvptc -mabi=lp64" } */
> +int foo()
> +{
> +}
> --
> 2.43.0
>
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index b0e49eb82c0..199b449a22f 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -405,6 +405,7 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svvptc",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1720,6 +1721,7 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
 
   RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL),
   RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
+  RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC),
 
   RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO),
 
diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def b/gcc/common/config/riscv/riscv-ext-bitmask.def
index ca5df1740f3..a733533df98 100644
--- a/gcc/common/config/riscv/riscv-ext-bitmask.def
+++ b/gcc/common/config/riscv/riscv-ext-bitmask.def
@@ -79,5 +79,6 @@  RISCV_EXT_BITMASK ("zcd",		1,  4)
 RISCV_EXT_BITMASK ("zcf",		1,  5)
 RISCV_EXT_BITMASK ("zcmop",		1,  6)
 RISCV_EXT_BITMASK ("zawrs",		1,  7)
+RISCV_EXT_BITMASK ("svvptc",		1,  8)
 
 #undef RISCV_EXT_BITMASK
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index ab9d6e82723..b9e980e30f5 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -466,6 +466,8 @@  Mask(SVINVAL) Var(riscv_sv_subext)
 
 Mask(SVNAPOT) Var(riscv_sv_subext)
 
+Mask(SVVPTC) Var(riscv_sv_subext)
+
 TargetVariable
 int riscv_ztso_subext
 
diff --git a/gcc/testsuite/gcc.target/riscv/arch-44.c b/gcc/testsuite/gcc.target/riscv/arch-44.c
new file mode 100644
index 00000000000..80dc19a7083
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-44.c
@@ -0,0 +1,5 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_svvptc -mabi=lp64" } */
+int foo()
+{
+}