[03/12] RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor extension
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Commit Message
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds configuration-setting instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: New test.
* testsuite/gas/riscv/x-thead-vector.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VSETVL): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise..
---
gas/testsuite/gas/riscv/x-thead-vector.d | 12 ++++++++++++
gas/testsuite/gas/riscv/x-thead-vector.s | 3 +++
include/opcode/riscv-opc.h | 5 +++++
opcodes/riscv-opc.c | 4 ++++
4 files changed, 24 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d
Comments
On Fri, Nov 10, 2023 at 3:22 PM Jin Ma <jinma@linux.alibaba.com> wrote:
> T-Head has a range of vendor-specific instructions.
> Therefore it makes sense to group them into smaller chunks
> in form of vendor extensions.
>
> This patch adds configuration-setting instructions for the "XTheadVector"
> extension. The 'th' prefix and the "XTheadVector" extension are documented
> in a PR for the RISC-V toolchain conventions ([1]).
>
> [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
>
> Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
>
> gas/ChangeLog:
>
> * testsuite/gas/riscv/x-thead-vector.d: New test.
> * testsuite/gas/riscv/x-thead-vector.s: New test.
>
> include/ChangeLog:
>
> * opcode/riscv-opc.h (MATCH_TH_VSETVL): New.
>
> opcodes/ChangeLog:
>
> * riscv-opc.c: Likewise..
> ---
> gas/testsuite/gas/riscv/x-thead-vector.d | 12 ++++++++++++
> gas/testsuite/gas/riscv/x-thead-vector.s | 3 +++
> include/opcode/riscv-opc.h | 5 +++++
> opcodes/riscv-opc.c | 4 ++++
> 4 files changed, 24 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d
>
> diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d
> b/gas/testsuite/gas/riscv/x-thead-vector.d
> new file mode 100644
> index 00000000000..e509ed0971b
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-thead-vector.d
> @@ -0,0 +1,12 @@
> +#as: -march=rv32if_xtheadvector
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
> +[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+th.vsetvl[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,tu,mu
> +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+th.vsetvli[ ]+a0,a1,2047
> diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s
> b/gas/testsuite/gas/riscv/x-thead-vector.s
> index e69de29bb2d..ffea0a6f9f9 100644
> --- a/gas/testsuite/gas/riscv/x-thead-vector.s
> +++ b/gas/testsuite/gas/riscv/x-thead-vector.s
> @@ -0,0 +1,3 @@
> + th.vsetvl a0, a1, a2
> + th.vsetvli a0, a1, 0
> + th.vsetvli a0, a1, 0x7ff
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index ed29384e825..dc18dd9f04c 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2648,6 +2648,11 @@
> #define MASK_TH_SYNC_IS 0xffffffff
> #define MATCH_TH_SYNC_S 0x0190000b
> #define MASK_TH_SYNC_S 0xffffffff
> +/* Vendor-specific (T-Head) XTheadVector instructions. */
> +#define MATCH_TH_VSETVL 0x80007057
> +#define MASK_TH_VSETVL 0xfe00707f
> +#define MATCH_TH_VSETVLI 0x00007057
> +#define MASK_TH_VSETVLI 0x8000707f
>
Seems like the whole t-head vector instructions will have the same
encodings as standard vector ones. Could we just use MATCH/MASK_VSETVL to
replace MATCH/MASK_TH_VSETVL, and for all related vendor instructions?
Thanks
Nelson
> /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
> #define MATCH_VT_MASKC 0x607b
> #define MASK_VT_MASKC 0xfe00707f
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 72d727cd77e..2fb7cf1e14a 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -2234,6 +2234,10 @@ const struct riscv_opcode riscv_opcodes[] =
> {"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS,
> MASK_TH_SYNC_IS, match_opcode, 0},
> {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S,
> MASK_TH_SYNC_S, match_opcode, 0},
>
> +/* Vendor-specific (T-Head) XTheadVector instructions. */
> +{"th.vsetvl", 0, INSN_CLASS_XTHEADVECTOR, "d,s,t", MATCH_TH_VSETVL,
> MASK_TH_VSETVL, match_opcode, 0},
> +{"th.vsetvli", 0, INSN_CLASS_XTHEADVECTOR, "d,s,Vc",
> MATCH_TH_VSETVLI, MASK_TH_VSETVLI, match_opcode, 0},
> +
> /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
> {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC,
> MASK_VT_MASKC, match_opcode, 0 },
> {"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN,
> MASK_VT_MASKCN, match_opcode, 0 },
> --
> 2.17.1
>
>
> Seems like the whole t-head vector instructions will have the same
> encodings as standard vector ones. Could we just use MATCH/MASK_VSETVL to
> replace MATCH/MASK_TH_VSETVL, and for all related vendor instructions?
>
> Thanks
> Nelson
>
Hi, Nelson
I am very honored to see your review and reply to this patch set. I think your
comment is very good. I will revise the patch and send a new patch set later. Any
other comments on the patches for the XTheadVector extension?
BR
Jin
new file mode 100644
@@ -0,0 +1,12 @@
+#as: -march=rv32if_xtheadvector
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+th.vsetvl[ ]+a0,a1,a2
+[ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,tu,mu
+[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+th.vsetvli[ ]+a0,a1,2047
@@ -0,0 +1,3 @@
+ th.vsetvl a0, a1, a2
+ th.vsetvli a0, a1, 0
+ th.vsetvli a0, a1, 0x7ff
@@ -2648,6 +2648,11 @@
#define MASK_TH_SYNC_IS 0xffffffff
#define MATCH_TH_SYNC_S 0x0190000b
#define MASK_TH_SYNC_S 0xffffffff
+/* Vendor-specific (T-Head) XTheadVector instructions. */
+#define MATCH_TH_VSETVL 0x80007057
+#define MASK_TH_VSETVL 0xfe00707f
+#define MATCH_TH_VSETVLI 0x00007057
+#define MASK_TH_VSETVLI 0x8000707f
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
#define MATCH_VT_MASKC 0x607b
#define MASK_VT_MASKC 0xfe00707f
@@ -2234,6 +2234,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS, match_opcode, 0},
{"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0},
+/* Vendor-specific (T-Head) XTheadVector instructions. */
+{"th.vsetvl", 0, INSN_CLASS_XTHEADVECTOR, "d,s,t", MATCH_TH_VSETVL, MASK_TH_VSETVL, match_opcode, 0},
+{"th.vsetvli", 0, INSN_CLASS_XTHEADVECTOR, "d,s,Vc", MATCH_TH_VSETVLI, MASK_TH_VSETVLI, match_opcode, 0},
+
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
{"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },