[v6,1/2] x86: Add comment explaining no Slow_SSE4_2 check in ifunc-sse4_2
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dj/TryBot-apply_patch |
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Patch applied to master at the time it was sent
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Commit Message
Just for clarities sake and so that if a future implementation is
added we remember to add the check.
---
sysdeps/x86_64/multiarch/ifunc-sse4_2.h | 4 ++++
1 file changed, 4 insertions(+)
Comments
On Jun 29 2022, Noah Goldstein via Libc-alpha wrote:
> diff --git a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
> index ee36525bcf..4eb9cca7f0 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
> +++ b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
> @@ -27,6 +27,10 @@ IFUNC_SELECTOR (void)
> {
> const struct cpu_features* cpu_features = __get_cpu_features ();
>
> + /* This function uses slow sse4.2 instructions (pcmpstri) but since
> + there is no other optimized implementation keep using. If an
I think there is something missing at the end of the sentence.
On Thu, Jun 30, 2022 at 12:47 AM Andreas Schwab <schwab@suse.de> wrote:
>
> On Jun 29 2022, Noah Goldstein via Libc-alpha wrote:
>
> > diff --git a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
> > index ee36525bcf..4eb9cca7f0 100644
> > --- a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
> > +++ b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
> > @@ -27,6 +27,10 @@ IFUNC_SELECTOR (void)
> > {
> > const struct cpu_features* cpu_features = __get_cpu_features ();
> >
> > + /* This function uses slow sse4.2 instructions (pcmpstri) but since
> > + there is no other optimized implementation keep using. If an
>
> I think there is something missing at the end of the sentence.
Fixed in V6.
>
> --
> Andreas Schwab, SUSE Labs, schwab@suse.de
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."
@@ -27,6 +27,10 @@ IFUNC_SELECTOR (void)
{
const struct cpu_features* cpu_features = __get_cpu_features ();
+ /* This function uses slow sse4.2 instructions (pcmpstri) but since
+ there is no other optimized implementation keep using. If an
+ optimized fallback is added add a X86_ISA_CPU_FEATURE_ARCH_P
+ (cpu_features, Slow_SSE4_2) check. */
if (CPU_FEATURE_USABLE_P (cpu_features, SSE4_2))
return OPTIMIZE (sse42);