diff mbox series

[v3] x86: Add more feature definitions to isa-level.h

Message ID 20220628032602.218678-1-goldstein.w.n@gmail.com
State Superseded
Headers
Series [v3] x86: Add more feature definitions to isa-level.h |

Checks

Context Check Description
dj/TryBot-apply_patch success Patch applied to master at the time it was sent
dj/TryBot-32bit success Build for i686

Commit Message

Noah Goldstein June 28, 2022, 3:26 a.m. UTC 
  This commit doesn't change anything in itself.  It is just to add
definitions that will be needed by future patches.
---
 sysdeps/x86/isa-level.h | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

H.J. Lu June 28, 2022, 3:30 a.m. UTC | #1 
On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> This commit doesn't change anything in itself.  It is just to add
> definitions that will be needed by future patches.
> ---
>  sysdeps/x86/isa-level.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> index f293aea906..443631662f 100644
> --- a/sysdeps/x86/isa-level.h
> +++ b/sysdeps/x86/isa-level.h
> @@ -71,11 +71,13 @@
>  #define AVX512F_X86_ISA_LEVEL 4
>  #define AVX512VL_X86_ISA_LEVEL 4
>  #define AVX512BW_X86_ISA_LEVEL 4
> +#define AVX512DQ_X86_ISA_LEVEL 4
>
>  /* ISA level >= 3 guaranteed includes.  */
>  #define AVX_X86_ISA_LEVEL 3
>  #define AVX2_X86_ISA_LEVEL 3
>  #define BMI2_X86_ISA_LEVEL 3
> +#define MOVBE_X86_ISA_LEVEL 3
>
>  /* NB: This feature is enabled when ISA level >= 3, which was disabled
>     for the following CPUs:
> @@ -89,6 +91,13 @@
>     when ISA level < 3.  */
>  #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
>
> +/* ISA level >= 2 guaranteed includes.  */
> +#define SSE4_2_X86_ISA_LEVEL 2
> +#define SSSE3_X86_ISA_LEVEL 2

Please move them immediately after MOVBE_X86_ISA_LEVEL.

> +/* This feature is enabled when ISA level >= 2.  */
> +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> +
>  /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
>     macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
>     runtime checks.  They differ in two ways.
> --
> 2.34.1
>
H.J. Lu June 28, 2022, 3:32 a.m. UTC | #2 
On Mon, Jun 27, 2022 at 8:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > This commit doesn't change anything in itself.  It is just to add
> > definitions that will be needed by future patches.
> > ---
> >  sysdeps/x86/isa-level.h | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > index f293aea906..443631662f 100644
> > --- a/sysdeps/x86/isa-level.h
> > +++ b/sysdeps/x86/isa-level.h
> > @@ -71,11 +71,13 @@
> >  #define AVX512F_X86_ISA_LEVEL 4
> >  #define AVX512VL_X86_ISA_LEVEL 4
> >  #define AVX512BW_X86_ISA_LEVEL 4
> > +#define AVX512DQ_X86_ISA_LEVEL 4
> >
> >  /* ISA level >= 3 guaranteed includes.  */
> >  #define AVX_X86_ISA_LEVEL 3
> >  #define AVX2_X86_ISA_LEVEL 3
> >  #define BMI2_X86_ISA_LEVEL 3
> > +#define MOVBE_X86_ISA_LEVEL 3
> >
> >  /* NB: This feature is enabled when ISA level >= 3, which was disabled
> >     for the following CPUs:
> > @@ -89,6 +91,13 @@
> >     when ISA level < 3.  */
> >  #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> >
> > +/* ISA level >= 2 guaranteed includes.  */
> > +#define SSE4_2_X86_ISA_LEVEL 2
> > +#define SSSE3_X86_ISA_LEVEL 2
>
> Please move them immediately after MOVBE_X86_ISA_LEVEL.

BTW, comments should be ended with 2 spaces after '.'.

> > +/* This feature is enabled when ISA level >= 2.  */
> > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > +
> >  /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> >     macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> >     runtime checks.  They differ in two ways.
> > --
> > 2.34.1
> >
>
>
> --
> H.J.
Noah Goldstein June 28, 2022, 3:35 a.m. UTC | #3 
On Mon, Jun 27, 2022 at 8:32 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > >
> > > This commit doesn't change anything in itself.  It is just to add
> > > definitions that will be needed by future patches.
> > > ---
> > >  sysdeps/x86/isa-level.h | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > >
> > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > index f293aea906..443631662f 100644
> > > --- a/sysdeps/x86/isa-level.h
> > > +++ b/sysdeps/x86/isa-level.h
> > > @@ -71,11 +71,13 @@
> > >  #define AVX512F_X86_ISA_LEVEL 4
> > >  #define AVX512VL_X86_ISA_LEVEL 4
> > >  #define AVX512BW_X86_ISA_LEVEL 4
> > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > >
> > >  /* ISA level >= 3 guaranteed includes.  */
> > >  #define AVX_X86_ISA_LEVEL 3
> > >  #define AVX2_X86_ISA_LEVEL 3
> > >  #define BMI2_X86_ISA_LEVEL 3
> > > +#define MOVBE_X86_ISA_LEVEL 3
> > >
> > >  /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > >     for the following CPUs:
> > > @@ -89,6 +91,13 @@
> > >     when ISA level < 3.  */
> > >  #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > >
> > > +/* ISA level >= 2 guaranteed includes.  */
> > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > +#define SSSE3_X86_ISA_LEVEL 2
> >
> > Please move them immediately after MOVBE_X86_ISA_LEVEL.


Personally I think it's clearer grouped by ISA level.

Can it remain this way?

ISA Level(N) Defaults
...

ISA Level(N) Features Enable
...

ISA Level(N - 1) Defualt
...


Think the question is more often "what's on at this ISA level"
as opposed to "what are the special features".

>
> BTW, comments should be ended with 2 spaces after '.'.

Which comment is missing?

>
> > > +/* This feature is enabled when ISA level >= 2.  */
> > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > +
> > >  /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > >     macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > >     runtime checks.  They differ in two ways.
> > > --
> > > 2.34.1
> > >
> >
> >
> > --
> > H.J.
>
>
>
> --
> H.J.
H.J. Lu June 28, 2022, 3:44 a.m. UTC | #4 
On Mon, Jun 27, 2022 at 8:36 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:32 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 8:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > > >
> > > > This commit doesn't change anything in itself.  It is just to add
> > > > definitions that will be needed by future patches.
> > > > ---
> > > >  sysdeps/x86/isa-level.h | 9 +++++++++
> > > >  1 file changed, 9 insertions(+)
> > > >
> > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > > index f293aea906..443631662f 100644
> > > > --- a/sysdeps/x86/isa-level.h
> > > > +++ b/sysdeps/x86/isa-level.h
> > > > @@ -71,11 +71,13 @@
> > > >  #define AVX512F_X86_ISA_LEVEL 4
> > > >  #define AVX512VL_X86_ISA_LEVEL 4
> > > >  #define AVX512BW_X86_ISA_LEVEL 4
> > > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > > >
> > > >  /* ISA level >= 3 guaranteed includes.  */
> > > >  #define AVX_X86_ISA_LEVEL 3
> > > >  #define AVX2_X86_ISA_LEVEL 3
> > > >  #define BMI2_X86_ISA_LEVEL 3
> > > > +#define MOVBE_X86_ISA_LEVEL 3
> > > >
> > > >  /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > > >     for the following CPUs:
> > > > @@ -89,6 +91,13 @@
> > > >     when ISA level < 3.  */
> > > >  #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > >
> > > > +/* ISA level >= 2 guaranteed includes.  */
> > > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > > +#define SSSE3_X86_ISA_LEVEL 2
> > >
> > > Please move them immediately after MOVBE_X86_ISA_LEVEL.
>
>
> Personally I think it's clearer grouped by ISA level.

ISAs are used with X86_ISA_CPU_FEATURE_USABLE_P and
features are used with X86_ISA_CPU_FEATURES_ARCH_P.
I think grouping them together is better.

> Can it remain this way?
>
> ISA Level(N) Defaults
> ...
>
> ISA Level(N) Features Enable
> ...
>
> ISA Level(N - 1) Defualt
> ...
>
>
> Think the question is more often "what's on at this ISA level"
> as opposed to "what are the special features".
>
> >
> > BTW, comments should be ended with 2 spaces after '.'.
>
> Which comment is missing?

I may be wrong.

>
> >
> > > > +/* This feature is enabled when ISA level >= 2.  */
> > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > > +
> > > >  /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > > >     macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > > >     runtime checks.  They differ in two ways.
> > > > --
> > > > 2.34.1
> > > >
> > >
> > >
> > > --
> > > H.J.
> >
> >
> >
> > --
> > H.J.
Noah Goldstein June 28, 2022, 3:50 a.m. UTC | #5 
On Mon, Jun 27, 2022 at 8:45 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 27, 2022 at 8:36 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> >
> > On Mon, Jun 27, 2022 at 8:32 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > >
> > > On Mon, Jun 27, 2022 at 8:30 PM H.J. Lu <hjl.tools@gmail.com> wrote:
> > > >
> > > > On Mon, Jun 27, 2022 at 8:26 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
> > > > >
> > > > > This commit doesn't change anything in itself.  It is just to add
> > > > > definitions that will be needed by future patches.
> > > > > ---
> > > > >  sysdeps/x86/isa-level.h | 9 +++++++++
> > > > >  1 file changed, 9 insertions(+)
> > > > >
> > > > > diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
> > > > > index f293aea906..443631662f 100644
> > > > > --- a/sysdeps/x86/isa-level.h
> > > > > +++ b/sysdeps/x86/isa-level.h
> > > > > @@ -71,11 +71,13 @@
> > > > >  #define AVX512F_X86_ISA_LEVEL 4
> > > > >  #define AVX512VL_X86_ISA_LEVEL 4
> > > > >  #define AVX512BW_X86_ISA_LEVEL 4
> > > > > +#define AVX512DQ_X86_ISA_LEVEL 4
> > > > >
> > > > >  /* ISA level >= 3 guaranteed includes.  */
> > > > >  #define AVX_X86_ISA_LEVEL 3
> > > > >  #define AVX2_X86_ISA_LEVEL 3
> > > > >  #define BMI2_X86_ISA_LEVEL 3
> > > > > +#define MOVBE_X86_ISA_LEVEL 3
> > > > >
> > > > >  /* NB: This feature is enabled when ISA level >= 3, which was disabled
> > > > >     for the following CPUs:
> > > > > @@ -89,6 +91,13 @@
> > > > >     when ISA level < 3.  */
> > > > >  #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
> > > > >
> > > > > +/* ISA level >= 2 guaranteed includes.  */
> > > > > +#define SSE4_2_X86_ISA_LEVEL 2
> > > > > +#define SSSE3_X86_ISA_LEVEL 2
> > > >
> > > > Please move them immediately after MOVBE_X86_ISA_LEVEL.
> >
> >
> > Personally I think it's clearer grouped by ISA level.
>
> ISAs are used with X86_ISA_CPU_FEATURE_USABLE_P and
> features are used with X86_ISA_CPU_FEATURES_ARCH_P.
> I think grouping them together is better.

Okay. Done in V4.

>
> > Can it remain this way?
> >
> > ISA Level(N) Defaults
> > ...
> >
> > ISA Level(N) Features Enable
> > ...
> >
> > ISA Level(N - 1) Defualt
> > ...
> >
> >
> > Think the question is more often "what's on at this ISA level"
> > as opposed to "what are the special features".
> >
> > >
> > > BTW, comments should be ended with 2 spaces after '.'.
> >
> > Which comment is missing?
>
> I may be wrong.
>
> >
> > >
> > > > > +/* This feature is enabled when ISA level >= 2.  */
> > > > > +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
> > > > > +
> > > > >  /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
> > > > >     macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
> > > > >     runtime checks.  They differ in two ways.
> > > > > --
> > > > > 2.34.1
> > > > >
> > > >
> > > >
> > > > --
> > > > H.J.
> > >
> > >
> > >
> > > --
> > > H.J.
>
>
>
> --
> H.J.
diff mbox series

Patch

diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h
index f293aea906..443631662f 100644
--- a/sysdeps/x86/isa-level.h
+++ b/sysdeps/x86/isa-level.h
@@ -71,11 +71,13 @@ 
 #define AVX512F_X86_ISA_LEVEL 4
 #define AVX512VL_X86_ISA_LEVEL 4
 #define AVX512BW_X86_ISA_LEVEL 4
+#define AVX512DQ_X86_ISA_LEVEL 4
 
 /* ISA level >= 3 guaranteed includes.  */
 #define AVX_X86_ISA_LEVEL 3
 #define AVX2_X86_ISA_LEVEL 3
 #define BMI2_X86_ISA_LEVEL 3
+#define MOVBE_X86_ISA_LEVEL 3
 
 /* NB: This feature is enabled when ISA level >= 3, which was disabled
    for the following CPUs:
@@ -89,6 +91,13 @@ 
    when ISA level < 3.  */
 #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
 
+/* ISA level >= 2 guaranteed includes.  */
+#define SSE4_2_X86_ISA_LEVEL 2
+#define SSSE3_X86_ISA_LEVEL 2
+
+/* This feature is enabled when ISA level >= 2.  */
+#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
+
 /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
    macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
    runtime checks.  They differ in two ways.