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[v2,17/18] Documentation for the RISC-V 32-bit port

Message ID 6e4924a4ef9a18a4bd80556b5edcb4be61a43e96.1591201405.git.alistair.francis@wdc.com
State New
Headers show
Series glibc port for 32-bit RISC-V (RV32) | expand

Commit Message

Alistair Francis June 3, 2020, 4:26 p.m. UTC
From: Zong Li <zongbox@gmail.com>

There is already RISC-V 64-bit port information in the documentation.
Let's add some documentation entries for the RISC-V 32-bit as well.
 NEWS   | 6 ++++++
 README | 1 +
 2 files changed, 7 insertions(+)
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diff --git a/NEWS b/NEWS
index a660fc59a8..d408c25592 100644
--- a/NEWS
+++ b/NEWS
@@ -31,6 +31,12 @@  Major new features:
   pthread_attr_getsigmask_np have been added.  They allow applications
   to specify the signal mask of a thread created with pthread_create.
+* Support RISC-V port for 32-bit. The ISA and ABI pairs supported as follows:
+    - rv32imac ilp32
+    - rv32imafdc ilp32
+    - rv32imafdc ilp32d
 Deprecated and removed features, and other changes affecting compatibility:
 * The deprecated <sys/sysctl.h> header and the sysctl function have been
diff --git a/README b/README
index 31c5da0405..cee86ab178 100644
--- a/README
+++ b/README
@@ -38,6 +38,7 @@  The GNU C Library supports these configurations for using Linux kernels:
 	powerpc64*-*-linux-gnu	Big-endian and little-endian.
+	riscv32-*-linux-gnu